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WV3EG264M64EFSU335D4MG

型号:

WV3EG264M64EFSU335D4MG

描述:

1GB - 2x64Mx64 DDR SDRAM UNBUFFERED[ 1GB - 2x64Mx64 DDR SDRAM UNBUFFERED ]

品牌:

WEDC[ WHITE ELECTRONIC DESIGNS CORPORATION ]

页数:

11 页

PDF大小:

149 K

WV3EG264M64EFSU-D4  
White Electronic Designs  
PRELIMINARY*  
1GB – 2x64Mx64 DDR SDRAM UNBUFFERED  
FEATURES  
DESCRIPTION  
PC2700 @ CL2.5  
The WV3EG264M64EFSU is a 2x64Mx64 Double Data  
Rate SDRAM memory module based on 512Mb DDR  
SDRAM component. The module consists of sixteen  
64Mx8 bit with 4 banks DDR SDRAMs in FBGApackages  
mounted on a 200 pin FR4 substrate.  
Double-data-rate architecture  
Bi-directional data strobes (DQS)  
Differential clock inputs (CK & CK#)  
Programmable Read Latency 2,2.5 (clock)  
Programmable Burst Length (2,4,8)  
Programmable Burst type (sequential & interleave)  
Auto and self refresh, (8K/64ms refresh)  
Serial presence detect  
Synchronous design allows precise cycle control with the  
use of system clock. Data I/O transactions are possible on  
both edges and Burst Lengths allow the same device to be  
useful for a variety of high bandwidth, high performance  
memory system applications.  
Power supply: VCC/VCCQ: 2.5V 0.2V  
Dual Rank  
* This product is under development, is not qualified or characterized and is subject to  
change without notice.  
Standard 200 pin SO-DIMM package  
• Package height options:  
D4: 31.75 mm (1.25”)  
NOTE: Consult factory for availability of:  
• RoHS compliant products  
• Vendor source control options  
• Industrial temperature option  
OPERATING FREQUENCIES  
DDR333 @CL=2.5  
166MHz  
Clock Speed  
CL-tRCD-tRP  
2.5-3-3  
August 2005  
Rev. 0  
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
WV3EG264M64EFSU-D4  
White Electronic Designs  
PRELIMINARY  
PIN CONFIGURATION  
PIN# SYMBOL PIN# SYMBOL PIN# SYMBOL PIN# SYMBOL  
PIN NAMES  
A0-A12  
Address input (Multiplexed)  
Bank Select Address  
Data Input/Output  
BA0-BA1  
1
VREF  
VREF  
VSS  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
100  
VSS  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
142  
143  
144  
145  
146  
147  
148  
149  
150  
A9  
151  
152  
153  
154  
155  
156  
157  
158  
159  
160  
161  
162  
163  
164  
165  
166  
167  
168  
169  
170  
171  
172  
173  
174  
175  
176  
177  
178  
179  
180  
181  
182  
183  
184  
185  
186  
187  
188  
189  
190  
191  
192  
193  
194  
195  
196  
197  
198  
199  
200  
DQ42  
DQ46  
DQ43  
DQ47  
VCC  
DQ0-DQ63  
2
VSS  
A8  
DQS0-DQS7 Data Strobe Input/Output  
3
DQ19  
DQ23  
DQ24  
DQ28  
VCC  
VSS  
CK0, CK0#  
CK1, CK1#  
Clock Input  
Clock Input  
4
VSS  
VSS  
5
DQ0  
DQ4  
DQ1  
DQ5  
VCC  
A7  
CKE0, CKE1 Clock Enable input  
6
A6  
VCC  
CS0#, CS1#  
RAS#  
CAS#  
WE#  
Chip Select Input  
Row Address Strobe  
Column Address Strobe  
Write Enable  
7
A5  
VCC  
8
VCC  
A4  
CK1#  
VSS  
9
DQ25  
DQ29  
DQS3  
DM3  
VSS  
A3  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
VCC  
A2  
CK1  
DM0-DM7  
VCC  
Data-In Mask  
DQS0  
DM0  
DQ2  
DQ6  
VSS  
A1  
VSS  
Power Supply (2.5V)  
Power Supply for DQS (2.5V)  
Ground  
A0  
VSS  
VCCQ  
VCC  
DQ48  
DQ52  
DQ49  
DQ53  
VCC  
VSS  
VSS  
VCC  
VREF  
Power Supply for Reference  
Serial EEPROM Power Supply  
(2.3V to 3.6V)  
Serial data I/O  
Serial clock  
Address in EEPROM  
No Connect  
DQ26  
DQ30  
DQ27  
DQ31  
VCC  
A10  
BA1  
BA0  
RAS#  
WE#  
CAS#  
CS0#  
CS1#  
NC  
VCCSPD  
VSS  
DQ3  
DQ7  
DQ8  
DQ12  
VCC  
SDA  
SCL  
SA0-SA2  
NC  
VCC  
DQS6  
DM6  
DQ50  
DQ54  
VSS  
VCC  
NC  
VCC  
NC  
DQ9  
DQ13  
DQS1  
DM1  
VSS  
NC  
NC  
NC  
VSS  
VSS  
VSS  
DQ51  
DQ55  
DQ56  
DQ60  
VCC  
VSS  
VSS  
NC  
DQ32  
DQ36  
DQ33  
DQ37  
VCC  
VSS  
NC  
DQ10  
DQ14  
DQ11  
DQ15  
VCC  
NC  
NC  
VCC  
VCC  
DQ57  
DQ61  
DQS7  
DM7  
VSS  
VCC  
VCC  
NC  
DQS4  
DM4  
DQ34  
DQ38  
VSS  
VCC  
CK0  
VCC  
CK0#  
VSS  
VSS  
VSS  
NC  
NC  
NC  
VSS  
VSS  
DQ58  
DQ62  
DQ59  
DQ63  
VCC  
VSS  
VSS  
NC  
DQ35  
DQ39  
DQ40  
DQ44  
VCC  
VSS  
DQ16  
DQ20  
DQ17  
DQ21  
VCC  
NC  
VCC  
VCC  
SDA  
SA0  
SCL  
SA1  
VCCSPD  
SA2  
VCC  
VCC  
VCC  
CKE1  
CKE0  
NC  
DQ41  
DQ45  
DQS5  
DM5  
VSS  
VCC  
DQS2  
DM2  
DQ18  
DQ22  
NC  
A12  
A11  
NC  
NC  
VSS  
August 2005  
Rev. 0  
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
WV3EG264M64EFSU-D4  
White Electronic Designs  
PRELIMINARY  
FUNCTIONAL BLOCK DIAGRAM  
CS1#  
CS0#  
S0#  
S0#  
S0#  
S0#  
S1#  
S1#  
S1#  
S1#  
S0#  
S0#  
S0#  
S0#  
S1#  
S1#  
S1#  
S1#  
DQS0  
DM0  
DQ0  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
DQS  
DM  
DQS  
DM  
DQS4  
DM4  
DQS  
DM  
DQS  
DM  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
DQ32  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
DQ33  
DQ34  
DQ35  
DQ36  
DQ37  
DQ38  
DQ39  
DQS1  
DM1  
DQ8  
DQ9  
DQ10  
DQ11  
DQ12  
DQ13  
DQ14  
DQ15  
DQS  
DM  
DQS  
DM  
DQS5  
DM5  
DQ40  
DQ41  
DQ42  
DQ43  
DQ44  
DQ45  
DQ46  
DQ47  
DQS  
DM  
DQS  
DM  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
DQS2  
DM2  
DQ16  
DQ17  
DQ18  
DQ19  
DQ20  
DQ21  
DQ22  
DQ23  
DQS  
DM  
DQS  
DM  
DQS6  
DM6  
DQ48  
DQ49  
DQ50  
DQ51  
DQ52  
DQ53  
DQ54  
DQ55  
DQS  
DM  
DQS  
DM  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
DQS3  
DM3  
DQ24  
DQ25  
DQ26  
DQ27  
DQ28  
DQ29  
DQ30  
DQ31  
DQS  
DM  
DQS  
DM  
DQS7  
DM7  
DQ56  
DQ57  
DQ58  
DQ59  
DQ60  
DQ61  
DQ62  
DQ63  
DQS  
DM  
DQS  
DM  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
BA0-BA1  
DDR SDRAMs  
DDR SDRAMs  
DDR SDRAMs  
DDR SDRAMs  
DDR SDRAMs  
DDR SDRAMs  
DDR SDRAMs  
Clock Wiring  
A0-A12  
RAS#  
CAS#  
WE#  
CKE0  
CKE1  
Clock  
Input  
SDRAMs  
CK0/CK0#  
CK1/CK1#  
8 SDRAMs  
8 SDRAMs  
VCCSPD  
VCC/VCCQ  
VREF  
SPD  
SERIAL PD  
A0 A1  
SA0 SA1  
SCL  
WP  
SDA  
DDR SDRAMs  
A2  
DDR SDRAMs  
DDR SDRAMs  
SA2  
VSS  
NOTE: All datalines are terminated through a 22 ohm series resistor  
August 2005  
Rev. 0  
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
WV3EG264M64EFSU-D4  
White Electronic Designs  
PRELIMINARY  
ABSOLUTE MAXIMUM RATINGS  
Parameter  
Symbol  
VIN, VOUT  
VCC  
VCCQ  
TSTG  
TA  
Value  
-0.5 to 3.3  
-1.0 to 3.6  
-1.0 to 3.6  
-55 to +150  
0 to +70  
16  
Units  
V
Voltage on any pin relative to VSS  
Voltage on VCC supply relative to VSS  
Voltage on VCCQ supply relative to VSS  
Storage Temperature  
V
V
°C  
°C  
W
Operating Temperature  
Power Dissipation  
Short Circuit Current  
PD  
IOS  
50  
mA  
Note:  
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.  
Functional operation should be restricted to recommended operating condition.  
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.  
DC CHARACTERISTICS  
0°C TA 70°C, VCC = 2.5V 0.2V  
Parameter  
Symbol  
VCC  
Min  
2.3  
Max  
2.7  
Unit  
Note  
Supply voltage DDR266/DDR333 (nominal VCC of 2.5V)  
I/O Supply voltage DDR266/DDR333 (nominal VCC of 2.5V)  
I/O Reference voltage  
VCCQ  
2.3  
2.7  
V
V
VREF  
VTT  
VIH(DC)  
VIL(DC)  
VIN(DC)  
VID(DC)  
VIX(DC)  
0.49*VCCQ  
VREF-0.04  
VREF+0.15  
-0.3  
0.51*VCCQ  
VREF+0.04  
VCCQ+0.30  
VREF-0.15  
VCCQ+0.30  
VCCQ+0.60  
VCCQ+0.60  
32  
1
2
I/O Termination voltage  
V
Input logic high voltage  
V
Input logic low voltage  
V
Input voltage level, CK and CK#  
Input differential voltage, CK and CK#  
Input crossing point voltage, CK and CK#  
-0.3  
V
0.3  
V
3
0.3  
V
Addr, CAS#,  
RAS#, WE#  
CS#, CKE  
CK, CK#  
DM  
-32  
uA  
-16  
-16  
-4  
16  
16  
4
10  
uA  
uA  
uA  
uA  
mA  
mA  
mA  
mA  
Input leakage current  
II  
Output leakage current  
IOZ  
IOH  
IOL  
IOH  
IOL  
-10  
-16.8  
16.8  
-9  
Output high current (normal strengh); VOUT = V +0.84V  
Output high current (normal strengh); VOUT = VTT -0.84V  
Output high current (half strengh); VOUT = VTT +0.45V  
Output high current (half strengh); VOUT = VTT -0.45V  
9
NOTES:  
1.  
V
REF is expected to be equal to 0.5*VCCQ of the transmitting device, and to track variations in the DC level of the same. Peak to peak noise on VREF may not exceed 2ꢀ of the DC  
value  
2.  
V
TT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF  
3. VID is the magnitude of the difference between the input level on CK and the input level on CK#.  
CAPACITANCE  
VCC = 2.5V, VCCQ = 2.5V, TA = 25°C, f = 1MHz  
Parameter  
Symbol  
CIN1  
Min  
28  
16  
16  
16  
11  
Max  
44  
Unit  
pF  
pF  
pF  
pF  
pF  
pF  
Input Capacitance (A0-A12, BA0-BA1, RAS#, CAS#, WE#)  
Input Capacitance (CKE0, CKE1)  
CIN2  
24  
Input Capacitance (CS0#, CS1#)  
CIN3  
24  
Input Capacitance (CK0,CK0#, CK1, CK1#)  
Input Capacitance (DM0-DM7)  
CIN4  
24  
CIN5  
13  
Data and DQS input/output capacitance (DQ0-DQ63)  
COUT  
11  
13  
August 2005  
Rev. 0  
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
WV3EG264M64EFSU-D4  
White Electronic Designs  
PRELIMINARY  
AC OPERATING TEST CONDITIONS  
Parameter/Condition  
Symbol  
VIH(AC)  
VIL(AC)  
VID(AC)  
VIX(AC)  
Min  
VREF +0.31  
Max  
Unit  
V
V
V
V
Note  
1
1
Input High (Logic 1) Voltage  
Input Low (Logic 0) Voltage  
Input Differential Voltage, CK and CK# inputs  
Input Crossing Point Voltage, CK and CK# inputs  
NOTES:  
VREF -0.31  
VCCQ+0.6  
0.5*VCCQ+0.2  
0.7  
0.5*VCCQ-0.2  
1.  
V
IH overshoot: VIH = VCCQ +1.5V for a pulse width < 3ns and the pulse can not be greater than 1/3 of the cycle rate.  
IL undershoot: VIL = -1.5V for a pulse width < 3ns and the pulse can not be greater than 1/3 of the cycle rate.  
V
August 2005  
Rev. 0  
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
WV3EG264M64EFSU-D4  
White Electronic Designs  
PRELIMINARY  
IDD SPECIFICATIONS AND TEST CONDITIONS  
0°C ≤ TA ≤ 70°C, VCCQ = 2.5V 0.2V, VCC = 2.5V 0.2V  
Conditions  
Parameter  
Symbol  
DDR333 @  
CL = 2.5 Max  
Unit  
One device bank active; Active-Precharge; tRC = tRC(MIN); tCK = tCK(MIN)  
;
Operating current  
Operating current  
IDD0*  
DQ, DM and DQS inputs change once per clock cycle; Address and control  
inputs change once every two clock cycles  
1080  
mA  
One device bank; Active-Read-Precharge; BL = 4; tRC = tRC(MIN); tCK = tCK(MIN)  
IOUT = 0mA; Address and control inputs change once per clock cycle  
;
IDD1*  
1320  
80  
mA  
mA  
Percharge power-  
down standby current  
IDD2P**  
All device banks are idle; Power-down mode; tCK = tCK(MIN); CKE = LOW  
CS# = HIGH; All device banks are idle; tCK = tCK(MIN); CKE = HIGH; Address  
and other control inputs changing once per clock cycle. VIN = VREF for DQ,  
DQS and DM  
Idle standby current  
IDD2F**  
IDD3P**  
IDD3N**  
IDD4R*  
IDD4W*  
720  
560  
mA  
mA  
mA  
mA  
mA  
Active power-down  
standby current  
One device bank active; Power-down mode; tCK = tCK(MIN); CKE = LOW  
CS# = HIGH; CKE = HIGH; One device bank active; tRC = tRAS(MAX)  
;
Active standby  
current  
tCK = tCK(MIN); DQ, DM and DQS inputs change twice per clock cycle; Address  
and other control inputs changing once per clock cycle  
800  
Burst = 2; Reads; Continuous burst; One device bank active; Address and  
other control inputs changing once per clock cycle; tCK = tCK(MIN); IOUT = 0mA  
Operating current  
Operating current  
1360  
1440  
Burst = 2; Writes; Continuous burst; One device bank active; Address and  
other control inputs changing once per clock cycle; tCK = tCK(MIN); DQ, DM and  
DQS inputs change twice per clock cycle  
Auto refresh current  
Self refresh current  
IDD5**  
IDD6**  
tRC = tRFC(MIN)  
CKE < 0.2V  
4640  
80  
mA  
mA  
Four device bank interleaving Reads Burst = 4 with auto precharge;  
tRC = tRFC(MIN); tCK = tCK(MIN); Address and control inputs change only during  
Active READ, or WRITE commands  
Orerating current  
IDD7A*  
3280  
mA  
NOTE:  
I
DD specification is based on Micron components. Other DRAM Manufacturers specification may be different.  
* Value calculated as one module rank in this operation condition and other module rank in IDD2P (CKE low) mode.  
** Value calculated as all module ranks in this operation condition.  
August 2005  
Rev. 0  
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
WV3EG264M64EFSU-D4  
White Electronic Designs  
PRELIMINARY  
AC TIMING PARAMETERS  
335  
Parameter  
Symbol  
Min  
Unit  
Max  
Row cycle time  
Refresh row cycle time  
Row active time  
RAS# to CAS# delay  
Row precharge time  
Row active to Row active delay  
Write recovery time  
Last data into Read command  
Clock cycle time  
Clock high level width  
tRC  
tRFC  
tRAS  
tRCD  
tRP  
tRRD  
tWR  
tWTR  
tCK  
tCH  
tCL  
tDQSCK  
tAC  
tDQSQ  
tRPRE  
tRPST  
tDQSS  
tWPRES  
tWPRE  
tDSS  
tDSH  
tDQSH  
tDQSL  
tIS  
60  
72  
42  
15  
15  
12  
15  
1
6
0.45  
0.55  
-0.6  
-0.7  
0.9  
0.4  
0.75  
0
0.25  
0.2  
0.2  
0.35  
0.35  
0.75  
0.75  
0.7  
0.7  
ns  
ns  
70K  
ns  
ns  
ns  
ns  
ns  
tCK  
ns  
tCK  
tCK  
ns  
ns  
ns  
tCK  
tCK  
tCK  
ns  
tCK  
tCK  
tCK  
tCK  
tCK  
ns  
ns  
ns  
ns  
ns  
ns  
CL = 2.5  
13  
0.55  
0.55  
+0.6  
+0.7  
0.45  
1.1  
Clock low level width  
DQS-out access time from CK/CK#  
Output data access time from CK/CK#  
Data strobe edge to ouput data edge  
Read Preamble  
Read Postamble  
CK to valid DQS-in  
DQS-in setup time  
DQS-in hold time  
DQS falling edge to CK rising-setup time  
DQS falling edge from CK rising-hold time  
DQS-in high level width  
0.6  
1.25  
DQS-in low level width  
Address and Control Input setup time (fast)  
Address and Control Input hold time (fast)  
Address and Control Input setup time (slow)  
Address and Control Input hold time (slow)  
Data-out high impedence time from CK/CK#  
Data-out low impedence time from CK/CK#  
tIH  
tIS  
tIH  
tHZ  
+0.7  
tLZ  
-0.7  
Note:  
AC Timing Parameters are based on Micron components. Other DRAM Manufacturers parameters may be different.  
August 2005  
Rev. 0  
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
WV3EG264M64EFSU-D4  
White Electronic Designs  
PRELIMINARY  
AC TIMING PARAMETERS (Continued)  
335  
Parameter  
Symbol  
Unit  
Min  
10  
Max  
Mode register set cycle time  
DQ & DM setup time to DQS  
DQ & DM hold time to DQS  
Control & Address input pulse width  
DQ & DM input pulse width  
Exit self refresh o non-Read command  
Exit self refresh to read command  
Refresh interval time  
Output DQS valid window  
Clock half period  
Data hold skew factor  
DQS write postamble time  
tMRD  
tDS  
tDH  
ns  
ns  
ns  
ns  
ns  
ns  
tCK  
us  
ns  
ns  
ns  
tCK  
0.4  
0.4  
2.2  
1.75  
75  
tIPW  
tDIPW  
tXSNR  
tXSRD  
tREFI  
tQH  
200  
7.8  
0.55  
0.6  
tHP - tQHS  
tCL(min) or tCH(min)  
tHP  
tQHS  
tWPST  
tRAP  
tDAL  
0.4  
15  
Active to Read with Auto precharge command  
Auto precharge write recovery + Precharge time  
(tWR/tCK) + (tRP/tCK  
)
tCK  
August 2005  
Rev. 0  
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
WV3EG264M64EFSU-D4  
White Electronic Designs  
PRELIMINARY  
ORDERING INFORMATION FOR D4  
Part Number  
Speed  
CAS Latency  
tRCD  
tRP  
Height*  
WV3EG264M64EFSU335D4xG  
166MHz/333Mb/s  
2.5  
3
3
31.75mm (1.25")  
NOTES:  
• Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant)  
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to be  
replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others)  
• Consult factory for availability of industrial temperature (-40°C to 85°C) option  
PACKAGE DIMENSIONS FOR D4  
67.60  
(2.661)  
3.80  
(0.150) MAX.  
Full R 2x  
63.60  
(2.504)  
4.00 0.10  
(0.158 0.039)  
31.75  
(1.25)  
20  
(0.787)  
6.0  
0.236  
1
39  
41  
199  
11.40  
4.00  
(0.158) MIN.  
47.40  
(0.449)  
2- 1.80  
(0.071)  
(1.866)  
2.15  
4.20 (0.165)  
(0.085)  
2.40 (0.094)  
1.0 0.1  
(0.04 0.0039)  
1.8  
(0.071)  
2.45  
0.60  
0.45 0.03  
(0.098)  
(0.024)  
(0.018 0.001)  
1.00 0.1  
(0.04 0.0039)  
0.25  
(0.01)  
2.55 Min  
(0.102 Min)  
4.00 0.10  
(0.158 0.039)  
Tolerances: 0.15 (0.006) unless otherwise specified  
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)  
August 2005  
Rev. 0  
9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
WV3EG264M64EFSU-D4  
White Electronic Designs  
PRELIMINARY  
PART NUMBERING GUIDE  
WV 3 E G 264M 64 E F S U xxx D4 x G  
WEDC  
MEMORY  
DDR  
GOLD  
DEPTH (Dual Rank)  
BUS WIDTH  
x8  
FBGA  
2.5V  
UNBUFFERED  
SPEED (MHz)  
PACKAGE 200 PIN  
COMPONENT VENDOR  
NAME  
(M = Micron)  
(S = Samsung)  
G = RoHS COMPLIANT  
August 2005  
Rev. 0  
10  
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
WV3EG264M64EFSU-D4  
White Electronic Designs  
PRELIMINARY  
Document Title  
1GB – 2x64Mx64 DDR SDRAM UNBUFFERED  
Revision History  
Rev #  
History  
Release Date Status  
Rev 0  
Initial Release  
8-05  
Preliminary  
August 2005  
Rev. 0  
11  
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
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