WV3HG2128M72AER-D6
White Electronic Designs
ADVANCED*
DDR2 IDD SPECIFICATIONS AND CONDITIONS
Includes DDR2 SDRAM components only
Symbol Proposed Conditions
IDD0*
534
403
Units
Operating one bank active-precharge current;
2284
2284
mA
tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
IDD1*
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD);
CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus input
are switching; Data pattern is same as IDD6W
2554
2554
mA
IDD2P**
IDD2Q**
IDD2N**
IDD3P**
Precharge power-down current;
988
1780
1960
988
1780
1960
mA
mA
mA
All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus
inputs are FLOATING
Precharge quiet standby current;
All banks idle; tCK = tCK(IDD); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
Precharge standby current;
All banks idle; tCK = tCK(IDD); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
Fast PDN Exit MRS(12) = 0mA
Active power-down current;
All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address
bus inputs are STABLE; Data bus inputs are FLOATING
1780
1132
1780
1132
mA
mA
Slow PDN Exit MRS(12) = 1mA
IDD3N**
Active standby current;
2500
2824
2500
2644
mA
mA
All banks open; tCK = tCK(IDD), tRC = tRC(IDD); tRAS = tRASmax(IDD); CKE is HIGH, CS# is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
IDD4W*
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP
= tRP(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data
bus inputs are SWITCHING
IDD4R*
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS
=
2914
2734
mA
tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data pattern is same as IDD4W
IDD5**
IDD6**
IDD7*
Burst auto refresh current;
5740
288
5740
288
mA
mA
tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS# is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Self refresh current;
CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING
Normal
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC
=
4804
4804
mA
tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address
bus inputs are STABLE during DESELECTs; Data bus imputs are switching.
Notes:
I
DD specification is based on SAMSUNG components. Other DRAM manufacturers specification may be different.
* Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P ( CKE LOW) mode.
** Value calculated reflects all module ranks in this operating condition.
September
2005 Rev. 0
6
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