WV3HG2128M72EEU-D6
White Electronic Designs
ADVANCED
DDR2 ICC SPECIFICATIONS AND CONDITIONS
DDR2 SDRAM components only
Symbol Proposed Conditions
ICC0* Operating one bank active-precharge current;
806
665
553
403
Units
tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
TBD
918
873
828
mA
ICC1*
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD
= tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data pattern is same as ICC4W
TBD
1,008
963
918
mA
ICC2P* Precharge power-down current;
All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
TBD
TBD
TBD
216
720
810
216
630
720
216
630
720
mA
mA
mA
ICC2Q** Precharge quiet standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs
are STABLE; Data bus inputs are FLOATING
ICC2N** Precharge standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs
are SWITCHING; Data bus inputs are SWITCHING
ICC3P** Active power-down current;
All banks open; tCK = tCK(ICC); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0
Slow PDN Exit MRS(12) = 1
TBD
TBD
540
216
450
216
450
216
mA
mA
ICC3N** Active standby current;
All banks open; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH
between valid commands; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
TBD
TBD
TBD
900
810
810
mA
mA
mA
ICC4W* Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS
=
1,503
1,503
1,278
1,278
1,143
1,143
tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data bus inputs are SWITCHING
ICC4R* Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC),
tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address
bus inputs are SWITCHING; Data pattern is same as ICC4W
ICC5B** Burst auto refresh current;
t
CK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between
TBD
TBD
3,960
180
3,870
180
3,780
180
mA
mA
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
ICC6**
Self refresh current;
CK and CK\ at 0V; CKE 0.2V; Other control and address bus
inputs are FLOATING; Data bus inputs are FLOATING
Normal
ICC7*
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK
=
tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between
valid commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are
SWITCHING.
TBD
2,808
2,628
2,448
mA
Note: ICC specification is based on SAMSUNG components. Other DRAM Manufacturers specification may be different.
*: Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P (CKE LOW) mode.
**: Value calculated reflects all module ranks in this operating condition.
August 2006
Rev. 1
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
