KXTF9,PDF,KXTF9 PDF资料,Datasheet,下载KXTF9技术资料

PART NUMBER:

2g Tri-axis Digital Accelerometer

Specifications

KXTF9-4100

Rev. 1

Dec-2009

Product Description

The KXTF9 is a tri-axis +/-2g, +/-4g or +/-8g silicon

micromachined accelerometer with integrated orientation,

tap/double tap, and activity detecting algorithms. The sense

element is fabricated using Kionix’s proprietary plasma

micromachining process technology. Acceleration sensing is

based on the principle of a differential capacitance arising from

acceleration-induced motion of the sense element, which

further utilizes common mode cancellation to decrease errors

from process variation, temperature, and environmental stress.

The sense element is hermetically sealed at the wafer level by

bonding a second silicon lid wafer to the device using a glass

frit. A separate ASIC device packaged with the sense element

provides

signal

conditioning,

and

intelligent

user-

programmable application algorithms. The accelerometer is

delivered in a 3 x 3 x 0.9 mm LGA plastic package operating

from a 1.8 – 3.6V DC supply. I²C interface is used to

communicate to the chip to configure and check updates to the orientation, Directional Tap^TM

detection and activity monitoring algorithms.

Functional Diagram

X

Sensor

Y

Sensor

Charge

Amp

A/D

Z

Sensor

5

Vdd

I ²C

Digital Engine

Digital

Filter

1

4

IO Vdd

GND

9

10

7

36 Thornwood Dr. – Ithaca, NY 14850

tel: 607-257-1080 – fax:607-257-1146

www.kionix.com - info@kionix.com

091222-00

Page 1 of 41

PART NUMBER:

2g Tri-axis Digital Accelerometer

Specifications

KXTF9-4100

Rev. 1

Dec-2009

Product Specifications

Table 1. Mechanical

(specifications are for operation at 1.8V and T = 25C unless stated otherwise)

Parameters

Operating Temperature Range

Zero-g Offset

Units

ºC

Min

-40

Typical

Max

85

-

mg

-125

+125

0.7 (xy)

0.4 (z)

1024

Zero-g Offset Variation from RT over Temp.

mg/ºC

GSEL1=0, GSEL=0 ( 2g)

988

494

1060

530

Sensitivity (12-bit)¹

counts/g

GSEL1=0, GSEL0=1 ( 4g)

512

GSEL1=1, GSEL0=0 ( 8g)

GSEL1=0, GSEL=0 ( 2g)

247

61

256

64

265

67

Sensitivity (8-bit)¹

counts/g

GSEL1=0, GSEL0=1 ( 4g)

30

32

34

GSEL1=1, GSEL0=0 ( 8g)

15

16

17

0.01 (xy)

0.03 (z)

0.3

Sensitivity Variation from RT over Temp.

%/ºC

%

Offset Ratiometric Error (V_dd= 1.8V 5%)

Sensitivity Ratiometric Error (V_dd= 1.8V 5%)

0.4 (xy)

0.2 (z)

0.9 (x)

0.8 (y)

0.7 (z)

3500 (xy)

1800 (z)

1

%

Self Test Output change on Activation

Mechanical Resonance (-3dB)²

g

Hz

Non-Linearity

% of FS

%

Cross Axis Sensitivity

2

Notes:

1. Resolution and acceleration ranges are user selectable via I²C.

2. Resonance as defined by the dampened mechanical sensor.

36 Thornwood Dr. – Ithaca, NY 14850

tel: 607-257-1080 – fax:607-257-1146

www.kionix.com - info@kionix.com

091222-00

Page 2 of 41

PART NUMBER:

2g Tri-axis Digital Accelerometer

Specifications

KXTF9-4100

Rev. 1

Dec-2009

Table 2. Electrical

(specifications are for operation at 1.8V and T = 25C unless stated otherwise)

Parameters

Supply Voltage (V_dd) Operating

I/O Pads Supply Voltage (V_IO)

Units

Min

Typical

Max

V

1.8

1.7

1.8

3.6

V_dd

All On (Res = 1)

470

-

570

230

670

Current Consumption

µ

A

All On (RES = 0)

Standby

-

0.1

-

Output Low Voltage¹

Output High Voltage

Input Low Voltage

V

-

0.3 * V_io

V

0.9 * V_io

-

0.2 * V_io

-

Input High Voltage

Input Pull-down Current

0.8 * V_io

-

0

µ

A

RES = 0

0.050

160

80

40

20

10

5

RES = 1, ODR = 12.5Hz

RES = 1, ODR = 25 Hz

RES = 1, ODR = 50Hz

RES = 1, ODR = 100Hz

RES = 1, ODR = 200Hz

RES = 1, ODR = 400Hz

RES = 1, ODR = 800Hz

Start Up Time²

ms

2.5

20

Power Up Time³

ms

KHz

Hz

I²C Communication Rate

Output Data Rate (ODR)⁴

400

800

12.5

50

RES = 0

RES = 1

KHz

Hz

1.59

Bandwidth (-3dB)⁵

Notes:

ODR/2

1. Assuming I²C communication and minimum 1.5Kohm pull-up resistor on SCL and

SDA pins.

2. Start up time is from PC1 set to valid outputs.

3. Power up time is from Vdd valid to device boot completion.

4. User selectable through I²C.

5. User selectable and dependant on ODR and RES.

36 Thornwood Dr. – Ithaca, NY 14850

tel: 607-257-1080 – fax:607-257-1146

www.kionix.com - info@kionix.com

091222-00

Page 3 of 41

PART NUMBER:

2g Tri-axis Digital Accelerometer

Specifications

KXTF9-4100

Rev. 1

Dec-2009

Table 3. Environmental

Parameters

Supply Voltage (V_dd) Absolute Limits

Operating Temperature Range

Storage Temperature Range

Units

V

Min

-0.3

-40

Typical

Max

6.0

-

ºC

85

ºC

-55

150

5000 for 0.5ms

10000 for 0.2ms

Mech. Shock (powered and unpowered)

g

-

ESD

HBM

V

2000

Caution: ESD Sensitive and Mechanical Shock Sensitive Component, improper handling

can cause permanent damage to the device.

This product conforms to Directive 2002/95/EC of the European Parliament and of the

Council of the European Union (RoHS). Specifically, this product does not contain lead,

mercury, cadmium, hexavalent chromium, polybrominated biphenyls (PBB), or

polybrominated diphenyl ethers (PBDE) above the maximum concentration values

(MCV) by weight in any of its homogenous materials. Homogenous materials are "of

uniform composition throughout."

This product is halogen-free per IEC 61249-2-21. Specifically, the materials used in this

HF product contain a maximum total halogen content of 1500 ppm with less than 900-ppm

bromine and less than 900-ppm chlorine.

Soldering

Soldering recommendations are available upon request or from www.kionix.com.

36 Thornwood Dr. – Ithaca, NY 14850

tel: 607-257-1080 – fax:607-257-1146

www.kionix.com - info@kionix.com

091222-00

Page 4 of 41

PART NUMBER:

2g Tri-axis Digital Accelerometer

Specifications

KXTF9-4100

Rev. 1

Dec-2009

Application Schematic

Table 4. KXTF9 Pin Descriptions

1

Name

IO Vdd

DNC

GND

Vdd

Description

The power supply input for the digital communication bus. Decouple this pin to ground with a 0.1uF ceramic capacitor.

2

Reserved – Do Not Connect

3

Reserved – Do Not Connect

4

Ground

5

The power supply input. Decouple this pin to ground with a 1uF ceramic capacitor.

6

DNC

INT

Reserved – Do Not Connect

Physical Interrupt

7

8

DNC

SCL

Reserved – Do Not Connect

I²C Serial Clock

9

10

SDA

I²C Serial Data

36 Thornwood Dr. – Ithaca, NY 14850

tel: 607-257-1080 – fax:607-257-1146

www.kionix.com - info@kionix.com

091222-00

Page 5 of 41

PART NUMBER:

2g Tri-axis Digital Accelerometer

Specifications

KXTF9-4100

Rev. 1

Dec-2009

Test Specifications

!

Special Characteristics:

These characteristics have been identified as being critical to the customer. Every part is tested to

verify its conformance to specification prior to shipment.

Table 5. Test Specifications

Parameter

Zero-g Offset @ RT

Sensitivity @ RT

Specification

0 +/- 128 counts

1024 +/- 36 counts/g

Test Conditions

25C, Vdd = 1.8 V

Current Consumption -- Operating 470 <= Idd <= 670 uA 25C, Vdd = 1.8 V

36 Thornwood Dr. – Ithaca, NY 14850

tel: 607-257-1080 – fax:607-257-1146

www.kionix.com - info@kionix.com

091222-00

Page 6 of 41

PART NUMBER:

2g Tri-axis Digital Accelerometer

Specifications

KXTF9-4100

Rev. 1

Dec-2009

Package Dimensions and Orientation

3 x 3 x 0.9 mm LGA

All dimensions and tolerances conform to ASME Y14.5M-1994

36 Thornwood Dr. – Ithaca, NY 14850

tel: 607-257-1080 – fax:607-257-1146

www.kionix.com - info@kionix.com

091222-00

Page 7 of 41

PART NUMBER:

2g Tri-axis Digital Accelerometer

Specifications

KXTF9-4100

Rev. 1

Dec-2009

Orientation

+Y

Pin 1

+X

+Z

When device is accelerated in +X, +Y or +Z direction, the corresponding output will increase.

Static X/Y/Z Output Response versus Orientation to Earth’s surface (1g):

GSEL1=0, GSEL0=0 ( 2g)

Position

1

2

3

4

5

6

Top

Bottom

Diagram

Bottom

Top

Resolution (bits)

X (counts)

12

0

8

0

12 8

1024 64

12

0

8

0

12 8

3072 192

12

8

0

12

8

0

1024 64

0

3072 192

0

Y (counts)

0

Z (counts)

0

1024 64 3072 192

0

+

0

+

0

-

0

+

0

-

X-Polarity

Y-Polarity

Z-Polarity

0

(1g)

Earth’s Surface

36 Thornwood Dr. – Ithaca, NY 14850

tel: 607-257-1080 – fax:607-257-1146

www.kionix.com - info@kionix.com

091222-00

Page 8 of 41

PART NUMBER:

2g Tri-axis Digital Accelerometer

Specifications

KXTF9-4100

Rev. 1

Dec-2009

Static X/Y/Z Output Response versus Orientation to Earth’s surface (1g):

GSEL1=0, GSEL0=1 ( 4g)

Position

1

2

3

4

5

6

Top

Bottom

Diagram

Bottom

Top

Resolution (bits)

X (counts)

12

0

8

0

12

8

12

0

8

0

12

8

12

8

0

12

8

512 32

3584 224

0

512 32

0

3584 224

0

Y (counts)

0

Z (counts)

0

512 32 3584 224

0

+

0

+

0

-

0

+

0

-

X-Polarity

Y-Polarity

Z-Polarity

0

(1g)

Earth’s Surface

Static X/Y/Z Output Response versus Orientation to Earth’s surface (1g):

GSEL1=1, GSEL0=0 ( 8g)

Position

1

2

3

4

5

6

Top

Bottom

Diagram

Bottom

Top

Resolution (bits)

X (counts)

12

0

8

0

12 8

256 16

12

0

8

0

12 8

3840 240

12

8

0

12

8

0

256 16

0

3840 240

0

Y (counts)

0

Z (counts)

0

256 16 3840 240

0

+

0

+

0

-

0

+

0

-

X-Polarity

Y-Polarity

Z-Polarity

0

(1g)

Earth’s Surface

36 Thornwood Dr. – Ithaca, NY 14850

tel: 607-257-1080 – fax:607-257-1146

www.kionix.com - info@kionix.com

091222-00

Page 9 of 41

PART NUMBER:

2g Tri-axis Digital Accelerometer

Specifications

KXTF9-4100

Rev. 1

Dec-2009

KXTF9 Digital Interface

The Kionix KXTF9 digital accelerometer has the ability to communicate on the I²C digital serial interface

bus. This flexibility allows for easy system integration by eliminating analog-to-digital converter

requirements and by providing direct communication with system micro-controllers.

The serial interface terms and descriptions as indicated in Table 6 below will be observed throughout this

document.

Term

Transmitter

Receiver

Master

Description

The device that transmits data to the bus.

The device that receives data from the bus.

The device that initiates a transfer, generates clock signals, and terminates a transfer.

The device addressed by the Master.

Slave

Table 6. Serial Interface Terminologies

I²C Serial Interface

As previously mentioned, the KXTF9 has the ability to communicate on an I²C bus. I²C is primarily used for

synchronous serial communication between a Master device and one or more Slave devices. The Master,

typically a micro controller, provides the serial clock signal and addresses Slave devices on the bus. The

KXTF9 always operates as a Slave device during standard Master-Slave I²C operation.

I²C is a two-wire serial interface that contains a Serial Clock (SCL) line and a Serial Data (SDA) line. SCL

is a serial clock that is provided by the Master, but can be held low by any Slave device, putting the Master

into a wait condition. SDA is a bi-directional line used to transmit and receive data to and from the

interface. Data is transmitted MSB (Most Significant Bit) first in 8-bit per byte format, and the number of

bytes transmitted per transfer is unlimited. The I²C bus is considered free when both lines are high.

I²C Operation

Transactions on the I²C bus begin after the Master transmits a start condition (S), which is defined as a

high-to-low transition on the data line while the SCL line is held high. The bus is considered busy after this

condition. The next byte of data transmitted after the start condition contains the Slave Address (SAD) in

the seven MSBs (Most Significant Bits), and the LSB (Least Significant Bit) tells whether the Master will be

receiving data ‘1’ from the Slave or transmitting data ‘0’ to the Slave. When a Slave Address is sent, each

device on the bus compares the seven MSBs with its internally stored address. If they match, the device

considers itself addressed by the Master. The Slave Address associated with the KXTF9 is 0001111.

It is mandatory that receiving devices acknowledge (ACK) each transaction. Therefore, the transmitter

must release the SDA line during this ACK pulse. The receiver then pulls the data line low so that it

remains stable low during the high period of the ACK clock pulse. A receiver that has been addressed,

whether it is Master or Slave, is obliged to generate an ACK after each byte of data has been received. To

36 Thornwood Dr. – Ithaca, NY 14850

tel: 607-257-1080 – fax:607-257-1146

091222-00

www.kionix.com - info@kionix.com

Page 10 of 41

PART NUMBER:

2g Tri-axis Digital Accelerometer

Specifications

KXTF9-4100

Rev. 1

Dec-2009

conclude a transaction, the Master must transmit a stop condition (P) by transitioning the SDA line from low

to high while SCL is high. The I²C bus is now free.

Writing to a KXTF9 8-bit Register

Upon power up, the Master must write to the KXTF9’s control registers to set its operational mode.

Therefore, when writing to a control register on the I²C bus, as shown Sequence 1 on the following page,

the following protocol must be observed: After a start condition, SAD+W transmission, and the KXTF9

ACK has been returned, an 8-bit Register Address (RA) command is transmitted by the Master. This

command is telling the KXTF9 to which 8-bit register the Master will be writing the data. Since this is I²C

mode, the MSB of the RA command should always be zero (0). The KXTF9 acknowledges the RA and the

Master transmits the data to be stored in the 8-bit register. The KXTF9 acknowledges that it has received

the data and the Master transmits a stop condition (P) to end the data transfer. The data sent to the

KXTF9 is now stored in the appropriate register. The KXTF9 automatically increments the received RA

commands and, therefore, multiple bytes of data can be written to sequential registers after each Slave

ACK as shown in Sequence 2 on the following page.

Reading from a KXTF9 8-bit Register

When reading data from a KXTF9 8-bit register on the I²C bus, as shown in Sequence 3 on the next page,

the following protocol must be observed: The Master first transmits a start condition (S) and the

appropriate Slave Address (SAD) with the LSB set at ‘0’ to write. The KXTF9 acknowledges and the

Master transmits the 8-bit RA of the register it wants to read. The KXTF9 again acknowledges, and the

Master transmits a repeated start condition (Sr). After the repeated start condition, the Master addresses

the KXTF9 with a ‘1’ in the LSB (SAD+R) to read from the previously selected register. The Slave then

acknowledges and transmits the data from the requested register. The Master does not acknowledge

(NACK) it received the transmitted data, but transmits a stop condition to end the data transfer. Note that

the KXTF9 automatically increments through its sequential registers, allowing data to be read from multiple

registers following a single SAD+R command as shown below in Sequence 4 on the following page.

If a receiver cannot transmit or receive another complete byte of data until it has performed some other

function, it can hold SCL low to force the transmitter into a wait state. Data transfer only continues when

the receiver is ready for another byte and releases SCL.

36 Thornwood Dr. – Ithaca, NY 14850

tel: 607-257-1080 – fax:607-257-1146

091222-00

www.kionix.com - info@kionix.com

Page 11 of 41

PART NUMBER:

2g Tri-axis Digital Accelerometer

Specifications

KXTF9-4100

Rev. 1

Dec-2009

Data Transfer Sequences

The following information clearly illustrates the variety of data transfers that can occur on the I²C bus and

how the Master and Slave interact during these transfers. Table 7 defines the I²C terms used during the

data transfers.

Term

S

Definition

Start Condition

Sr

Repeated Start Condition

Slave Address

SAD

W

Write Bit

R

Read Bit

ACK

NACK

RA

Acknowledge

Not Acknowledge

Register Address

Transmitted/Received Data

Stop Condition

Data

P

Table 7. I²C Terms

Sequence 1. The Master is writing one byte to the Slave.

Master

Slave

S

SAD + W

RA

DATA

P

ACK

Sequence 2. The Master is writing multiple bytes to the Slave.

Master

Slave

S

SAD + W

RA

DATA

P

ACK

Sequence 3. The Master is receiving one byte of data from the Slave.

Master

Slave

S

SAD + W

RA

Sr SAD + R

NACK

P

ACK

ACK DATA

Sequence 4. The Master is receiving multiple bytes of data from the Slave.

Master

Slave

S

SAD + W

RA

Sr SAD + R

ACK

NACK

P

ACK

ACK DATA

DATA

36 Thornwood Dr. – Ithaca, NY 14850

tel: 607-257-1080 – fax:607-257-1146

www.kionix.com - info@kionix.com

091222-00

Page 12 of 41

PART NUMBER:

2g Tri-axis Digital Accelerometer

Specifications

KXTF9-4100

Rev. 1

Dec-2009

KXTF9 Embedded Registers

The KXTF9 has 39 embedded 8-bit registers that are accessible by the user. This section contains the

addresses for all embedded registers and also describes bit functions of each register. Table 8 below

provides a listing of the accessible 8-bit registers and their addresses.

Type

I2C Read/Write Address

Register Name

XOUT_HPF_L

XOUT_HPF_H

YOUT_HPF_L

YOUT_HPF_H

ZOUT_HPF_L

ZOUT_HPF_H

XOUT_L

Read/Write

Hex

Binary

R

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

0000 0000

0000 0001

0000 0010

0000 0011

0001 0100

0001 0101

0000 0110

0000 0111

0000 1000

0000 1001

0001 1010

0001 1011

0000 1100

0000 1101

0000 1110

0000 1111

0001 0000

0001 0001

0001 0010

0001 0011

0001 0100

0001 0101

0001 0110

0001 0111

0001 1000

0001 1001

0001 1010

0001 1011

0001 1100

0001 1101

0001 1110

0001 1111

R

XOUT_H

R

YOUT_L

R

YOUT_H

R

ZOUT_L

R

ZOUT_H

R

DCST_RESP

Not Used

R

-

Not Used

-

WHO_AM_I

R

TILT_POS_CUR

TILT_POS_PRE

Kionix Reserved

INT_SRC_REG1

INT_SRC_REG2

Not Used

R

-

R

-

STATUS_REG

Not Used

R

-

INT_REL

R

CTRL_REG1*

CTRL_REG2*

CTRL_REG3*

INT_CTRL_REG1*

INT_CTRL_REG2*

R/W

36 Thornwood Dr. – Ithaca, NY 14850

tel: 607-257-1080 – fax:607-257-1146

www.kionix.com - info@kionix.com

091222-00

Page 13 of 41

PART NUMBER:

2g Tri-axis Digital Accelerometer

Specifications

KXTF9-4100

Rev. 1

Dec-2009

INT_CTRL_REG3*

DATA_CTRL_REG*

Not Used

R/W

-

0x20

0x21

0010 0000

0010 0001

-

0x22 – 0x27

0x28

TILT_TIMER*

R/W

-

0010 1000

0010 1001

0010 1010

0010 1011

0010 1100

0010 1101

0010 1110

0010 1111

0011 0000

0011 0001

-

WUF_TIMER*

Not Used

0x29

0x2A

TDT_TIMER*

R/W

-

0x2B

TDT_H_THRESH*

TDT_L_THRESH*

TDT_TAP_TIMER*

TDT_TOTAL_TIMER*

TDT_LATENCY_TIMER*

TDT_WINDOW_TIMER*

Reserved

0x2C

0x2D

0x2E

0x2F

0x30

0x31

0x32 – 0x39

0x3A

SELF_TEST

R/W

-

0011 1010

-

Reserved

0x3B – 0x59

0x5A

WUF_THRESH*

Reserved

R/W

-

0101 1010

0101 1011

0101 1100

-

0x5B

TILT_ANGLE*

Reserved

R/W

-

0x5C

0x5D – 0x5E

0x5F

HYST_SET*

R/W

0101 1111

* Note: When changing the contents of these registers, the PC1 bit in CTRL_REG1 must

first be set to “0”.

Table 8. KXTF9 Register Map

36 Thornwood Dr. – Ithaca, NY 14850

tel: 607-257-1080 – fax:607-257-1146

www.kionix.com - info@kionix.com

091222-00

Page 14 of 41

PART NUMBER:

2g Tri-axis Digital Accelerometer

Specifications

KXTF9-4100

Rev. 1

Dec-2009

KXTF9 Register Descriptions

Accelerometer Outputs

These registers contain up to 12-bits of valid acceleration data for each axis depending on the

setting of the RES bit in CTRL_REG1, where the acceleration outputs are represented in 12-bit

valid data when RES = ‘1’ and 8-bit valid data when RES = ‘0’. The data is updated every user-

defined ODR period, is protected from overwrite during each read, and can be converted from

digital counts to acceleration (g) per Figure 9 below.

12-bit Data

0111 1111 1111

0111 1111 1110

…

Range = +/-2g Range = +/-4g Range = +/-8g

+1.999g

+1.998g

…

+3.998g

+3.996g

…

+7.996g

+7.992g

…

0000 0000 0001

0000 0000 0000

1111 1111 1111

…

+0.001g

0.000g

-0.001g

…

+0.002g

0.000g

-0.002g

…

+0.004g

0.000g

-0.004g

…

1000 0000 0001

1000 0000 0000

-1.999g

-2.000g

-3.998g

-4.000g

-7.996g

-8.000g

8-bit Data

0111 1111

0111 1110

Range = +/-2g Range = +/-4g Range = +/-8g

+1.984g

+1.968g

…

+3.968g

+3.936g

…

+7.936g

+7.872g

…

0000 0001

+0.016g

0.000g

-0.016g

…

+0.032g

0.000g

-0.032g

…

+0.064g

0.000g

-0.064g

…

0000 0000

1111 1111

…

1000 0001

-1.984g

-2.000g

-3.968g

-4.000g

-7.936g

-8.000g

1000 0000

Figure 9. Acceleration (g) Calculation

36 Thornwood Dr. – Ithaca, NY 14850

tel: 607-257-1080 – fax:607-257-1146

www.kionix.com - info@kionix.com

091222-00

Page 15 of 41

PART NUMBER:

2g Tri-axis Digital Accelerometer

Specifications

KXTF9-4100

Rev. 1

Dec-2009

XOUT_HPF_L

X-axis high-pass filtered accelerometer output least significant byte

R

X

R

X

R

X

R

X

XOUTD3 XOUTD2 XOUTD1 XOUTD0

Bit7 Bit6 Bit5 Bit4

Bit3

Bit2

Bit1

Bit0

I²C Address: 0x00h

XOUT_HPF_H

X-axis high-pass filtered accelerometer output most significant byte

R

XOUTD11 XOUTD10 XOUTD9 XOUTD8 XOUTD7 XOUTD6 XOUTD5 XOUTD4

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

I²C Address: 0x01h

YOUT_HPF_L

Y-axis high-pass filtered accelerometer output least significant byte

R

X

R

X

R

X

R

X

YOUTD3 YOUTD2 YOUTD1 YOUTD0

Bit7 Bit6 Bit5 Bit4

Bit3

Bit2

Bit1

Bit0

I²C Address: 0x02h

YOUT_HPF_H

Y-axis high-pass filtered accelerometer output most significant byte

R

YOUTD11 YOUTD10 YOUTD9 YOUTD8 YOUTD7 YOUTD6 YOUTD5 YOUTD4

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

I²C Address: 0x03h

ZOUT_HPF_L

Z-axis high-pass filtered accelerometer output least significant byte

R

X

R

X

R

X

R

X

ZOUTD3 ZOUTD2 ZOUTD1 ZOUTD0

Bit7 Bit6 Bit5 Bit4

Bit3

Bit2

Bit1

Bit0

I2C Address: 0x04h

36 Thornwood Dr. – Ithaca, NY 14850

tel: 607-257-1080 – fax:607-257-1146

www.kionix.com - info@kionix.com

091222-00

Page 16 of 41

PART NUMBER:

2g Tri-axis Digital Accelerometer

Specifications

KXTF9-4100

Rev. 1

Dec-2009

ZOUT_HPF_H

Z-axis high-pass filtered accelerometer output most significant byte

R

ZOUTD11 ZOUTD10 ZOUTD9 ZOUTD8 ZOUTD7 ZOUTD6 ZOUTD5 ZOUTD4

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

I²C Address: 0x05h

XOUT_L

X-axis accelerometer output least significant byte

R

X

R

X

R

X

R

X

XOUTD3 XOUTD2 XOUTD1 XOUTD0

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

I²C Address: 0x06h

XOUT_H

X-axis accelerometer output most significant byte

R

XOUTD11 XOUTD10 XOUTD9 XOUTD8 XOUTD7 XOUTD6 XOUTD5 XOUTD4

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

I²C Address: 0x07h

YOUT_L

Y-axis accelerometer output least significant byte

R

X

R

X

R

X

R

X

YOUTD3 YOUTD2 YOUTD1 YOUTD0

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

I²C Address: 0x08h

YOUT_H

Y-axis accelerometer output most significant byte

R

YOUTD11 YOUTD10 YOUTD9 YOUTD8 YOUTD7 YOUTD6 YOUTD5 YOUTD4

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

I²C Address: 0x09h

36 Thornwood Dr. – Ithaca, NY 14850

tel: 607-257-1080 – fax:607-257-1146

www.kionix.com - info@kionix.com

091222-00

Page 17 of 41

PART NUMBER:

2g Tri-axis Digital Accelerometer

Specifications

KXTF9-4100

Rev. 1

Dec-2009

ZOUT_L

Z-axis accelerometer output least significant byte

R

X

R

X

R

X

R

X

ZOUTD3 ZOUTD2 ZOUTD1 ZOUTD0

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

I2C Address: 0x0Ah

ZOUT_H

Z-axis accelerometer output most significant byte

R

ZOUTD11 ZOUTD10 ZOUTD9 ZOUTD8 ZOUTD7 ZOUTD6 ZOUTD5 ZOUTD4

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

I²C Address: 0x0Bh

DCST_RESP

This register can be used to verify proper integrated circuit functionality. It always has a byte value

of 0x55h unless the DCST bit in CTRL_REG3 is set. At that point this value is set to 0xAAh. The

byte value is returned to 0x55h after reading this register.

R

DCSTR7 DCSTR6 DCSTR5 DCSTR4 DCSTR3 DCSTR2 DCSTR1 DCSTR0

Reset Value

01010101

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

I²C Address: 0x0Ch

WHO_AM_I

This register can be used for supplier recognition, as it can be factory written to a known byte value.

The default value is 0x01h.

R

WIA7

Bit7

WIA6

Bit6

WIA5

Bit5

WIA4

Bit4

WIA3

Bit3

WIA2

Bit2

WIA1

Bit1

WIA0

Bit0

Reset Value

00000001

I²C Address: 0x0Fh

36 Thornwood Dr. – Ithaca, NY 14850

tel: 607-257-1080 – fax:607-257-1146

www.kionix.com - info@kionix.com

091222-00

Page 18 of 41

PART NUMBER:

2g Tri-axis Digital Accelerometer

Specifications

KXTF9-4100

Rev. 1

Dec-2009

Tilt Position Registers

These two registers report previous and current position data that is updated at the user-defined

ODR frequency and is protected during register read. Table 9 describes the reported position for

each bit value.

TILT_POS_CUR

Current tilt position register

R

0

R

0

R

RI

R

Reset Value

00100000

LE

DO

Bit3

UP

Bit2

FD

Bit1

FU

Bit0

Bit7

Bit6

Bit5

Bit4

I²C Address: 0x10h

TILT_POS_PRE

Previous tilt position register

R

0

R

0

R

RI

R

Reset Value

00100000

LE

DO

Bit3

UP

Bit2

FD

Bit1

FU

Bit0

Bit7

Bit6

Bit5

Bit4

I²C Address: 0x11h

Bit

LE

RI

Description

Left State (X-)

Right State (X+)

Down State (Y-)

Up State (Y+)

DO

UP

FD

FU

Face-Down State (Z-)

Face-Up State (Z+)

Table 9. KXTF9 Tilt Position

36 Thornwood Dr. – Ithaca, NY 14850

tel: 607-257-1080 – fax:607-257-1146

www.kionix.com - info@kionix.com

091222-00

Page 19 of 41

PART NUMBER:

2g Tri-axis Digital Accelerometer

Specifications

KXTF9-4100

Rev. 1

Dec-2009

Interrupt Source Registers

These two registers report function state changes. This data is updated when a new state change

or event occurs and each applications result is latched until the interrupt release register is read.

The motion interrupt bit WUFS can be configured to report data in an unlatched manner via the

interrupt control registers.

INT_SRC_REG1

This register reports which axis and direction detected a single or double tap event, per

Table 10.

R

0

R

0

R

TLE

Bit5

TRI

Bit4

TDO

Bit3

TUP

Bit2

TFD

Bit1

TFU

Bit0

Bit7

Bit6

I²C Address: 0x15h

Bit

Description

TLE

TRI

X Negative (X-) Reported

X Positive (X+) Reported

Y Negative (Y-) Reported

Y Positive (Y+) Reported

Z Negative (Z-) Reported

Z Positive (Z+) Reported

TDO

TUP

TFD

TFU

Table 10. KXTF9 Directional Tap^TMReporting

INT_SRC_REG2

This register reports which function caused an interrupt. Reading from the interrupt release

register will clear the entire contents of this register.

R

0

R

0

R

0

R

DRDY

Bit4

TDTS1

Bit3

TDTS0

Bit2

WUFS

Bit1

TPS

Bit0

Bit7

Bit6

Bit5

I²C Address: 0x16h

DRDY indicates that new acceleration data is available. This bit is cleared when

acceleration data is read or the interrupt release register is read.

DRDY = 0 – new acceleration data not available

DRDY = 1 – new acceleration data available

TDTS1, TDTS0 indicates whether a single or double-tap event was detected per

Table 11.

36 Thornwood Dr. – Ithaca, NY 14850

tel: 607-257-1080 – fax:607-257-1146

www.kionix.com - info@kionix.com

091222-00

Page 20 of 41

PART NUMBER:

2g Tri-axis Digital Accelerometer

Specifications

KXTF9-4100

Rev. 1

Dec-2009

TDTS1 TDTS0

Event

No Tap

0

1

0

1

0

1

Single Tap

Double Tap

DNE

Table 11. Directional Tap^TMEvent Description

TPS reflects the status of the tilt position function.

TPS = 0 – tilt position state has not changed

TPS = 1 – tilt position state has changed

STATUS_REG

This register reports the status of the interrupt.

R

0

R

0

R

0

R

0

R

0

R

0

R

0

INT

Bit4

Bit7

Bit6

Bit5

Bit3

Bit2

Bit1

Bit0

I²C Address: 0x18h

INT reports the combined interrupt information of all enabled functions. This bit is

released to 0 when the interrupt source latch register (1Ah) is read.

INT = 0 – no interrupt event

INT = 1 – interrupt event has occurred

INT_REL

Latched interrupt source information (INT_SRC_REG1 and INT_SRC_REG2), the status register,

and the physical interrupt pin (7) are cleared when reading this register.

R

X

R

X

R

X

R

X

R

X

R

X

R

X

R

X

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

I²C Address: 0x1Ah

36 Thornwood Dr. – Ithaca, NY 14850

tel: 607-257-1080 – fax:607-257-1146

www.kionix.com - info@kionix.com

091222-00

Page 21 of 41

PART NUMBER:

2g Tri-axis Digital Accelerometer

Specifications

KXTF9-4100

Rev. 1

Dec-2009

CTRL_REG1

Read/write control register that controls the main feature set.

R/W

PC1

Bit7

R/W

RES

Bit6

R/W

DRDYE

Bit5

R/W

GSEL1

Bit4

R/W

GSEL0

Bit3

R/W

TDTE

Bit2

R/W

WUFE

Bit1

R/W

TPE

Bit0

Reset Value

00000000

I²C Address: 0x1Bh

PC1 controls the operating mode of the KXTF9.

PC1 = 0 - stand-by mode

PC1 = 1 – operating mode

RES determines the performance mode of the KXTF9. Note that to change the value of

this bit, the PC1 bit must first be set to “0”.

RES = 0 – low current, 8-bit valid

RES = 1- high current, 12-bit valid

DRDYE enables the reporting of the availability of new acceleration data on the interrupt.

Note that to change the value of this bit, the PC1 bit must first be set to “0”.

DRDYE = 0 – availability of new acceleration data not reflected on interrupt pin (7)

DRDYE = 1- availability of new acceleration data reflected on interrupt pin (7)

GSEL1, GSEL0 selects the acceleration range of the accelerometer outputs per Table 12.

Note that to change the value of this bit, the PC1 bit must first be set to “0”.

GSEL1 GSEL0

Range

+/-2g

+/-4g

+/-8g

NA

0

1

0

1

0

1

Table 12. Selected Acceleration Range

TDTE enables the Directional Tap^TMfunction that will detect single and double tap events.

Note that to change the value of this bit, the PC1 bit must first be set to “0”.

TDTE = 0 – disable

TDTE = 1- enable

36 Thornwood Dr. – Ithaca, NY 14850

tel: 607-257-1080 – fax:607-257-1146

www.kionix.com - info@kionix.com

091222-00

Page 22 of 41

PART NUMBER:

2g Tri-axis Digital Accelerometer

Specifications

KXTF9-4100

Rev. 1

Dec-2009

WUFE enables the Wake Up (motion detect) function that will detect a general motion

event. Note that to change the value of this bit, the PC1 bit must first be set to “0”.

WUFE = 0 – disable

WUFE = 1- enable

TPE enables the Tilt Position function that will detect changes in device orientation. Note

that to change the value of this bit, the PC1 bit must first be set to “0”.

TPE = 0 – disable

TPE = 1- enable

CTRL_REG2

Read/write control register that controls tilt position state enabling. Per Table 13, if a state’s bit is

set to one (1), a transition into the corresponding orientation state will generate an interrupt. If it is

set to zero (0), a transition into the corresponding orientation state will not generate an interrupt.

Note that to properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set

to “0”.

R/W

0

R/W

0

R/W

LEM

Bit5

R/W

RIM

Bit4

R/W

DOM

Bit3

R/W

UPM

Bit2

R/W

FDM

Bit1

R/W

FUM

Bit0

Reset Value

00111111

Bit7

Bit6

I²C Address: 0x1Ch

Bit

Description

Left State

Right State

LEM

RIM

DOM

UPM

FDM

FUM

Down State

Up State

Face-Down State

Face-Up State

Table 13. Tilt Position State Enabling

CTRL_REG3

Read/write control register that provides more feature set control. Note that to properly change the

value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”.

R/W

SRST

Bit7

R/W

OTPA

Bit6

R/W

OTPB

Bit5

R/W

DCST

Bit4

R/W

OTDTA

Bit3

R/W

OTDTB

Bit2

R/W

OWUFA OWUFB

Bit1 Bit0

I²C Address: 0x1Dh

R/W

Reset Value

01001101

36 Thornwood Dr. – Ithaca, NY 14850

tel: 607-257-1080 – fax:607-257-1146

www.kionix.com - info@kionix.com

091222-00

Page 23 of 41

PART NUMBER:

2g Tri-axis Digital Accelerometer

Specifications

KXTF9-4100

Rev. 1

Dec-2009

SRST initiates software reset, which performs the RAM reboot routine. This bit will remain

1 until the RAM reboot routine is finished.

SRST = 0 – no action

SRST = 1 – start RAM reboot routine

OTPA, OTPB sets the output data rate for the Tilt Position function per Table 14. The

default Tilt Position ODR is 12.5Hz.

OTPA OTPB Output Data Rate

0

1

0

1

0

1

1.6Hz

6.3Hz

12.5Hz

50Hz

Table 14. Tilt Position Function Output Data Rate

DCST initiates the digital communication self-test function.

DCST = 0 – no action

DCST = 1 – sets ST_RESP register to 0xAAh and when ST_RESP is read, sets

this bit to 0 and sets ST_RESP to 0x55h

OTDTA, OTDTB sets the output data rate for the Directional Tap^TMfunction per Table 15.

The default Directional Tap^TMODR is 400Hz.

OTDTA OTDTB Output Data Rate

0

1

0

1

0

1

50Hz

100Hz

200Hz

400Hz

Table 15. Directional Tap^TMFunction Output Data Rate

36 Thornwood Dr. – Ithaca, NY 14850

tel: 607-257-1080 – fax:607-257-1146

www.kionix.com - info@kionix.com

091222-00

Page 24 of 41

PART NUMBER:

2g Tri-axis Digital Accelerometer

Specifications

KXTF9-4100

Rev. 1

Dec-2009

OWUFA, OWUFB sets the output data rate for the general motion detection function and

the high-pass filtered outputs per Table 16. The default Motion Wake Up ODR is

50Hz.

OWUFA OWUFB Output Data Rate

0

1

0

1

0

1

25Hz

50Hz

100Hz

200Hz

Table 16. Motion Wake Up Function Output Data Rate

INT_CTRL_REG1

This register controls the settings for the physical interrupt pin (7). Note that to properly change the

value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”.

R/W

0

R/W

0

R/W

IEN

Bit5

R/W

IEA

Bit4

R/W

IEL

R/W

IEU

Bit2

R/W

0

R/W

0

Reset Value

00010000

Bit7

Bit6

Bit3

Bit1

Bit0

I²C Address: 0x1Eh

IEN enables/disables the physical interrupt pin (7)

IEN = 0 – physical interrupt pin (7) is disabled

IEN = 1 – physical interrupt pin (7) is enabled

IEA sets the polarity of the physical interrupt pin (7)

IEA = 0 – polarity of the physical interrupt pin (7) is active low

IEA = 1 – polarity of the physical interrupt pin (7) is active high

IEL sets the response of the physical interrupt pin (7)

IEL = 0 – the physical interrupt pin (7) latches until it is cleared by reading INT_REL

IEL = 1 – the physical interrupt pin (7) will transmit one pulse with a period of 0.05ms

IEU sets an alternate unlatched response for the physical interrupt pin (7) when the motion

interrupt feature (WUF) only is enabled.

IEU = 0 – the physical interrupt pin (7) latches or pulses per the IEL bit until it is

cleared by reading INT_REL

IEU = 1 – the physical interrupt pin (7) will follow an unlatched response if the motion

interrupt feature is enabled

36 Thornwood Dr. – Ithaca, NY 14850

tel: 607-257-1080 – fax:607-257-1146

www.kionix.com - info@kionix.com

091222-00

Page 25 of 41

PART NUMBER:

2g Tri-axis Digital Accelerometer

Specifications

KXTF9-4100

Rev. 1

Dec-2009

INT_CTRL_REG2

This register controls motion detection axis enabling. Per Table 17, if an axis’ bit is set to one (1),

a motion on that axis will generate an interrupt. If it is set to zero (0), a motion on that axis will not

generate an interrupt. Note that to properly change the value of this register, the PC1 bit in

CTRL_REG1 must first be set to “0”.

R/W

XBW

Bit7

R/W

YBW

Bit6

R/W

ZBW

Bit5

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Reset Value

11100000

Bit4

Bit3

Bit2

Bit1

Bit0

I²C Address: 0x1Fh

Bit

Description

X-Axis Motion

Y-Axis Motion

Z-Axis Motion

XBW

YBW

ZBW

Table 17. Motion Detection Axis Enabling

INT_CTRL_REG3

This register controls the tap detection direction axis enabling. Per Table 18, if a direction’s bit is

set to one (1), a single or double tap in that direction will generate an interrupt. If it is set to zero

(0), a single or double tap in that direction will not generate an interrupt. Note that to properly

change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”.

R/W

0

R/W

0

R/W

TLEM

Bit5

R/W

TRIM

Bit4

R/W

TDOM

Bit3

R/W

TUPM

Bit2

R/W

TFDM

Bit1

R/W

TFUM

Bit0

Reset Value

00111111

Bit7

Bit6

I²C Address: 0x20h

Bit

Description

X Negative (X-)

X Positive (X+)

Y Negative (Y-)

Y Positive (Y+)

Z Negative (Z-)

Z Positive (Z+)

TLEM

TRIM

TDOM

TUPM

TFDM

TFUM

Table 18. Directional Tap^TMAxis Mask

36 Thornwood Dr. – Ithaca, NY 14850

tel: 607-257-1080 – fax:607-257-1146

www.kionix.com - info@kionix.com

091222-00

Page 26 of 41

PART NUMBER:

2g Tri-axis Digital Accelerometer

Specifications

KXTF9-4100

Rev. 1

Dec-2009

DATA_CTRL_REG

Read/write control register that configures the acceleration outputs. Note that to properly change

the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”.

R/W

0

R/W

0

R/W

HPFROA HPROB

Bit5 Bit4

R/W

0

R/W

OSAA

Bit2

R/W

OSAB

Bit1

R/W

OSAC

Bit0

Reset Value

00000010

Bit7

Bit6

Bit3

I²C Address: 0x21h

HPFROA, HPFROB sets the roll-off frequency for the first-order high-pass filter in

conjunction with the output data rate (OWUFA, OWUFB) that is chosen for the HPF

acceleration outputs that are used in the Motion Wake Up (WUF) application per Table 19.

Note that this roll-off frequency is also applied to the X, Y and Z high-pass filtered outputs.

High-Pass Filter Configuration

HPFROA HPFROB Beta HPF Roll-Off (Hz)

0

1

0

1

0

1

7/8

ODR / 50

ODR / 100

ODR / 200

ODR / 400

15/16

31/32

63/64

Table 19. High-Pass Filter Roll-Off Frequency

OSAA, OSAB, OSAC sets the output data rate (ODR) for the low-pass filtered

acceleration outputs per Table 20.

OSAA OSAB OSAC Output Data Rate

LPF Roll-Off

6.25Hz

0

1

0

1

0

1

0

1

0

1

0

1

0

1

12.5Hz

25Hz

12.5Hz

50Hz

25Hz

100Hz

50Hz

200Hz

100Hz

400Hz

200Hz

800Hz

400Hz

Does Not Exist

Table 20. LPF Acceleration Output Data Rate (ODR)

36 Thornwood Dr. – Ithaca, NY 14850

tel: 607-257-1080 – fax:607-257-1146

www.kionix.com - info@kionix.com

091222-00

Page 27 of 41

PART NUMBER:

2g Tri-axis Digital Accelerometer

Specifications

KXTF9-4100

Rev. 1

Dec-2009

TILT_TIMER

This register is the initial count register for the tilt position state timer (0 to 255 counts). Every count

is calculated as 1/ODR delay period, where the ODR is user-defined per Table 14. A new state must

be valid as many measurement periods before the change is accepted. Note that to properly change

the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”.

R/W

TSC7

Bit7

R/W

TSC6

Bit6

R/W

TSC5

Bit5

R/W

TSC4

Bit4

R/W

TSC3

Bit3

R/W

TSC2

Bit2

R/W

TSC1

Bit1

R/W

TSC0

Bit0

Reset Value

00000000

I²C Address: 0x28h

WUF_TIMER

This register is the initial count register for the motion detection timer (0 to 255 counts). Every

count is calculated as 1/ODR delay period, where the ODR is user-defined per Table 16. A new

state must be valid as many measurement periods before the change is accepted. Note that to

properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”.

R/W

Reset Value

00000000

WUFC7 WUFC6 WUFC5 WUFC4 WUFC3 WUFC2 WUFC1 WUFC0

Bit2

Bit7

Bit6

Bit5

Bit4

Bit3

Bit1

Bit0

I²C Address: 0x29h

TDT_TIMER

This register contains counter information for the detection of a double tap event. Every count is

calculated as 1/ODR delay period, where the ODR is user-defined per Table 15. TDT_TIMER

represents the minimum time separation between the first tap and the second tap in a double tap

event. The Kionix recommended default value is 0.3 seconds (0x78h). Note that to properly change

the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”.

R/W

TDTC7

Bit7

R/W

TDTC6

Bit6

R/W

TDTC5

Bit5

R/W

TDTC4

Bit4

R/W

TDTC3

Bit3

R/W

TDTC2

Bit2

R/W

TDTC1

Bit1

R/W

TDTC0

Bit0

Reset Value

01111000

I²C Address: 0x2Bh

36 Thornwood Dr. – Ithaca, NY 14850

tel: 607-257-1080 – fax:607-257-1146

www.kionix.com - info@kionix.com

091222-00

Page 28 of 41

PART NUMBER:

2g Tri-axis Digital Accelerometer

Specifications

KXTF9-4100

Rev. 1

Dec-2009

TDT_H_THRESH

This register represents the 9-bit jerk high threshold to determine if a tap is detected. The

Performance Index (PI) is the jerk signal that is expected to be less than this threshold, but greater

than the TDT_L_THRESH threshold during single and double tap events. Note that to properly

change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”. The Kionix

recommended default value is 182 (0xB6h) and the Performance Index is calculated as:

X’ = X(current) – X(previous)

Y’ = Y(current) – Y(previous)

Z’ = Z(current) – Z(previous)

PI = |X’| + |Y’| + |Z’|

Equation 1. Performance Index

R/W

TTH8

Bit7

R/W

TTH7

Bit6

R/W

TTH6

Bit5

R/W

TTH5

Bit4

R/W

TTH4

Bit3

R/W

TTH3

Bit2

R/W

TTH2

Bit1

R/W

TTH1

Bit0

Reset Value

10110110

I²C Address: 0x2Ch

TDT_L_THRESH

This register represents the 7-bit jerk low threshold to determine if a tap is detected. The

Performance Index (PI) is the jerk signal that is expected to be greater than this threshold and less

than the TDT_H_THRESH threshold during single and double tap events. This register also

contains the LSB of the TDT_H_THRESH threshold. The Kionix recommended default value is 26

(0x1Ah). Note that to properly change the value of this register, the PC1 bit in CTRL_REG1 must

first be set to “0”.

R/W

TTH0

Bit7

R/W

TTL6

Bit6

R/W

TTL5

Bit5

R/W

TTL4

Bit4

R/W

TTL3

Bit3

R/W

TTL2

Bit2

R/W

TTL1

Bit1

R/W

TTL0

Bit0

Reset Value

00011010

I²C Address: 0x2Dh

36 Thornwood Dr. – Ithaca, NY 14850

tel: 607-257-1080 – fax:607-257-1146

www.kionix.com - info@kionix.com

091222-00

Page 29 of 41

PART NUMBER:

2g Tri-axis Digital Accelerometer

Specifications

KXTF9-4100

Rev. 1

Dec-2009

TDT_TAP_TIMER

This register contains counter information for the detection of any tap event. Every count is

calculated as 1/ODR delay period, where the ODR is user-defined per Table 17. In order to ensure

that only tap events are detected, these time limits are used. A tap event must be above the

performance index threshold (TDT_THRESH) for at least the low limit (FTDL0 – FTDL2) and no

more than the high limit (FTDH0 – FTDH4). The Kionix recommended default value for the high

limit is 0.05 seconds and for the low limit is 0.005 seconds (0xA2h). Note that to properly change

the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”.

R/W

FTDH4

Bit7

R/W

FTDH3

Bit6

R/W

FTDH2

Bit5

R/W

FTDH1

Bit4

R/W

FTDH0

Bit3

R/W

FTDL2

Bit2

R/W

FTDL1

Bit1

R/W

FTDL0

Bit0

Reset Value

10100010

I²C Address: 0x2Eh

TDT_TOTAL_TIMER

This register contains counter information for the detection of a double tap event. Every count is

calculated as 1/ODR delay period, where the ODR is user-defined per Table 17. In order to ensure

that only tap events are detected, this time limit is used. This register sets the total amount of time

that the two taps in a double tap event can be above the PI threshold (TDT_L_THRESH). The

Kionix recommended default value for TDT_TOTAL_TIMER is 0.09 seconds (0x24h). Note that to

properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”.

R/W

STD7

Bit7

R/W

STD6

Bit6

R/W

STD5

Bit5

R/W

STD4

Bit4

R/W

STD3

Bit3

R/W

STD2

Bit2

R/W

STD1

Bit1

R/W

STD0

Bit0

Reset Value

00100100

I²C Address: 0x2Fh

36 Thornwood Dr. – Ithaca, NY 14850

tel: 607-257-1080 – fax:607-257-1146

www.kionix.com - info@kionix.com

091222-00

Page 30 of 41

PART NUMBER:

2g Tri-axis Digital Accelerometer

Specifications

KXTF9-4100

Rev. 1

Dec-2009

TDT_LATENCY_TIMER

This register contains counter information for the detection of a tap event. Every count is calculated

as 1/ODR delay period, where the ODR is user-defined per Table 17. In order to ensure that only

tap events are detected, this time limit is used. This register sets the total amount of time that the

tap algorithm will count samples that are above the PI threshold (TDT_L_THRESH) during a

potential tap event. It is used during both single and double tap events. However, reporting of

single taps on the physical interrupt pin (7) will occur at the end of the TDT_WINDOW_TIMER. The

Kionix recommended default value for TDT_LATENCY_TIMER is 0.1 seconds (0x28h). Note that

to properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”.

R/W

TLT7

Bit7

R/W

TLT6

Bit6

R/W

TLT5

Bit5

R/W

TLT4

Bit4

R/W

TLT3

Bit3

R/W

TLT2

Bit2

R/W

TLT1

Bit1

R/W

TLT0

Bit0

Reset Value

00101000

I²C Address: 0x30h

TDT_WINDOW_TIMER

This register contains counter information for the detection of single and double taps. Every count

is calculated as 1/ODR delay period, where the ODR is user-defined per Table 17. It defines the

time window for the entire tap event, single or double, to occur. Reporting of single taps on the

physical interrupt pin (7) will occur at the end of this tap window. The Kionix recommended default

value for TDT_WINDOW_TIMER is 0.4 seconds (0xA0h). Note that to properly change the value of

this register, the PC1 bit in CTRL_REG1 must first be set to “0”.

R/W

TWS7

Bit7

R/W

TWS6

Bit6

R/W

TWS5

Bit5

R/W

TWS4

Bit4

R/W

TWS3

Bit3

R/W

TWS2

Bit2

R/W

TWS1

Bit1

R/W

TWS0

Bit0

Reset Value

10100000

I²C Address: 0x31h

SELF_TEST

When 0xCA is written to this register, the MEMS self-test function is enabled. Electrostatic-

actuation of the accelerometer, results in a DC shift of the X, Y and Z axis outputs. Writing 0x00 to

this register will return the accelerometer to normal operation.

R/W

1

R/W

1

R/W

0

R/W

0

R/W

1

R/W

0

R/W

1

R/W

0

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

I²C Address: 0x3Ah

36 Thornwood Dr. – Ithaca, NY 14850

tel: 607-257-1080 – fax:607-257-1146

www.kionix.com - info@kionix.com

091222-00

Page 31 of 41

PART NUMBER:

2g Tri-axis Digital Accelerometer

Specifications

KXTF9-4100

Rev. 1

Dec-2009

WUF_THRESH

This register sets the acceleration threshold, WUF Threshold that is used to detect a general motion

input. The KXTF9 will ship from the factory with WUF_THRESH set to a change in acceleration of

0.5g. Note that to properly change the value of this register, the PC1 bit in CTRL_REG1 must first

be set to “0”.

R/W

Bit6

R/W

Bit5

R/W

Bit4

R/W

Bit3

R/W

Bit2

R/W

Reset Value

00001000

WUFTH7 WUFTH6 WUFTH5 WUFTH4 WUFTH3 WUFTH2 WUFTH1 WUFTH0

Bit7

Bit1

Bit0

I²C Address: 0x5Ah

TILT_ANGLE

This register sets the tilt angle that is used to detect the transition from Face-up/Face-down states

to Screen Rotation states. The KXTF9 ships from the factory with tilt angle set to a low threshold of

26°from horizontal. A different default tilt angle can be requested from the factory. Note that the

minimum suggested tilt angle is 10°. Note that to properly change the value of this register, the

PC1 bit in CTRL_REG1 must first be set to “0”.

R/W

TA7

Bit7

R/W

TA6

Bit6

R/W

TA5

Bit5

R/W

TA4

Bit4

R/W

TA3

Bit3

R/W

TA2

Bit2

R/W

TA1

Bit1

R/W

TA0

Bit0

Reset Value

00001100

I²C Address: 0x5Ch

HYST_SET

This register sets the Hysteresis that is placed in between the Screen Rotation states. The KXTF9

ships from the factory with HYST_SET set to +/-15°of hysteresis. A different default hysteresis can

be requested from the factory. Note that when writing a new value to this register the current

values of RES0, RES1, RES2 and RES3 must be preserved. These values are set at the factory

and must not change. Note that to properly change the value of this register, the PC1 bit in

CTRL_REG1 must first be set to “0”.

R/W

RES2

Bit7

R/W

RES1

Bit6

R/W

RES0

Bit5

R/W

HYST4 HYST3 HYST2 HYST1 HYST0

Bit4 Bit3 Bit2 Bit1 Bit0

I²C Address: 0x5Fh

R/W

Reset Value

---10100

36 Thornwood Dr. – Ithaca, NY 14850

tel: 607-257-1080 – fax:607-257-1146

www.kionix.com - info@kionix.com

091222-00

Page 32 of 41

PART NUMBER:

2g Tri-axis Digital Accelerometer

Specifications

KXTF9-4100

Rev. 1

Dec-2009

KXTF9 Embedded Applications

Orientation Detection Feature

The orientation detection feature of the KXTF9 will report changes in face up, face down, +/- vertical and

+/- horizontal orientation. This intelligent embedded algorithm considers very important factors that provide

accurate orientation detection from low cost tri-axis accelerometers. Factors such as: hysteresis, device

orientation angle and delay time are described below as these techniques are utilized inside the KXTF9.

Hysteresis

A 45° tilt angle threshold seems like a good choice because it is halfway between 0° and 90°.

However, a problem arises when the user holds the device near 45°. Slight vibrations, noise and

inherent sensor error will cause the acceleration to go above and below the threshold rapidly and

randomly, so the screen will quickly flip back and forth between the 0° and the 90° orientations.

This problem is avoided in the KXTF9 by choosing a 30°threshold angle. With a 30°threshold, the

screen will not rotate from 0°to 90°until the device is tilted to 60°(30°from 90°). To rotate back to

0°, the user must tilt back to 30°, thus avoiding the screen flipping problem. This example

essentially applies +/- 15°of hysteresis in between the four screen rotation states. Table 21 shows

the acceleration limits implemented for φ _T=30°.

Orientation X Acceleration (g) Y Acceleration (g)

0°/360°

90°

180°

270°

-0.5 < a_x< 0.5

a_x> 0.866

-0.5 < a_x< 0.5

a_x< -0.866

a_y> 0.866

-0.5 < a_y< 0.5

a_y< -0.866

-0.5 < a_y< 0.5

Table 21. Acceleration at the four orientations with +/- 15°of hysteresis

The KXTF9 allows the user to change the amount of hysteresis in between the four screen rotation

states. By simply writing to the HYST_SET register, the user can adjust the amount of hysteresis

up to +/- 45°. The plot in Figure 1 shows the typical amount of hysteresis applied for a given digital

count value of HYST_SET.

36 Thornwood Dr. – Ithaca, NY 14850

tel: 607-257-1080 – fax:607-257-1146

www.kionix.com - info@kionix.com

091222-00

Page 33 of 41

PART NUMBER:

2g Tri-axis Digital Accelerometer

Specifications

KXTF9-4100

Rev. 1

Dec-2009

HYST_SET vs Hysteresis

50

45

40

35

30

25

20

15

10

5

Hysteresis

0

5

10

15

20

25

30

HYST_SET Value (Counts)

Figure 1. HYST_SET vs Hysteresis

Device Orientation Angle (aka Tilt Angle)

To ensure that horizontal and vertical device orientation changes are detected, even when it isn’t in

the ideal vertical orientation – where the angle θ in Figure 2 is 90°, the KXTF9 considers device

orientation angle in its algorithm.

Angle

θ

Figure 2. Device Orientation Angle

As the angle in Figure 2 is decreased, the maximum gravitational acceleration on the X-axis or Y-

axis will also decrease. Therefore, when the angle becomes small enough, the user will not be able

to make the screen orientation change. When the device orientation angle approaches 0°(device

is flat on a desk or table), a_x= a_y= 0g, a_z= +1g, and there is no way to determine which way the

screen should be oriented, the internal algorithm determines that the device is in either the face-up

or face-down orientation, depending on the sign of the z-axis. The KXTF9 will only change the

36 Thornwood Dr. – Ithaca, NY 14850

tel: 607-257-1080 – fax:607-257-1146

www.kionix.com - info@kionix.com

091222-00

Page 34 of 41

PART NUMBER:

2g Tri-axis Digital Accelerometer

Specifications

KXTF9-4100

Rev. 1

Dec-2009

screen orientation when the orientation angle is above the factory-defaulted/user-defined threshold

set in the TILT_ANGLE register. Equation 2 can be used to determine what value to write to the

TILT_ANGLE register to set the device orientation angle.

TILT_ANGLE (counts) = sin θ * (32 (counts/g))

Equation 2. Tilt Angle Threshold

Tilt Timer

The 8-bit register, TILT_TIMER can be used to qualify changes in orientation. The KXTF9 does this

by incrementing a counter with a size that is specified by the value in TILT_TIMER for each set of

acceleration samples to verify that a change to a new orientation state is maintained. A user

defined output data rate (ODR) determines the time period for each sample. Equation 3 shows how

to calculate the TILT_TIMER register value for a desired delay time.

TILT_TIMER (counts) = Delay Time (sec) x ODR (Hz)

Equation 3. Tilt Position Delay Time

Motion Interrupt Feature Description

The Motion interrupt feature of the KXTF9 reports qualified changes in the high-pass filtered acceleration

based on the Wake Up (WUF) threshold. If the high-pass filtered acceleration on any axis is greater than

the user-defined wake up threshold (WUF_THRESH), the device has transitioned from an inactive state to

an active state. When configured in the unlatched mode, the KXTF9 will report when the motion event

finished and the device has returned to an inactive state. Equation 4 shows how to calculate the

WUF_THRESH register value for a desired wake up threshold.

WUF_THRESH (counts) = Wake Up Threshold (g) x 16 (counts/g)

Equation 4. Wake Up Threshold

A WUF (WUF_TIMER) 8-bit raw unsigned value represents a counter that permits the user to qualify each

active/inactive state change. Note that each WUF Timer count qualifies 1 (one) user-defined ODR period

(OWUF). Equation 5 shows how to calculate the WUF_TIMER register value for a desired wake up delay

time.

WUF_TIMER (counts) = Wake Up Delay Time (sec) x OWUF (Hz)

Equation 5. Wake Up Delay Time

36 Thornwood Dr. – Ithaca, NY 14850

tel: 607-257-1080 – fax:607-257-1146

091222-00

www.kionix.com - info@kionix.com

Page 35 of 41

PART NUMBER:

2g Tri-axis Digital Accelerometer

Specifications

KXTF9-4100

Rev. 1

Dec-2009

Figure 3 below shows the latched response of the motion detection algorithm with WUF Timer = 10 counts.

Typical Motion Interrupt Example

HPF Acceleration

WUF Threshold

0g

10

WUF Timer

Ex: Delay Counter = 10

Motion

Inactive

Figure 3. Latched Motion Interrupt Response

36 Thornwood Dr. – Ithaca, NY 14850

tel: 607-257-1080 – fax:607-257-1146

091222-00

www.kionix.com - info@kionix.com

Page 36 of 41

PART NUMBER:

2g Tri-axis Digital Accelerometer

Specifications

KXTF9-4100

Rev. 1

Dec-2009

Figure 4 below shows the unlatched response of the motion detection algorithm with WUF Timer = 10

counts.

Typical Motion Interrupt Example

HPF Acceleration

WUF Threshold

0g

10

WUF Timer

Ex: Delay Counter = 10

Motion

Inactive

Figure 4. Unlatched Motion Interrupt Response

36 Thornwood Dr. – Ithaca, NY 14850

tel: 607-257-1080 – fax:607-257-1146

091222-00

www.kionix.com - info@kionix.com

Page 37 of 41

PART NUMBER:

2g Tri-axis Digital Accelerometer

Specifications

KXTF9-4100

Rev. 1

Dec-2009

Directional Tap Detection Feature Description

The Directional Tap Detection feature of the KXTF9 recognizes single and double tap inputs and reports

the acceleration axis and direction that each tap occurred. Eight performance parameters, as well as a

user-selectable ODR are used to configure the KXTF9 for a desired tap detection response.

Performance Index

The Directional Tap^TMdetection algorithm uses low and high thresholds to help determine when a

tap event has occurred. A tap event is detected when the previously described jerk summation

exceeds the low threshold (TDT_L_THRESH) for more than the tap detection low limit, but less

than the tap detection high limit as contained in TDT_TAP_TIMER. Samples that exceed the high

limit (TDT_H_THRESH) will be ignored. Figure 5 shows an example of a single tap event meeting

the performance index criteria.

Calculated Performance Index

PI

180

: Sampled Data

160

140

120

100

80

60

40

TDT_L_THRESH

20

0

3.14

3.15

3.16

3.17

3.18

3.19

3.2

3.21

time(sec)

Figure 5. Jerk Summation vs Threshold

36 Thornwood Dr. – Ithaca, NY 14850

tel: 607-257-1080 – fax:607-257-1146

www.kionix.com - info@kionix.com

091222-00

Page 38 of 41

PART NUMBER:

2g Tri-axis Digital Accelerometer

Specifications

KXTF9-4100

Rev. 1

Dec-2009

Single Tap Detection

The latency timer (TDT_LATENCY_TIMER) sets the time period that a tap event will only be

characterized as a single tap. A second tap has to occur outside of the latency timer. If a second

tap occurs inside the latency time, it will be ignored as it occurred too quickly. The single tap will be

reported at the end of the TDT_WINDOW_TIMER. Figure 6 shows a single tap event meeting the

PI, latency and window requirements.

Calculated Performance Index

160

PI

140

TDT_WINDOW_TIMER

120

100

TDT_LATENCY_TIMER

80

60

40

TDT_L_THRESH

20

0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

3

3.1

time(sec)

Figure 6. Single Directional Tap^TMTiming

36 Thornwood Dr. – Ithaca, NY 14850

tel: 607-257-1080 – fax:607-257-1146

www.kionix.com - info@kionix.com

091222-00

Page 39 of 41

PART NUMBER:

2g Tri-axis Digital Accelerometer

Specifications

KXTF9-4100

Rev. 1

Dec-2009

Double Tap Detection

An event can be characterized as a double tap only if the second tap crosses the performance

index (TDT_L_THRESH) outside the TDT_TIMER. This means that the TDT_TIMER determines

the minimum time separation that must exist between the two taps of a double tap event. Similar to

the single tap, the second tap event must exceed the performance index for the time limit contained

in TDT_TAP_TIMER.

The double tap will be reported at the end of the second

TDT_LATENCY_TIMER. Figure 7 shows a double tap event meeting the PI, latency and window

requirements.

Calculated Performance Index

PI

TDT_WINDOW_TIMER

200

150

TDT_TIMER

100

TDT_LATENCY_TIMER

50

TDT_L_THRESH

0

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

time(sec)

Figure 7. Double Directional Tap^TMTiming

36 Thornwood Dr. – Ithaca, NY 14850

tel: 607-257-1080 – fax:607-257-1146

www.kionix.com - info@kionix.com

091222-00

Page 40 of 41

PART NUMBER:

2g Tri-axis Digital Accelerometer

Specifications

KXTF9-4100

Rev. 1

Dec-2009

Revision History

REVISION DESCRIPTION DATE

Initial Release

1

18-Dec-2009

"Kionix" is a registered trademark of Kionix, Inc. Products described herein are protected by patents issued or pending. No license is granted by implication or

otherwise under any patent or other rights of Kionix. The information contained herein is believed to be accurate and reliable but is not guaranteed. Kionix does not

assume responsibility for its use or distribution. Kionix also reserves the right to change product specifications or discontinue this product at any time without prior

notice. This publication supersedes and replaces all information previously supplied.

36 Thornwood Dr. – Ithaca, NY 14850

tel: 607-257-1080 – fax:607-257-1146

091222-00

www.kionix.com - info@kionix.com

Page 41 of 41

厂商	型号	描述	页数
CK-COMPONENTS	KXT	[ Ultra Low Profile Top Actuated ]	2 页
CK-COMPONENTS	KXT111LHS	[ Ultra Low Profile Top Actuated ]	2 页
CK-COMPONENTS	KXT121LHS	[ Ultra Low Profile Top Actuated ]	2 页
CK-COMPONENTS	KXT131LHS	[ Ultra Low Profile Top Actuated ]	2 页
CK-COMPONENTS	KXT2	[ Double Action Ultra Low Profile Top Actuated ]	2 页
CK-COMPONENTS	KXT211LHS	[ Double Action Ultra Low Profile Top Actuated ]	2 页
CK-COMPONENTS	KXT3	[ High number of cycle ]	2 页
CK-COMPONENTS	KXT311LHS	[ High number of cycle ]	2 页
CK-COMPONENTS	KXT321LHS	[ High number of cycle ]	2 页
CK-COMPONENTS	KXT331LHS	[ High number of cycle ]	2 页