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MXT224

型号:

MXT224

描述:

的maXTouch 224路触摸屏传感器IC[ maXTouch 224-channel Touchscreen Sensor IC ]

品牌:

Narda-ATM[ Narda-ATM ]

页数:

12 页

PDF大小:

143 K

Features  
maXTouchTouchscreen  
– True 12-bit multi-touch with independent XY tracking for up to 10 concurrent  
touches in real time with touch size reporting  
– Up to 4.3 inch diagonal screen size supported with 10 mm “pinch” separation  
– Up to 10.1 inch support with correspondingly wider “pinch”  
Number of Channels  
– Up to 224 (subject to other configuration limitations)  
– Electrode grid configurations up to 20 X by 10 Y lines supported (subject to 30  
total pins and a maximum of 14 Y lines)  
maXTouch™  
224-channel  
Touchscreen  
Sensor IC  
maXTouch Touch Key Support  
– Up to 32 channels can be allocated as fixed keys (subject to other configurations)  
Zero Additional Part Count  
– 16 X by 14 Y matrix (224 channels) implementable with power bypass capacitors only  
Signal Processing  
– Advanced digital filtering using both hardware engine and firmware  
– Self-calibration  
– Auto drift compensation  
– Adjacent Key Suppression® (AKS) technology  
– Grip and face suppression  
mXT224  
– Reports one-touch and two-touch gestures  
– Down-scaling and clipping support to match LCD resolution  
– Ultra-fast start-up and calibration for best user experience  
– Supports axis flipping and axis switch-over for portrait and landscape modes  
Scan Speed  
Summary  
– Maximum single touch >250Hz, subject to configuration  
– Configurable to allow power/speed optimization  
– Programmable timeout for automatic transition from active to idle states  
Response Times  
– Initial latency <10 ms for first touch from idle, subject to configuration  
Sensors  
– Works with PET or glass sensors  
– Works with all proprietary sensor patterns recommended by Atmel®  
– Works with passive stylus  
Panel Thickness  
– Glass up to 3 mm, screen size dependent  
– Plastic up to 1.5 mm, screen size dependent  
Interface  
– I2C-compatible slave mode 400 kHz  
Dual-rail Power  
– Interface 1.8V to 3.3V nominal, analog 2.7V to 3.3V nominal  
Power Consumption  
Note: This is a summary document.  
A complete document is available  
under NDA. For more information  
contact www.atmel.com/touchscreen.  
– Idle 80Hz: <1.8 mW, subject to configuration  
– One Touch Active 80Hz: 3.9 mW, subject to configuration  
– Sleep: 4.5 µW  
Package  
– 49-ball UFBGA 5 x 5 x 0.6 mm, 0.65 ball pitch  
– 49-ball VFBGA 5 x 5 x 1 mm, 0.65 ball pitch  
– 48-pin QFN 6 x 6 x 0.6 mm, 0.4 mm pin pitch  
9530BS–AT42–10/09  
1. Pinout and Schematic  
1.1  
Pinout Configuration  
1.1.1  
49-ball UFBGA/VFBGA  
Top View  
Bottom View  
3
5
6
6
5
3
1
2
4
7
7
4
2
1
A
B
C
D
E
F
A
B
C
D
E
F
mXT224  
G
G
1.1.2  
48-pin QFN  
48  
46 45  
43  
41 40 39 38 37  
42  
47  
44  
Y13  
1
2
3
4
5
6
7
8
9
36  
Y0  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
GND  
GND  
AVDD  
X8  
AVDD  
X7  
X9  
X6  
X10  
X11  
X12  
X13  
X14  
X15  
GND  
X5  
mXT224  
X4  
X3  
X2  
10  
11  
12  
X1  
X0  
GND  
13 14 15 16 17 18 19 20  
23  
24  
21 22  
2
mXT224  
9530BS–AT42–10/09  
mXT224  
1.2  
Pinout Descriptions  
1.2.1  
49-ball UFBGA/VFBGA  
Table 1-1.  
Ball  
A1  
Pin Listing  
Name  
AVDD  
Y12  
Y10  
Y8  
Type  
P
I/O  
I/O  
I
Comments  
If Unused, Connect To...  
Analog power  
A2  
Y line connection or X line in extended mode  
Y line connection or X line in extended mode  
Y line connection  
Leave open  
Leave open  
Leave open  
Leave open  
Leave open  
Leave open  
Leave open  
A3  
A4  
A5  
Y6  
I
Y line connection  
A6  
Y4  
I
Y line connection  
A7  
Y2  
I
Y line connection  
B1  
X8  
O
P
I/O  
I
X matrix drive line  
B2  
GND  
Y11  
Y9  
Ground  
B3  
Y line connection or X line in extended mode  
Y line connection  
Leave open  
Leave open  
Leave open  
Leave open  
Leave open  
Leave open  
Leave open  
Leave open  
Leave open  
Leave open  
B4  
B5  
Y5  
I
Y line connection  
B6  
Y1  
I
Y line connection  
B7  
Y0  
I
Y line connection  
C1  
C2  
C3  
C4  
C5  
C6  
C7  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
E1  
X10  
X9  
O
O
I/O  
I
X matrix drive line  
X matrix drive line  
Y13  
Y7  
Y line connection or X line in extended mode  
Y line connection  
Y3  
I
Y line connection  
GND  
AVDD  
X12  
X13  
X11  
GND  
X7  
P
P
O
O
O
P
O
O
O
O
O
I
Ground  
Analog power  
X matrix drive line  
Leave open  
Leave open  
Leave open  
X matrix drive line  
X matrix drive line  
Ground  
X matrix drive line  
Leave open  
Leave open  
Leave open  
Leave open  
Leave open  
Leave open or Vdd  
X5  
X matrix drive line  
X6  
X matrix drive line  
X14  
X15  
RESET  
X matrix drive line  
E2  
X matrix drive line  
E3  
Reset low; has internal 30 kto 60 kpull-up resistor  
Input: GND  
Output: leave open  
E4  
GPIO1  
I/O  
General purpose I/O  
3
9530BS–AT42–10/09  
Table 1-1.  
Pin Listing (Continued)  
Ball  
E5  
E6  
E7  
F1  
Name  
X1  
Type  
O
Comments  
If Unused, Connect To...  
X matrix drive line  
X matrix drive line  
X matrix drive line  
Digital power  
Leave open  
X3  
O
Leave open  
X4  
O
Leave open  
VDD  
GND  
SCL  
P
F2  
P
Ground  
F3  
OD  
Serial Interface Clock  
GPIO3/  
MOSI  
General purpose I/O /  
Debug data  
Input: GND  
Output: leave open  
F4  
I/O  
F5  
F6  
F7  
G1  
G2  
GND  
CHG  
X2  
P
OD  
O
Ground  
State change interrupt  
X matrix drive line  
No connection  
Leave open  
Leave open  
N/C  
SDA  
OD  
Serial Interface Data  
GPIO0/  
SYNC  
General purpose I/O  
External synchronization  
Input: GND  
Output: leave open  
G3  
G4  
I/O  
I/O  
GPIO2/  
SCK  
General purpose I/O /  
Debug clock  
Input: GND  
Output: leave open  
G5  
G6  
G7  
VDD  
ADDR_SEL  
X0  
P
I
Digital power  
I2C-compatible address select  
O
X matrix drive line  
Leave open  
I
Input only  
I/O  
Input and output  
O
P
Output only, push-pull  
Ground or power  
OD  
Open drain output  
4
mXT224  
9530BS–AT42–10/09  
mXT224  
1.2.2  
48-pin QFN  
Table 1-2.  
Pin Listing  
Name  
Y13  
Pin  
1
Type  
I/O  
P
Comments  
If Unused, Connect To...  
Y line connection or X line in extended mode  
Ground  
Leave open  
2
GND  
AVDD  
X8  
3
P
Analog power  
4
O
X matrix drive line  
X matrix drive line  
X matrix drive line  
X matrix drive line  
X matrix drive line  
X matrix drive line  
X matrix drive line  
X matrix drive line  
Ground  
Leave open  
Leave open  
Leave open  
Leave open  
Leave open  
Leave open  
Leave open  
Leave open  
5
X9  
O
6
X10  
O
7
X11  
O
8
X12  
O
9
X13  
O
10  
11  
12  
13  
14  
15  
16  
17  
X14  
O
X15  
O
GND  
VDD  
RESET  
N/C  
P
P
Digital power  
I
Reset low; has internal 30 kto 60 kpull-up resistor  
No connection  
Leave open or Vdd  
Leave open  
SDA  
SCL  
OD  
OD  
Serial Interface Data  
Serial Interface Clock  
GPIO0/  
SYNC  
General purpose I/O  
External synchronization  
Input: GND  
Output: leave open  
18  
I/O  
Input: GND  
Output: leave open  
19  
20  
21  
GPIO1  
VDD  
I/O  
P
General purpose I/O  
Digital power  
GPIO2/  
SCK  
General purpose I/O /  
Debug clock  
Input: GND  
Output: leave open  
I/O  
GPIO3/  
MOSI  
General purpose I/O /  
Debug data  
Input: GND  
Output: leave open  
22  
I/O  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
ADDR_SEL  
I
OD  
P
I2C-compatible address select  
State change interrupt  
Ground  
CHG  
GND  
X0  
O
O
O
O
O
O
O
X matrix drive line  
X matrix drive line  
X matrix drive line  
X matrix drive line  
X matrix drive line  
X matrix drive line  
X matrix drive line  
Leave open  
Leave open  
Leave open  
Leave open  
Leave open  
Leave open  
Leave open  
X1  
X2  
X3  
X4  
X5  
X6  
5
9530BS–AT42–10/09  
Table 1-2.  
Pin Listing (Continued)  
Pin  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
Name  
X7  
Type  
Comments  
If Unused, Connect To...  
Leave open  
O
X matrix drive line  
AVDD  
GND  
Y0  
P
Analog power  
P
Ground  
I
Y line connection  
Leave open  
Leave open  
Leave open  
Leave open  
Leave open  
Leave open  
Leave open  
Leave open  
Leave open  
Leave open  
Leave open  
Leave open  
Leave open  
Y1  
I
Y line connection  
Y2  
I
Y line connection  
Y3  
I
Y line connection  
Y4  
I
Y line connection  
Y5  
I
Y line connection  
Y6  
I
I
Y line connection  
Y7  
Y line connection  
Y8  
I
Y line connection  
Y9  
I
Y line connection  
Y10  
Y11  
Y12  
I/O  
I/O  
I/O  
Y line connection or X line in extended mode  
Y line connection or X line in extended mode  
Y line connection or X line in extended mode  
I
Input only  
I/O  
Input and output  
O
P
Output only, push-pull  
Ground or power  
OD  
Open drain output  
6
mXT224  
9530BS–AT42–10/09  
mXT224  
1.3  
Schematic  
1.3.1  
49-ball UFBGA/VFBGA  
Regulated Regulated  
AVDD  
NOTE: Bypass capacitors must be X7R or  
X5R and placed <5 mm away from chip.  
VDD  
100 nF  
1 mF  
100 nF  
1 mF  
G7  
E5  
F7  
E6  
E7  
D6  
D7  
D5  
B1  
C2  
C1  
D3  
D1  
D2  
E1  
E2  
X0  
X1  
X2  
E4  
G4  
F4  
GPIO1  
X3  
GPIO2/SCK  
GPIO3/MOSI  
X4  
VDD  
X5  
X6  
X7  
X8  
mXT224  
Rp  
Rp  
X9  
X10  
X11  
X12  
X13  
X14  
X15  
G2  
F3  
SDA  
SDA  
SCL  
I2C-COMPATIBLE  
SCL  
G1  
E3  
N/C  
VDD  
RESET  
C3  
A2  
B3  
A3  
X16/Y13  
X17/Y12  
X18/Y11  
X19/Y10  
G3  
GPIO0/SYNC  
Rc  
F6  
B4  
A4  
C4  
A5  
B5  
A6  
C5  
A7  
B6  
B7  
CHG  
CHG  
Y9  
Y8  
Y7  
Y6  
Y5  
Y4  
Y3  
Y2  
Y1  
Y0  
I2C-COMPATIBLE  
G6  
ADDR_SEL  
ADDRESS SELECT  
B2  
C6  
D4  
F2  
F5  
GND  
GND  
GND  
GND  
GND  
* NOTE: Y10 to Y13 scan lines may be  
used as additional X drive lines in  
extended mode (a 100W resistor must  
be added to each additional line).  
7
9530BS–AT42–10/09  
1.3.2  
48-pin QFN  
Regulated Regulated  
AVDD  
NOTE: Bypass capacitors must be X7R or  
X5R and placed <5 mm away from chip.  
VDD  
100 nF  
1 mF  
100 nF  
1 mF  
26  
27  
28  
29  
30  
31  
32  
33  
4
X0  
X1  
X2  
19  
21  
22  
GPIO1  
X3  
GPIO2/SCK  
GPIO3/MOSI  
X4  
VDD  
X5  
X6  
X7  
X8  
mXT224  
5
Rp  
Rp  
X9  
6
X10  
X11  
X12  
X13  
X14  
X15  
7
16  
17  
SDA  
SDA  
SCL  
8
I2C-COMPATIBLE  
9
SCL  
10  
11  
15  
14  
N/C  
VDD  
RESET  
1
X16/Y13  
X17/Y12  
X18/Y11  
X19/Y10  
48  
47  
46  
18  
GPIO0/SYNC  
Rc  
24  
23  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
CHG  
CHG  
Y9  
Y8  
Y7  
Y6  
Y5  
Y4  
Y3  
Y2  
Y1  
Y0  
I2C-COMPATIBLE  
ADDR_SEL  
ADDRESS SELECT  
2
12  
25  
35  
GND  
GND  
GND  
GND  
* NOTE: Y10 to Y13 scan lines may be  
used as additional X drive lines in  
extended mode (a 100W resistor must  
be added to each additional line).  
8
mXT224  
9530BS–AT42–10/09  
mXT224  
2. Overview of the mXT224  
2.1  
Introduction  
The mXT224 (AT42QT602240) uses a unique charge-transfer acquisition engine to implement  
the QMatrixcapacitive sensing method patented by Atmel®. This allows the measurement of  
up to 224 mutual capacitance nodes in under 1 ms. Coupled with a state-of-the-art XMEGA™  
CPU, the entire touchscreen sensing solution can measure, classify and track a single finger  
touch every 4 ms if required.  
The acquisition engine uses an optimal measurement approach to ensure almost complete  
immunity from parasitic capacitance on the receiver inputs (Y lines). The engine includes  
sufficient dynamic range to cope with touchscreen mutual capacitances spanning 0.5 pF to 5 pF,  
allowing great flexibility for use with Atmel’s proprietary ITO pattern designs. One and two layer  
ITO sensors are possible using glass or PET substrates.  
The main AVR® XMEGA CPU has, under its control, two powerful, yet low power,  
microsequencer coprocessors. These combine to allow the signal acquisition, preprocessing,  
postprocessing and housekeeping to be partitioned in an efficient and flexible way. This gives  
ample scope for sensing algorithms, touch tracking or advanced shape-based filtering. An  
in-circuit reflash can be performed over the chip’s hardware-driven two-wire interface  
(I2C-compatible).  
Overall, the mXT224 represents a step improvement over competing technologies, providing a  
near optimal mix of low power, small size and low part count, while offering unrivalled true  
multitouch performance.  
9
9530BS–AT42–10/09  
Revision History  
Revision Number  
Revision AS – September 2009 Initial release for chip revision 1.4  
Revision BS – October 2009 QFN package details added  
History  
10  
mXT224  
9530BS–AT42–10/09  
mXT224  
Notes  
11  
9530BS–AT42–10/09  
Headquarters  
International  
Atmel Corporation  
2325 Orchard Parkway  
San Jose, CA 95131  
USA  
Tel: 1(408) 441-0311  
Fax: 1(408) 487-2600  
Atmel Asia  
Atmel Europe  
Le Krebs  
Atmel Japan  
9F, Tonetsu Shinkawa Bldg.  
1-24-8 Shinkawa  
Chuo-ku, Tokyo 104-0033  
Japan  
Tel: (81) 3-3523-3551  
Fax: (81) 3-3523-7581  
Unit 01-05 & 16, 19/F  
BEA Tower, Millennium City 5  
418 Kwun Tong Road  
Kwun Tong  
Kowloon  
Hong Kong  
8, Rue Jean-Pierre Timbaud  
BP 309  
78054 Saint-Quentin-en-  
Yvelines Cedex  
France  
Tel: (852) 2245-6100  
Fax: (852) 2722-1369  
Tel: (33) 1-30-60-70-00  
Fax: (33) 1-30-60-71-11  
Touch Technology Division  
1 Mitchell Point  
Ensign Way  
Hamble  
Southampton  
Hampshire SO31 4RF  
United Kingdom  
Tel: (44) 23-8056-5600  
Fax: (44) 23-8045-3939  
Product Contact  
Web Site  
Technical Support  
Sales Contact  
www.atmel.com  
touch@atmel.com  
www.atmel.com/contacts  
Literature Requests  
www.atmel.com/literature  
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellec-  
tual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMELS TERMS AND CONDITIONS  
OF SALE LOCATED ON ATMELS WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY  
WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTIC-  
ULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL  
OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMA-  
TION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAM-  
AGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make  
changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein.  
Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended,  
authorized, or warranted for use as components in applications intended to support or sustain life.  
© 2009 Atmel Corporation. All rights reserved. Atmel®, Atmel logo and combinations thereof, AVR®, Adjacent Key Suppression® and others are  
registered trademarks, maXTouch, AKS, QMatrix, XMEGAand others are trademarks of Atmel Corporation or its subsidiaries. Other terms  
and product names may be registered trademarks or trademarks of others.  
9530BS–AT42–10/09  
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