IDT5V925BI Data Sheet
PROGRAMMABLE LVCMOS/LVTTL CLOCK GENERATOR
How to Use the IDT5V925BI
The IDT5V925BI is a general-purpose phase-locked loop (PLL) that
can be used as a zero delay buffer or a clock multiplier. It generates
three outputs at the VCO frequency and one output at the VCO
frequency divided by n, where n is determined by the Mode/
Frequency Select input pins S0 and S1. The PLL will adjust the VCO
frequency (within the limits of the Function Table) to ensure that the
input frequency equals the Q/N frequency.
By connecting one of the 49FCT3505 outputs to the FB input of the
IDT5V925BI, the propagation delay from CLKIN to the output of the
49FCT3505 will be nearly zero. To ensure PLL stability, only one
49FCT3505 should be included between Q/N and FB.
The second way to drive the input of the IDT5V925BI is via an
external crystal. When connecting an external crystal to pins 5 and 6,
the X2 pin must be shorted to the CLKIN (pin 7) as shown in Figure
3. To reduce the parasitic between the external crystal and the
IDT5V925BI, it is recommended to connect the crystal as close as
possible to the X1 and X2 pins.
The IDT5V925BI can accept two types of input signals. The first is a
reference clock generated by another device on the board which
needs to be reproduced with a minimal delay between the incoming
clock and output. The second is an external crystal. When used in the
first mode, the crystal input (X1) should be tied to ground and the
crystal output (X2) should be left unconnected.
FB
By connecting Q/N to FB (see Figure 1), the IDT5V925BI not only
becomes a zero delay buffer, but also a clock multiplier. With proper
selection of S0 and S1, the Q0–Q2 outputs will generate two, three,
or up to eight times the input clock frequency. Make sure that the
input and output frequency specifications are not violated (refer to
Function Table). There are some applications where higher fan-out
is required. These kinds of applications could be addressed by using
the IDT5V925BI in conjunction with a clock buffer such as the
49FCT3805. Figure 2 shows how higher fan-out with different clock
rates can be generated.
5V925
Q/N
CLKIN
Q0
Q1
Q2
X2
XTAL
OSC
X1
S0
S1
Figure 3
One of the questions often asked is what is the accuracy of our clock
generators? In applications where clock synthesizers are used, the
terms frequency accuracy and frequency error are used
interchangeably. Here, frequency accuracy (or error) is based on two
factors. One is the input frequency and the other is the multiplication
factor. Clock multipliers (or synthesizers) are governed by the
equation:
FB
Q/N
CLKIN
Q0
Q1
Q2
5V925
X2
X1
M
----
FOUT =
× FIN
N
S0
S1
Where “M” is the feedback divide and “N” is the reference divide. If
the ratio of M/N is not an integer, then the output frequency will not
be an exact multiple of the input. On the other hand, if the ratio is a
whole number, the output clock would be an exact multiple of the
input. In the case of IDT5V925BI, since the reference divide (“N”) is
“1”, the equation is a strong function of the feedback divide (“M”). In
addition, since the feedback is an integer, the output frequency error
(or accuracy) is merely a function of how accurate the input is. For
instance, IDT5V925BI could accept two forms of input, one from a
crystal oscillator (see Figure 1) and the other from a crystal (see
Figure 3). By using a 20MHz clock with a multiplication factor of 5
(with an accuracy of 30 parts per million), one can easily have three
copies of 100MHz of clock with 30ppm of accuracy. Frequency
accuracy is defined by the following equation:
Figure 1
FB
INA
5 COPIES
OF Q/N
Q/N
CLKIN
X2
5V925
49FCT3805
INB
5 COPIES
OF Q
X1
Q[2:0]
Accuracy = Measured Frequency – Nominal Frequency x 106
Nominary Frequency
S0
S1
Where measured frequency is the average frequency over certain
number of cycles (typically 10,000) and the nominal frequency is the
desired frequency.
Figure 2
IDT5V925BQGI REVISION B JANUARY 21, 2011
9
©2011 Integrated Device Technology, Inc.
