The length of this burst is an important
parameter as it is directly related to the signal
value. The burst duration also affects the
response time of the sensor; the larger Cs is, the
longer the burst, the slower the possible
acquisition rate.
2.2 Tacq - Acquire Response Time
The time from the /REQ or 1W line going low
until the completion of data transmission is
Tacq. Tacq depends on the acquisition burst
length as well as the serial transmission time.
SPI Mode: In SPI mode Tacq depends in part on
the serial clock speed and the space between
the returned high and low bytes. In SPI slave
mode the clock speed and the inter-byte spacing
time Tbdly is determine by the host. In SPI
Master mode these timings are set by Setup
parameters SCD and MLS.
1W mode: Tacq depends in part on the Baud
rate as well as the inter-byte spacing. The Baud
rate is auto-set by the trigger pulse width; the
inter-byte spacing is set by the MLS parameter.
See Section 4.
2.3 Tbs - Burst Spacing
Figure 2-1 Signal Acquisition - Slave SPI Mode
Burst spacing is the time from the start of one
acquisition burst to the start of the next burst. It
depends on the host’s trigger rate on the /REQ or 1W pin.
The QT300 only acquires when the host requests it.
In master mode, /DRDY goes high between bytes for the
period determined by Setup parameter MLS; this is a multiple
of 6µs.
While waiting for a new request the part is in a low power
mode.
When not communicating, all SPI lines float to allow multiple
chips to connect over the same SPI lines. A pullup or
pulldown resistor is required on SCK depending on the
selected clock phase, determined by Setups. A pullup
resistor is required on /DRDY. /REQ may require a pullup if
the host ever allows this line to float.
3 - SPI Port
3.1 SPI Specifications
The QT300 can operate in master or slave mode, and thus is
compatible with virtually all SPI-capable microcontrollers. The
SPI interface has the following specifications:
3.3 SPI Bus Sharing
All SPI float transfers making it possible to have several
QT300 devices (or other unrelated devices) share the SPI
control signals (Figure 3-1).
Max clock rate, Fckm 40KHz (master mode)
Max clock rate, Fcks 40KHz (slave mode)
Each part needs an individual /REQ line, but /DRDY, SCK
and SDO can be connected together.
Data length
Inter-byte delay
2 bytes (16 bits total)
≥8µs (master mode)*
≥12µs (slave mode)
Clock idle logic level
Clock edge
Data sequence
Low or High*
Data out on rising or falling edge*
High byte first, MSB first
3.4 SPI Slave Mode
Refer to Figure 7-1 and Table 7-1, page 8.
In SPI Slave mode, /DRDY is used to let the host know when
data is ready for collection in response to a request so that
the host can clock over the data.
*Determined by Setups
The host can clock the SPI at any rate up to and including
the maximum. The maximum clock rate of the part in Master
mode is determined in Setups via cloning.
SPI Slave mode uses 4 signals:
/REQ - Request Acquisition Input; Active low input-only.
When /REQ is pulled low, the QT300 wakes and starts an
acquire. The IC will transmit the resulting data only when
the acquire has finished.
3.2 Protocol Overview
The QT300 only transmits data on request, after an
acquisition burst. The host requests an acquire by setting the
/REQ line low for at least 30µs; the device then acquires.
When finished, the DRDY line is pulled low by the QT300 to
indicate it is ready to send data. (Figure 2-1). The transfer is
done as two bytes, with the highest byte transferred first.
/REQ should return high before the end of the burst. If
/REQ is still low at the end of the burst the part will go into
Setup mode. The minimum duration of /REQ is 30µs.
LQ
3
QT300 R1.01 21/09/03
