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QT301

型号：

QT301

描述：

电容ANALOG CONVERTER[ CAPACITANCE TO ANALOG CONVERTER ]

品牌：

QUANTUM[ QUANTUM RESEARCH GROUP ]

页数：

11 页

PDF大小：

264 K

下载PDF手册
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QT301  
CAPACITANCE TO  
A
NALOG  
CONVERTER  
ꢀ Capacitance to Analog Converter (CAC) IC  
ꢀ Patented charge-transfer conversion method  
ꢀ Sub-ranging Direct-to-Analog conversion  
ꢀ Rescaleable PWM: wide dynamic range  
ꢀ End-to-end calibration (gain, span) via CAL pins  
ꢀ 100 kHz PWM  
SYNC  
CAL_DN  
SNS1  
1
2
3
4
8
7
6
5
VDD  
CAL_UP  
PWM  
ꢀ Spread spectrum acquisition bursts for low noise  
ꢀ Sample on demand via Sync pin  
VSS  
SNS2  
ꢀ Only one external sample capacitor  
APPLICATIONS  
ꢀ Fluid level sensors  
ꢀ Moisture detection  
ꢀ Position sensing  
ꢀ Transducer driver  
ꢀ Material sensors  
ꢀ Proximity sensors  
The QT301 charge-transfer (QT) IC is a self-contained Capacitance-to-Analog-Converter (CAC) capable of detecting  
femotofarad level changes in capacitance. This part is designed primarily for stand-alone instrumentation applications.  
Primary applications include fluid level sensors, distance sensors, material detectors, transducer amplifiers for pressure and  
humidity sensing functions, and other uses requiring quantified capacitance data.  
Unlike other Quantum products, the QT301 does not process its acquired data. Its only output is raw, unprocessed data in  
filterable PWM form that can be translated into an analog voltage by a simple RC network. This allows the designer to treat  
the device as a CAC for measurement applications.  
The PWM range is set via two inputs that control the starting and ending point of the conversion range. For example, if the  
capacitance range of Cx is from 27pF to 38pF, the QT301 can be calibrated so that the PWM zero point occurs at 27pF, and  
the endpoint (255) occurs at 38pF. In this way, the PWM range is optimized for the zone of interest. These calibration points  
are stored in internal EEPROM and do not have to be reacquired after a power reset. This means that the resolution of the  
part can be compared easily to other methods that might otherwise require 12 or more bits of overall resolution.  
The device operates on demand via a sync input pin. The sync input can also be used to avoid external noise sources and  
cross-interference from adjacent QRG capacitive sensors. Unique among capacitance sensors, this device features  
spread-spectrum burst modulation, permitting extremely high noise rejection characteristics for very robust signals even in  
high EMI environments.  
The device requires only a single sampling capacitor (Cs) to acquire signals. The value of this capacitor controls the gain of  
the sensor, and it can be adjusted over 2½ decades of range from 1nF to 500nF. No external switches, opamps, or other  
components are required.  
AVAILABLE OPTIONS  
TA  
00C to +700C  
-400C to +850C  
SOIC  
-
QT301-IS  
8-PIN DIP  
QT301-D  
-
LQ  
Copyright © 2003 QRG Ltd  
QT301 R1.06 12/03  
Table 1-1 Pin Description  
Name Function  
SYNC  
1 - Overview  
The QT301 is a digital burst mode charge-transfer (QT)  
capacitance-to-analog converter (CAC). It has a PWM output  
designed for applications such as fluid level sensing and  
distance gauging; the PWM signal is eight bits in resolution.  
The IC features two calibration inputs for end-to-end span  
calibration. The output depends on load (Cx) and sampling  
capacitor (Cs) values.  
Pin  
1
Sync Input  
2
CAL_DN  
SNS1  
VSS  
Lower Calibration input  
Sense 1 line (to electrode)  
Negative supply (ground)  
Sense 2 line  
3
4
5
SNS2  
PWM  
6
PWM output  
1.1 Basic Operation  
7
CAL_UP  
VDD  
Upper Calibration input  
Positive supply  
The QT301 has internal EEPROM to store the two calibration  
points. The sensor acquires the signal from the electrode and  
calculates the PWM result using the two calibration points.  
The sensor can be calibrated via the two calibration inputs  
(see Section 4). The signal can be acquired either  
continuously or it can be synchronized on an external signal.  
The response time of the PWM depends largely on the  
acquisition burst spacing.  
8
2 - Signal Acquisition  
The QT301 has a power-up delay of 300ms. During this  
interval it does not acquire signals or generate a PWM result;  
it also ignores calibration inputs. This delay helps to prevent  
false calibrations due to signal noise on Vdd during  
startup.  
Figure 2-1 shows the basic QT301 acquisition timing  
parameters. Tbd is the burst duration, Tbs is the  
burst spacing from the start of one burst to the start  
of the next burst; when there is no Sync signal Tbs =  
Tbd+2.5ms.  
Figure 1-1 Basic Circuit Diagram  
3 to 5.5V  
0.1uF  
8
VDD  
R1  
1
2.1 Burst Properties  
SYNC  
Electrode  
The QT301 employs bursts of charge-transfer cycles  
to acquire its signal. Burst mode dramatically reduces  
RF emissions and lowers susceptibility to EMI.  
Upper Cal  
Rs  
7
2
6
3
5
CAL_UP  
CAL_DN  
PWM  
SNS1  
SNS2  
Lower Cal  
Cs  
The acquisition burst operates in a band between  
230kHz and 310kHz. The burst is spread-spectrum  
modulated within this band to suppress interference  
from external noise sources.  
Cx  
PWM Out  
VSS  
R3  
R2  
The QT switches and charge measurement hardware  
functions are all internal to the QT301. A 16-bit  
single-slope switched capacitor, analog to digital  
converter (ADC), includes both the required QT  
charge and transfer switches in a configuration that  
4
provides direct ADC conversion. The ADC is designed to  
dynamically optimize the QT burst length according to the  
rate of charge buildup on Cs, which in turn depends on the  
values of Cs, Cx, and VDD. VDD is used as the charge  
reference voltage.  
1.2 Basic Circuit  
Figure 1-1 shows a basic circuit diagram for the QT301. The  
pin layout of the QT301 is as explained in Table 1-1. In this  
particular circuit, C1 should be 100nF and R1, R2 and R3  
should all be 10K.  
R1 is only required if the synchronization feature is not used  
and can be connected to either VDD or VSS.  
Cs should be between 1nF and 500nF depending on the  
sensitivity required. Use either NPO or PPS capacitors for  
best results.  
Figure 2-1 Acquisition Burst: No Sync Pulse  
Rs is calculated with the following formula:  
166%103  
Rs <  
Cx  
where Cx is expressed in pF.  
Tbd  
Tbs  
LQ  
2
QT301 R1.06 12/03  
Figure 2-2 Acquisition Burst with Sync Signal  
2.2 CS / CX Dependency  
The signal value is a direct function of Cs and Cx, where Cs  
is the fixed sample capacitor, and Cx is the unknown  
capacitance. These two values influence device sensitivity,  
resolution and response time, making them very important  
parameters.  
Sync Signal  
Sensitivity and resolution are also a function of the size,  
shape, and composition of the electrode, the composition  
and thickness of any dielectric overlaying the electrode, the  
composition and aspect of the object being sensed, and the  
degree of mutual coupling between the electrode and the  
object being sensed.  
Acquisition  
Burst  
2.3 Burst Length  
The burst length (and hence the signal level) is described by  
the following formula:  
Figure 2-3 Acquisition Burst: Sync Lost  
k$CS  
BL =  
CX  
Where ‘k’ is a constant, typically 0.51 (this may vary slightly  
from device to device).  
Sync Signal  
Each doubling of Cs increases the signal level and  
differential sensitivity by a factor of two. Likewise, doubling  
Cx reduces the signal level and differential sensitivity by a  
factor of two (Figures 6-1, 6-2, page 8).  
Acquisition  
Burst  
The device has an internal Cx, Csns, which adds to the Cx in  
the formula. This capacitance is about 11pF.  
Because the QT301 has an 8-bit PWM output which spans  
two calibration endpoints, the PWM output value is  
expressed as:  
100ms  
Figure 2-4 Acquisition Burst: Sync Reacquired  
k$C  
k$C  
S
S
−
−
C
C
C
X2$(CX1−CX)  
X
X1  
PWM = 255 $  
= 255 $  
;
k$C  
k$C  
CX$(CX1−CX2)  
S
S
C
C
X1  
X2  
where:  
Cx1 is the capacitance at the lower cal point  
Cx2 is the capacitance at the upper cal point, and  
Sync Signal  
Cx is the measured capacitance between Cx1 and Cx2  
Particularly noteworthy is that Cs is not part of this equation;  
the PWM result is purely a function of the three Cx values.  
Cs only needs to be large enough to prevent granularity  
problems (i.e. coarseness or resolution).  
Acquisition  
Burst  
In most cases the result is a nearly-linear response between  
the endpoints. Only when the capacitance of the lower cal  
point becomes comparable to delta Cx does the result  
become substantially non-linear.  
For a linear response, make sure that the lower cal point  
capacitance is significantly larger than the delta capacitance  
between the endpoints. If the delta Cx amounts to 5pF, the  
response will be accurate to 2.4% of full scale if the lower cal  
point is 50pF. But if the lower cal point is only 20pF and the  
delta Cx is 10pF, the error rises to 10% at points. The largest  
errors occur near the middle of the Cx span.  
Figure 2-5 Sync Overclocked  
Sync Signal  
An example of the error can be seen in Figure 2-6.  
Non-linear errors can be linearized using polynomials or a  
piece-wise linear correction method in a microcontroller. A  
spreadsheet with the calculations for this equation and the  
error terms can be obtained on request.  
Acquisition  
Burst  
LQ  
3
QT301 R1.06 12/03  
The 2.5ms is the minimum gap between bursts is to  
allow Cs to properly discharge; Sync is not possible  
during this interval nor is it possible to re-sync during a  
burst.  
PWM, 0..255  
% Error  
Figure 2-6 PWM vs Cx, Over Range 100pF...110pF  
300  
250  
200  
150  
100  
50  
3%  
2%  
2%  
1%  
1%  
0%  
3 PWM Output  
The PWM output is a 100KHz 7% square wave. It  
can be filtered using a simple RC circuit, or fed directly  
into a timer circuit that can measure its duty cycle with  
sufficient resolution. If an RC is used, the resistor  
should be at least 10K ohms to reduce pin loading  
errors.  
The PWM duty cycle is defined as follows:  
0
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
TPWM_high  
Cx, pF  
DPWM  
=
TPWM_Period  
If an RC circuit is used, it is often best to put a voltage  
follower circuit on the output of the filter to buffer the output  
voltage (Figure 2-7).  
2.4 Sync Input  
Bursts can be synchronized to external noise sources such  
as powerline fields to suppress their interferening effects. A  
typical sync circuit is shown in Figure 2-7. By synchronizing  
with a noise source, the noise itself becomes highly  
correlated with the acquired data, and AC alias components  
effectively disappear from the signal. Synchronization works  
best on low frequency, highly repeatable signals, such as  
mains frequency (50/60 Hz) sources.  
Note that the PWM output is not 100% linear with changes in  
Cx capacitance from end to end. The transfer function for the  
QT301 vs Cx is described in Section 2.3.  
During CAL, the PWM output value is locked in place with  
the value just prior to when the CAL process was triggered.  
Only after CAL is complete is the PWM updated with the new  
results.  
Figure 2-2 shows the effect of sync pulses on the burst rate.  
A sync signal triggers a burst on the rising edge.  
4 Calibration  
There is a Sync timeout of 100ms as shown in Figure 2-3. If  
Sync pulses cease for >100ms, the Sync signal will be  
treated as being lost and the device will start to acquire at its  
own default rate again. When using the Sync feature it is  
important that the Sync pulses are spaced less than 100ms  
apart.  
The QT301 should be calibrated end to end to have an  
effective, properly scaled PWM output. The calibration is  
done on a ‘learn by example’ basis. Each end is calibrated  
separately while the appropriate end-point signal level is  
applied. After the Cal process, the PWM signal will scale  
itself to reflect these endpoints with the best resolution  
possible.  
Figure 2-2 shows the acquisition burst in relation to Sync  
pulses. If no rising edge is detected for 100ms, the QT301  
will revert to the default timing shown in Figure 2-1. Figure  
2-4 shows the sudden start of a train of Sync pulses and the  
effect on the acquisition bursts.  
4.1 Calibration Pins  
The CAL_DN pin should be used to calibrate the signal when  
the electrode is at its lowest level of Cx, for example with a  
level probe when the fluid is at a minimum.  
Should the sync signal overclock the acquisition bursts  
(Figure 2-5), the device will trigger on the next rising edge  
after a delay of Tbd+2.5ms.  
Figure 2-7 Line Sync and PWM Output Filter  
+3 to 5.5V  
0.1uf  
IN4148  
8
VDD  
1M  
1
Line  
Frequency  
SYNC  
Electrode  
20pF  
Rs  
7
2
6
3
5
CAL_UP  
CAL_DN  
PWM  
Upper Cx Cal  
SNS1  
SNS2  
Cs  
Lower Cx Cal  
Cx  
100K  
Analog  
Output  
VSS  
0.1uF  
10K  
10K  
4
LQ  
4
QT301 R1.06 12/03  
The CAL_UP pin should be used to calibrate the signal when  
the electrode is at its maximum useable level of Cx, for  
example with a level probe when the fluid is at the top.  
Figure 4-1 Calibration Process  
User sets CAL_DN  
high  
User sets CAL_UP  
high  
It does not matter whether CAL_DN or CAL_UP are applied  
first. After calibration is complete, either CAL_DN or CAL_UP  
can be asserted again to obtain a fresh calibration for the  
corresponding end point, without affecting the other end  
point.  
2.5ms Delay  
2.5ms Delay  
CAL_DN forced high  
by QT301  
CAL_UP forced high  
by QT301  
4.2 Calibration Process  
The CAL pins are inputs used to trigger a CAL process on  
the upper (max Cx) or lower (min Cx) capacitance endpoints.  
These pins must be pulled low via a pulldown resistor on  
each, to prevent damage.  
Calibration starts  
Calibration starts  
User floats CAL_DN  
User floats CAL_UP  
To calibrate either endpoint, assert either CAL pin high using  
an open-source output from a mosfet or microcontroller, or, a  
collector from a PNP transistor whose emitter is connected to  
Vdd. Hold this level high for 2.5ms minimum (preferably, 3ms  
to be safe). Then release the pin to try to float down.  
NO  
NO  
QT301 Cal done?  
QT301 Cal done?  
The QT301 will continue to hold the pin high starting at the  
2.5ms point. There should be no contention problem with an  
external voltage plus the QT301 both holding this pin high.  
YES  
YES  
QT301 floats  
CAL_DN pin again  
QT301 floats  
CAL_UP pin again  
When the QT301 is done calibrating, it will release the CAL  
pin in question to float low. A host controller can use this  
feature to check when the calibration process has completed.  
If the power supply is shared with another electronic system,  
make sure the supply is free of spikes, sags, and surges.  
The supply is best locally regulated using a conventional  
78L05 type regulator, or almost any 3-terminal LDO device  
from 3V to 5V.  
Calibration takes 15 acquisition burst samples to complete.  
The new calibration data is stored in internal EEPROM when  
the host releases the CAL pin to float low again; the chip also  
begins to operate normally again at this time.  
Figure 4-1 shows the control flows for calibration.  
For proper operation, a 0.1µF or greater bypass capacitor  
must be used between VDD and VSS; the bypass cap should  
be placed very close to the device pins. The PCB should if  
possible include a copper pour under and around the IC, but  
not extensively under the SNS pins or lines.  
The capacitive signal on the electrode should be as stable  
and noise-free as possible during the CAL intervals to ensure  
accurate calibration points.  
During a CAL cycle, the PWM output functions normally  
using the last known good calibration data and signal value.  
The PWM output will change again only when the CAL  
process is complete.  
5.3 ESD Protection  
In cases where the electrode is placed behind a dielectric  
panel the IC will be protected from direct static discharge.  
However, even with a panel transients can still flow into the  
electrodes via induction, or in extreme cases via dielectric  
breakdown. Porous materials may allow a spark to tunnel  
right through the material. Testing is required to reveal any  
problems.  
Note: The CAL pins should never be driven low. Driving  
either of the CAL pins low will short circuit the chip.  
5 - CIRCUIT GUIDELINES  
5.1 Sample Capacitor  
The device has diode protection on its SNS pins that absorb  
most induced discharges (up to 20mA), and protect the  
device. The usefulness of the internal clamping will depend  
on the dielectric properties, panel thickness, and rise time of  
the ESD transients. In extreme cases, ESD dissipation can  
be aided further by adding a resistor in series with the  
electrode.  
The charge sampler capacitor (Cs) can be virtually any  
plastic film or low to medium-K ceramic capacitor. The  
acceptable Cs range is from 1nF to 500nF depending on the  
sensitivity required; larger values of Cs demand higher  
stability to ensure reliable sensing. Acceptable capacitor  
types include plastic film (especially PPS film) and NP0/C0G  
ceramic. X7R ceramic can also be used but this type is less  
stable over temperature.  
The charge pulse can be a minimum of 1µs and therefore the  
circuit can tolerate values of series-R up to 18k in cases  
where electrode Cx load is below 10pF. Extra diode  
protection may be used at the electrodes but this often leads  
to additional RFI problems as the diodes will rectify RF  
signals into DC; this will disturb the sensing signals.  
Series-R’s should be low enough to permit at least six RC  
time-constants (i.e. a net RC timeconstant of 1/6 µs) to occur  
during the charge pulse, where R is the added series-R and  
5.2 Power supply, PCB Layout  
The QT301 makes use of the power supply as a reference  
voltage. The acquired signal will shift slightly with changes in  
VDD; fluctuations in VDD often happen when additional loads  
are switched on or off such as LEDs etc.  
Care should be taken when designing the power supply, as  
any change in VDD will affect the PWM level.  
LQ  
5
QT301 R1.06 12/03  
C is the load Cx. If the series-R or Cx is too large, sensitivity  
will be reduced.  
5. Route sense traces away from other traces or wires that  
are connected to other circuits.  
Directly placing semiconductor transient protection devices  
or MOV's on the sense leads is not advised; these devices  
have extremely large amounts of non-linear parasitic C,  
which will swamp the capacitance of the electrode and may  
deliver spurious sensing results.  
6. Sense electrodes should be kept away from other  
circuits and grounds which are not directly connected to  
the sensor’s own circuit ground; other grounds will  
appear to float at high frequencies and couple RF  
currents into the sense lines.  
7. Keep the Cs sampling capacitors and all series-R  
components close to the IC.  
5.4 RF Susceptibility  
PCB layout, grounding, and the structure of the input circuitry  
have a great bearing on the success of a design that can  
withstand strong RF interference. The circuit is remarkably  
immune to RFI provided that certain design rules are  
adhered to:  
8. Use a 0.1µF minimum, ceramic bypass cap very close to  
the VSS/VDD supply pins.  
9. Use series-R’s in the sense line of as large a value as  
the circuit can tolerate without degrading sensitivity  
appreciably (see Section 1.2).  
1. Use SMT components to minimize lead lengths.  
2. Connect electrodes to SNS1, not SNS2.  
10. Bypass input power to chassis ground and again at  
circuit ground to reduce line-injected noise effects.  
Ferrites over the power wiring may be required to  
attenuate line injected noise.  
3. Use a ground plane under and around the circuit and  
along the sense lines, that is as unbroken as possible  
except for relief under and beside the sense lines to  
reduce total Cx. Relieved rear ground planes along the  
SNS lines should be ‘mended’ by bridging over them at  
1cm intervals with 0.5mm ‘rungs’ like a ladder.  
Achieving RF immunity requires diligence and a good  
working knowledge of grounding, shielding, and layout  
techniques. Very few projects involving these devices will fail  
EMC tests once properly constructed.  
4. Ground planes and traces should be connected only to a  
common point near the VSS pin of the IC.  
LQ  
6
QT301 R1.06 12/03  
6 Electrical specifications  
6.1 ABSOLUTE MAXIMUM SPECIFICATIONS  
Operating temp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . as designated by suffix  
Storage temp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65OC to +125OC  
Vdd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +6V  
Max continuous pin current, any control or drive pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mA  
Short circuit duration to ground, any pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . infinite  
Short circuit duration to VDD, any pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . infinite  
Voltage forced onto any pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to (VDD + 0.5) Volts  
6.2 RECOMMENDED OPERATING CONDITIONS  
Vdd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3 to 5V  
Short-term supply ripple+noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mV  
Long-term supply stability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mV  
Cs value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 to 500nF  
Cx value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 500pF  
6.3 GENERAL SPECIFICATIONS  
Parameter  
Description  
EEPROM write cycles  
Power up time  
Min  
Typ  
Max  
Units  
Notes  
E
WC  
100,000  
TPU  
300  
11  
ms  
pF  
Csns  
K
Sensor pin internal capacitance  
Burst length coefficient  
0.51  
6.4 AC SPECIFICATIONS  
VDD = 3.3 Volts, Cs = 100nF, Cx = 5pF, Ta = recommended range, unless otherwise noted  
Parameter  
Description  
Charge/transfer time  
Burst center frequency  
Burst frequency modulation  
Burst length  
Min  
Typ  
1.25  
265  
±±  
Max  
Units  
µs  
Notes  
TPC  
1
1.5  
Fc  
kHz  
%
FD  
+/-10% over voltage and  
temperature range  
T
BD  
BS  
16  
ms  
T
Burst spacing  
T
BD + 2.5  
T
BD + 100  
ms  
F
PWM  
CPD  
CD  
PWM frequency  
100  
kHz  
ms  
T
Calibration pulse duration  
Calibration duration  
2.5  
T
15 x TBS  
ms  
6.5 DC SPECIFICATIONS  
VDD = 3.3 Volts, Cs = 100nF, Cx = 5pF, Ta = recommended range, unless otherwise noted  
Parameter  
Description  
Supply current  
Min  
Typ  
5
Max  
Units  
Notes  
IDD  
mA  
mA  
V
@5V  
I
DD  
Supply current  
2.9  
@3.3V  
V
IL  
IH  
OL  
OH  
Input low voltage  
Input high voltage  
Low output voltage  
High output voltage  
Acquisition resolution  
0.3 VDD  
0.5  
VDD = 3 to 5.5V  
VDD = 3 to 5.5V  
V
0.6 VDD  
VDD-0.±  
V
V
V
I
I
OL = 6mA  
V
V
OH = -1.5mA  
A
R
11  
8
bits  
S
Resolution per bit  
fF  
LQ  
7
QT301 R1.06 12/03  
10000  
9000  
8000  
7000  
6000  
5000  
4000  
3000  
2000  
1000  
0
1000  
900  
800  
700  
600  
500  
400  
300  
200  
100  
0
22nF  
10nF  
4.7nF  
200nF  
120nF  
80nF  
40nF  
0
10  
20  
30  
40  
50  
0
10  
20  
30  
40  
50  
Cx Load  
Cx Load  
Figure 6-2 Typical Burst Length versus Cx & Cs;  
VDD= 5.0 Volts  
Figure 6-1 Typical Burst Length versus Cx & Cs;  
VDD = 5.0 Volts  
5.0  
4.5  
4.0  
3.5  
3.0  
2.5  
2.0  
2.5  
3.0  
3.5  
4.0  
4.5  
5.0  
5.5  
Power supply, Volts  
Figure 6-3 Power Consumption versus VDD  
LQ  
8
QT301 R1.06 12/03  
Figure 6-4 Typical Signal Deviation versus Temperature  
VDD = 5.0 Volts, Cx = 10pF  
6000  
5000  
4000  
3000  
2000  
1000  
0
200nF PPS  
100nF PPS  
4.7nF PPS  
-10  
0
10  
20  
30  
40  
50  
60  
70  
80  
Temperature, °C  
Figure 6-5 Typical Signal Deviation vs. Temperature  
Vdd = 5.0 Volts, Cx = 10pF, Cs = 5nF - 200nF PPS Film  
5.00%  
4.00%  
3.00%  
2.00%  
1.00%  
0.00%  
-1.00%  
-2.00%  
-3.00%  
-4.00%  
-5.00%  
-10 -5  
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85  
Temperature, C  
LQ  
9
QT301 R1.06 12/03  
M
A
F
S1  
S
a
A
r
L2  
Pin 1  
x
m
L1  
L
Q
Package type: 8-pin Dual-In-Line  
Millimeters  
Inches  
Max  
Symbol  
Min  
Max  
Notes  
Min  
Notes  
a
A
M
m
Q
L
L1  
L2  
F
r
S
S1  
x
6.1  
±.62  
9.02  
±.62  
0.69  
0.356  
1.14  
0.203  
2.54  
0.38  
2.92  
-
±.11  
8.26  
10.16  
-
0.94  
0.559  
1.±8  
0.305  
-
0.24  
0.3  
0.355  
0.3  
0.02±  
0.014  
0.045  
0.008  
0.1  
0.015  
0.115  
-
0.28  
0.325  
0.4  
Typical  
-
Typical  
0.03±  
0.022  
0.0±  
0.012  
-
BSC  
BSC  
-
-
3.81  
5.33  
10.9  
0.15  
0.21  
0.43  
M
M
a
A
H
φ
e
h
Pin 1  
E
F
L
Package type: 8-pin Wide SOIC  
Millimeters  
Inches  
Symbol  
Min  
5.21  
Max  
Notes  
Min  
0.205  
0.3  
Max  
0.213  
0.33  
Notes  
a
A
M
F
L
5.41  
8.38  
5.38  
±.62  
5.16  
0.203  
0.05  
0.212  
1.2±  
BSC  
BSC  
0.305  
0.102  
1.±8  
0.508  
0.33  
2.03  
0.012  
0.004  
0.0±  
0.02  
0.013  
0.08  
h
H
e
0.1±8  
0.508  
o
0.254  
0.889  
o
0.00±  
0.02  
o
0.01  
0.035  
o
E
φ
0
8
0
8
LQ  
10  
QT301 R1.06 12/03  
lQ  
Copyright © 2003 QRG Ltd. All rights reserved.  
Patented and patents pending  
Corporate Headquarters  
1 Mitchell Point  
Ensign Way, Hamble SO31 4RF  
Great Britain  
Tel: +44 (0)23 8056 5600 Fax: +44 (0)23 8045 3939  
admin@qprox.com  
www.qprox.com  
North America  
651 Holiday Drive Bldg. 5 / 300  
Pittsburgh, PA 15220 USA  
Tel: 412-391-7367 Fax: 412-291-1015  
The specifications set out in this document are subject to change without notice. All products sold and services supplied by QRG are subject  
to our Terms and Conditions of sale and supply of services which are available online at www.qprox.com and are supplied with every order  
acknowledgement. QProx, QTouch, QMatrix, QLevel, and QSlide are trademarks of QRG. QRG products are not suitable for medical  
(including life-saving equipment), safety or mission critical applications or other similar purposes. Except as expressly set out in QRG's  
Terms and Conditions, no licenses to patents or other intellectual property of QRG (express or implied) are granted by QRG in connection  
with the sale of QRG products or provision of QRG services. QRG will not be liable for customer product design and customers are entirely  
responsible for their products and applications which incorporate QRG's products.  
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