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NX2601CMTR

型号:

NX2601CMTR

描述:

与NMOS LDO控制器与5V偏置稳压器双同步PWM控制器[ DUAL SYNCHRONOUS PWM CONTROLLER WITH NMOS LDO CONTROLLER & 5V BIAS REGULATOR ]

品牌:

MICROSEMI[ Microsemi ]

页数:

25 页

PDF大小:

1010 K

Evaluation board available.  
NX2601  
DUAL SYNCHRONOUS PWM CONTROLLER WITH NMOS LDO  
CONTROLLER & 5V BIAS REGULATOR  
PRELIMINARY DATA SHEET  
Pb Free Product  
FEATURES  
DESCRIPTION  
n Two channel PWM with out of phase operation  
The NX2601 controller IC is a triple controller with a dual  
channel synchronous Buck controller IC and an LDO con-  
troller designed for multiple converters such as PCIe  
graphic card applications .The two synchronous PWM  
controllers are 180 degree out of phase which reduces  
the input ripple current, allowing to reduce the # of input  
capacitors.Another main feature of the part is that it can  
operate from single 12V supply while maintaining a regu-  
lated 5V supply for the biasing and the internal drivers.  
Other features of NX2601 are: programmable frequency  
from 200kHz to 1MHz, independent digital soft start and  
enable pins for each controller which allows for different  
power sequencing, Adaptive driver provides optimized ef-  
ficiency while maintain sufficient deadband, Vcc  
undervoltage lock out and current limiting using an Rds-  
on of the external MOSFET with HICCUP feature.  
n Individual digital soft start for two PWM output  
and LDO controller  
n
n
Bus voltage operation from 2V to 25V  
Hiccup Current limit by sensing Rdson of MOSFET  
n Adjustable frequency up to 1Mhz per channel  
n Adaptive deadband time  
n Three enable pin available allows for independent  
power sequencing  
n MLPQ-32L package offers small size  
n Pb-free and RoHS compliant  
APPLICATIONS  
n
n
n
PCI Graphic Card on board converters  
Vddq Supply in mother board applications  
On board DC to DC such as  
12V to 3.3V, 2.5V or 1.8V  
n
FPGA and Set Top Box Applications  
TYPICAL APPLICATION  
10  
R11  
+5V  
C15  
1uF  
R12  
5k  
C17  
68uF  
5
23 C1  
1uF  
11  
R13  
1.65k  
VCC  
+5V  
REG FB  
PVCC1  
VIN1  
L1 1uH  
47pF  
C16  
VIN1  
+12V  
D1  
24  
C3  
100uF  
C2  
180uF  
BST1  
10  
REG OUT  
AUXVCC  
LDO OUT  
2N3904  
M5  
C4  
5k  
0.1uF  
M1  
9
8
VIN2  
+3.3V  
25  
26  
C24 1uF  
R15  
HDRV1  
L2 0.78uH  
C20  
VOUT1  
C18  
150uF  
SW1  
+1.2V@15A  
0
R1 10.5k  
150pF  
27  
C7  
VOUT3  
+2.5V/2A  
7
OCP1  
LDO FB  
ENLDO  
2 x (2R5TPD680M6,680uF,6mohm)  
R2  
1.5k  
R16  
5k  
R17  
2.35k  
R3  
10.4k  
22  
21  
C19  
150uF  
LDRV1  
R18  
1.5k  
M2  
C6  
2.7nF  
PGND1  
Fb1  
29  
28  
3
R5 5k  
C22  
OFF R25  
10k  
8.2nF C5  
220pF  
+5V  
R4  
20.8k  
R19  
1.25k  
2N3904  
Comp1  
PVCC2  
C25  
1uF  
ON  
R26  
10k  
18 C8  
1uF  
R20  
6.8k  
D2  
1
ENSW1  
VIN1  
17  
C9  
180uF  
BST2  
R21  
C11  
0.1uF  
1.25k  
M3  
L4 1.5uH  
16  
15  
HDRV2  
OFF R27  
10k  
2N3904  
VOUT2  
2
6
ON  
ENSW2  
RT  
R28  
10k  
SW2  
+1.8V/10A  
R6  
14  
6k  
C14  
OCP2  
3 x (4TPE150M,150uF,18mohm)  
R7  
820  
R8  
8.7k  
M4  
19  
LDRV2  
20  
12  
C13  
PGND2  
Fb2  
R24  
C21  
62k  
3.3nF  
30  
31  
VP  
VREF  
C12  
R10  
R9  
6.97k  
13  
1nF  
Comp2  
GND  
5k  
10nF  
4
220pF  
C23  
Figure1 - Typical application of 2601  
PATENT PENDING  
ORDERING INFORMATION  
Device  
NX2601CMTR  
Temperature  
0 to 70oC  
Package  
MLPQ-32L  
Frequency  
Pb-Free  
Yes  
200kHz to 1MHz  
Rev. 2.3  
12/01/06  
1
NX2601  
ABSOLUTE MAXIMUM RATINGS  
Vcc,PVcc & BST to SW voltage ......................... 6.5V  
BST Voltage ...................................................... 35V  
SW ................................................................... -5V(Note1) to 35V  
AUXVCC .......................................................... 35V  
All other pins .................................................... GND to Vcc+0.3V  
Storage Temperature Range ............................... -65oC to 150oC  
Operating Junction Temperature Range ............... -40oC to 125oC  
CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to  
the device. This is a stress only rating and operation of the device at these or any other conditions above those  
indicated in the operational sections of this specification is not implied.  
PACKAGE INFORMATION  
32-LEAD 5x5 PLASTIC MLPQ  
31 30 29 28 27  
25  
26  
32  
BST1  
ENSW1  
ENSW2  
ENLDO  
1
2
3
4
5
6
7
8
24  
23  
22  
PVCC1  
LDRV1  
qJA » 35oC / W  
GND  
VCC  
21 PGnd1  
NX2601  
PGnd2  
LDRV2  
20  
19  
RT  
LDO FB  
LDO OUT  
18 PVCC2  
17 BST2  
9
10  
12 13 14 15 16  
11  
ELECTRICAL SPECIFICATIONS  
Unless otherwise specified, these specifications apply over Vcc = 5V, VBST-VSW=5V, ENSW1=HIGH, ENSW2=HIGH,  
ENLDO=HIGH, and TA = 0 to 70oC. Typical values refer to TA = 25oC. Low duty cycle pulse testing is used which  
keeps junction and case temperatures equal to the ambient temperature.  
PARAMETER  
Reference Voltage  
FB Voltage  
SYM  
TEST CONDITION  
MIN  
TYP  
MAX  
UNITS  
VREF  
4.5 < Vcc < 5.5  
0.800  
0.4  
V
FB Voltage Line Regulation  
Vcc Supply Voltage  
Vcc Voltage Range  
Vcc Static Supply Current  
Vcc Dynamic Supply  
Current  
%
VCC  
5.5  
5.5  
5.0  
2.0  
8
4.5  
V
ICC_STA  
Outputs not switching  
Freq=600kHz,  
mA  
mA  
ICC_DYN  
CLOAD = 3300pF  
4.  
VBST  
VBST Voltage Range  
VBST Static Supply Current  
VBST Dynamic Supply  
Current  
5.0  
2.0  
4.5  
V
IBST_STA  
Outputs not switching  
Freq = 600KHz,  
mA  
mA  
IBST_DYN  
TBD  
CLOAD = 3300pF  
Rev. 2.3  
12/01/06  
2
NX2601  
PARAMETER  
SYM  
TEST CONDITION  
MIN  
TYP  
MAX  
UNITS  
Under Voltage Lockout  
UVLO Threshold - Vcc  
UVLO Hysteresis - Vcc  
UVLO Threshold - VAUXVcc  
UVLO Hysteresis - VAUXVcc  
Error Amplifiers  
VCC_UVLO  
VCC__HYST  
VAUX_UVLO  
VAUX_HYST  
Supply Ramping Up  
Supply Ramping Down  
Supply Ramping Up  
Supply Ramping Down  
4
0.2  
7
V
V
V
V
0.7  
Open Loop Gain  
65  
0.3  
0
dB  
uA  
Input Bias Current  
Input Offset Voltage  
Oscillator  
mV  
Frequency  
FS  
VRAMP  
TSS  
Rt=30k,measured at the  
output drive  
600  
1
KHz  
V
Ramp Amplitude  
EN & SS  
Soft Start Time  
Fs=600KHz  
3.41  
1.25  
100  
mS  
V
Enable Threshold Voltage  
Enable Hysterises  
LDO Controller  
Enable ramp up  
LDOOUT=LDOFB  
mV  
LDO FB Voltage  
V
mA  
V
0.8  
0
FB Pin Bias Current  
LDO_out Output Voltage High  
-0.2  
22  
AUXVCC=24V,LDO FB=0.7V  
IO_SOURCE=1.4mA  
23.5  
AUXVCC=24V,LDO FB=0.9V  
IO_SINK=1.4mA  
V
LDO_out Output Voltage Low  
0.2  
GBNT(Note2)  
dB  
Open Loop Gain  
5V AUX REG  
50  
V
mA  
V
REG FB Voltage  
FB Pin Bias Current  
REG_out Output Voltage  
High  
1.25  
0
REGOUT=REGFB  
-0.2  
22  
AUXVCC=24V,REG FB=1.1V  
IO_SOURCE=1.4mA  
23.5  
AUXVCC=24V,REG FB=1.4V  
IO_SINK=1.4mA  
V
REG_out Output Voltage  
Low  
0.2  
dB  
GBNT(Note2)  
Open Loop Gain  
High Side driver  
(CL=3300pF)  
50  
ohm  
Output Impedance, Sourcing Rsource  
Current  
_
H
0.85  
Output Impedance , Sinking Rsink  
_
H
ohm  
ns  
Current  
0.65  
25  
10% to 90%  
Rise Time  
THDRV_RISE  
THDRV_FALL  
TDEAD_LH  
90% to 10%  
ns  
Fall Time  
20  
LDRV going Low to HDRV  
going High, 10% to 10%  
Deadband Time  
ns  
30  
Rev. 2.3  
12/01/06  
3
NX2601  
PARAMETER  
Low Side driver  
(CL=3300pF)  
SYM  
TEST CONDITION  
MIN  
TYP  
MAX  
UNITS  
Output Impedance, Sourcing Rsource  
Current  
_
L
0.85  
ohm  
Output Impedance , Sinking Rsink  
_
L
Current  
0.5  
25  
20  
20  
ohm  
ns  
10% to 90%  
Rise Time  
TLDRV_RISE  
TLDRV_FALL  
TDEAD_HL  
90% to 10%  
Fall Time  
ns  
SW going Low to LDRV going  
High, 10% to 10%  
Deadband Time  
ns  
Note 1: 500ns transient. This pin can withstand -2V DC.  
Note 2: This parameter is guaranteed by design but not tested in production(GBNT).  
Rev. 2.3  
12/01/06  
4
NX2601  
PIN DESCRIPTIONS  
PIN #  
PIN SYMBOL  
PIN DESCRIPTION  
A resistor divider is connected from the respective switcher BUS voltages to these  
pins that holds off the controllers soft start until this threshold is reached. An  
external low cost MOSFET or NPN transisitor can be connected to this pin for  
external enable control.  
1
2
ENSW1  
ENSW2  
A resistor divider is connected from the LDO bus voltage to this pin that holds off  
the LDO soft start until this threshold is reached. An external low cost MOSFET  
can be connected to this pin for external enable control.  
3
4
5
ENLDO  
GND  
Analog ground.  
IC's supply voltage. This pin biases the internal logic circuits. A high freq 1uF  
ceramic capacitor is placed as close as possible to and connected to this pin and  
ground pin.  
VCC  
Oscillator's frequency can be set by using an external resistor from this pin to  
GND. This frequency is the master clock frequency which is internally divided by  
two to set each controller frequency.  
6
7
8
9
RT  
LDO controller feedback input. If the LDOFB pin is pulled below 0.5*Vref, an  
internal comparator after certain delay and pulls down LDOOUT pin and initiates  
the HICCUP circuitry. During the startup this latch is not activated, allowing the  
LDOFB pin to come up and follow the Soft started Vref voltage.  
LDO FB  
LDO OUT  
AUXVCC  
LDO controller output. This pin is controlling the gate of an external NCH  
MOSFET. The maximum rating of this pin is 16V.  
This pin is the supply voltage for the LDO controller as well as the 5V regulator  
controller that regulates the voltage at Vcc derived from the BUS voltage. The  
maximum voltage applied to this pin is 30V.  
The output of the 5V regulator controller that drives a low current low cost external  
BIPOLAR transistor or an external MOSFET to regulate the voltage at Vcc pin  
derived from BUS voltage. This eliminates an otherwise external regulator needed  
in applications where 5V is not available.  
REGOUT  
RER  
10  
11  
REGFB  
Feedback pin of the 5V regulator controller.A resistor divider is connected from  
the output of the 5V regulator to this pin to complete the loop.  
12  
29  
13  
28  
FB2  
FB1  
This pin is the error amplifiers inverting input. These pins are connected via  
resistor dividers to the output of the switching regulators to set the output DC  
voltage.  
COMP2  
COMP1  
These pins are the outputs of error amplifiers and are used to compensate the  
respective voltage control feedback loops.  
Rev. 2.3  
12/01/06  
5
NX2601  
PIN DESCRIPTIONS  
PIN #  
PIN SYMBOL  
PIN DESCRIPTION  
This pin is connected to the drain of the external low side MOSFET and is the  
input of the over current protection(OCP) comparator.An internal current source  
which equals 1.25V divided by Rt resistor is flown to the external resistor which  
sets the OCP voltage across the Rdson of the low side MOSFET. Current limit  
point is this voltage divided by the Rds-on. Once this threshold is reached the  
Hdrv and Ldrv pins are switched low and an internal hiccup circuit is set that  
recycles the soft start circuit after 2048 switching cycles.  
14  
OCP2  
27  
OCP1  
ThesepinsareconnectedtosourceofhighsideFETsandprovidereturnpathfor  
thehighsidedrivers. Theyarealsousedtoholdthelowsidedriverslowuntilthis  
pinisbroughtlowbytheactionofhighsideturningoff.LDRVscanonlygohighif  
SW isbelow1Vthreshold.  
15  
26  
SW2  
SW1  
Highsidegatedriveroutputs.  
16  
25  
HDRV2  
HDRV1  
ThispinsuppliesvoltagetohighsideFETdriver.Ahighfreq1uFceramiccapaci-  
torisplacedascloseaspossibletoandconnectedtothesepinsandrespected  
SW pins.  
17  
24  
18  
23  
BST2  
BST1  
Supplyvoltageforthelowsidefetdrivers.Ahighfrequency1uFceramiccapmust  
beconnectedfromthispintothePGND1andPGND2pinascloseaspossibleto  
thepins.  
PVCC2  
PVCC1  
Lowsidegatedriveroutputs.  
19  
22  
LDRV2  
LDRV1  
Powergroundpinforlowsidedrivers.  
20  
21  
PGND2  
PGND1  
Thispinisthefirsterroramplifiernon-invertinginput.Thispinshouldbecon-  
nectedeithertoanexternalreferencevoltage(trackingapplication)ortothe  
internalreferencevoltageprovidedbythisdevice.  
30  
VP  
Referencevoltageavailable.A100pFcapacitorcanbeconnectedfromthispinto  
GND.ThispinisheldlowuntilinternalVccUVLOandtheENSW1pinaregood,  
allowingittosoftstart.  
31  
32  
VREF  
NC  
Rev. 2.3  
12/01/06  
6
NX2601  
BLOCK DIAGRAM  
AUXVCC  
Bias  
REGFB  
9.6/9.2  
4/3.8  
UVLO  
UVLO  
POR_LDO  
REGOUT  
1.25V  
Bias  
Generator  
VCC  
Vref  
POR_SW  
0.8V  
BST1  
ENSW1  
DRVH1  
SW1  
1.25/1.15  
two phase  
OSC  
set1  
RT  
VP  
Control  
Logic  
Digital  
start Up  
ramp1  
PVCC1  
POR_SW  
S
R
Q
DRVL1  
PGND1  
FB1  
COMP1  
OCP1  
Channel 1 PWM Controller  
OCP  
comparator  
BST2  
ENSW2  
FB2  
DrvH2  
SW2  
Channel 2 PWM controller (exclude oscillator)  
PVCC2  
DrvL2  
COMP2  
PGND2  
OCP2  
ENLDO  
GND  
digital  
start up  
LDO  
control  
logic  
1.25/1.15  
LDOOUT  
FBLDO  
POR_LDO  
0.4  
Rev. 2.3  
12/01/06  
7
NX2601  
10  
R19  
+5V  
C10  
1uF  
R16  
5k  
C17  
68uF  
5
23 C41  
1uF  
11  
R15  
1.65k  
VCC  
+5V  
C7  
REG FB  
PVCC1  
VIN1  
L2 1uH  
47pF  
VIN1  
+12V  
D1  
C8  
33uF  
R13  
5k  
24  
C24  
1uF  
C23  
180uF  
C21  
39uF  
BST1  
10  
REG OUT  
AUXVCC  
LDO OUT  
Q2  
C11  
0.1uF  
9
8
VIN3  
+3.3V  
25  
26  
HDRV1  
Q4  
Q5  
L1 0.78uH  
C5  
M5  
VOUT1  
R10  
150pF  
C3  
150uF  
SW1  
+1.2V@15A  
0
R22 10.5k  
27  
22  
C13,C14  
680uF,6mohm  
R23  
20k  
VOUT3  
+2.5V/2A  
7
OCP1  
LDO FB  
ENLDO  
R26  
1.5k  
R11  
5k  
R6  
C4  
150uF  
R27  
10.4k  
C12  
470pF  
LDRV1  
2.35k  
21  
29  
28  
C19  
2.7nF  
PGND1  
Fb1  
R7  
3
8.2nF  
5k  
R24  
C18  
R25  
20.8k  
R5  
1.5k  
Comp1  
1.25k  
C17  
220pF  
18 C42  
1uF  
R8  
+5V  
PVCC2  
1
2
L4 1uH  
ENSW1  
ENSW2  
VIN1  
VIN2  
+5V  
D2  
6.8k  
R4  
1.25k  
17  
C38  
1uF  
C36  
180uF  
C33  
39uF  
BST2  
C31  
0.1uF  
16  
15  
R9  
HDRV2  
VIN2  
L3 1.5uH  
Q6  
2.7k  
VOUT2  
R3  
SW2  
1.25k  
+1.8V@10A  
R32  
14  
3k  
C26,27,28  
150uF,18mohm  
R34  
20k  
OCP2  
R28  
330  
6
RT  
VP  
R29  
3.5k  
19  
C34  
470pF  
LDRV2  
R2 62k  
Q7  
C37  
10nF  
20  
12  
C25  
8.2nF  
30  
PGND2  
Fb2  
C1 100pF  
C2 100pF  
R1  
1k  
R33  
R35  
2.7k  
13  
Comp2  
5k  
31  
VREF  
GND  
220pF  
C32  
4
Simplified Demo board schematic  
Rev. 2.3  
12/01/06  
8
NX2601  
J 6  
J 7  
T P 3  
Q 3  
R 1 9  
1
1
S W 1  
S W 2  
OP  
1 0  
R 1 7  
0
R 1 8  
C 1 0  
1 u  
T P 4  
S W 1 _ IN  
P V C C  
T P 7  
0
Q 2  
2N3904  
C 9  
C 8  
L 2  
1 6 T Q  
C
3 3 M  
R 1 6 6 T P B 6 8 M  
4 . 9 9 k  
U 1  
Vcc1  
S W 1 _ IN  
DO1603C-102  
C 2 2  
C 2 3  
1 6 S V P A 1 8 0OMP  
C 2 1  
C 2 4  
1 u  
D 1  
1 6 S V P A 3 9 M A A  
R 1 3  
0
11  
24  
25  
P V C C  
REG_Fb  
BST1  
D 1 N 5 8 1 9  
4 . 9 9 k  
T P 1  
L D O _ IN  
R 1 4  
Q
4
C 1 1  
.1 u  
R 1 5  
1 .6 5 k  
R 2 0  
0
Hdrv 1  
IR F 3 7 0 6  
C 7  
4 7 p  
J 2  
L 1  
DO5010P-781HC  
SW1  
SW1_OUT  
26  
27  
1
2
SW1  
10  
9
R 2 2  
REG_OUT  
AUX_VCC  
LDO_OUT  
C 5  
4 T P  
Q
5
OCP1  
E
1 5 0 M  
R 2 3  
1 0 .5 k  
R 2 1  
Q
1
op  
22  
23  
2 0 k  
C 1 4  
C 1 6  
C 1 5  
C 1 3  
R 1 2  
0
C 2 0  
M T D 3 0 5 5 E  
J 4  
8
Ldrv 1  
1
0
PVCC1  
IR F 3 7 0 6  
C 1 2  
4 7 0 p  
C 3  
1 5 0 p f  
L D O _ O U T  
P V C C  
32  
C 3 9  
. 1 u  
R 2 7  
1 0 . 4 k  
NC  
C 4 1  
1 u  
R 1 0  
0
21  
29  
T P 2  
J 1  
PGND1  
Fb1  
C 1 9  
R 2 6  
R 1 1  
T P 5  
1
7
1 . 5 k  
2 .7 n  
LDO_FB  
4 . 9 9 k  
C 1 7  
2 2 0 p  
C 1 8  
8 . 2 n  
R 2 5  
2 0 .8 k  
C 4  
4 T P  
R 6  
2 .3 5 k  
L 4  
C 6  
R 2 4  
E
1 5 0 M  
Vcc2  
28  
S W 2 _ IN  
Comp1  
DO1603C-102  
. 1 u  
4 . 9 9 k  
D 2  
R 7  
3
L D O _ IN  
S W 1 _ IN  
S W 2 _ IN  
EN_LDO  
EN_SW1  
EN_SW2  
C 3 6  
C 3 5  
C 3 3  
1 6 S V P A 3 9 M A A  
C 3 8  
1 u  
1 .5 k  
R 5  
O
P
J 9  
17  
16  
P V C C  
BST2  
1
2
L D O _ O U T  
D 1 N 5 8 1 9  
1 .2 5 k  
R 3 0  
1 6 S V P A 1 8 0 M  
4
R 8  
Hdrv 2  
1
0
Q
6
6 .8 k  
R 4  
IR F 7 8 2 2  
C 3 1  
.1 u  
J 3  
L 3  
DO5010P-222HC  
SW2  
SW2_OUT  
15  
14  
1
2
1 .2 5 k  
SW2  
R 9  
R 3 2  
C 3 0  
2
OCP2  
R 3 4  
2 0 k  
2 .7 k  
R 3  
3 k  
C 2 7  
C 2 9  
o p  
C 2 6  
C 2 8  
J 8  
op  
R 3 1  
0
1
2
11  
19  
18  
4
L D O _ IN  
L D O _ IN  
L D O _ IN  
T P 6  
1 .2 5 k  
Ldrv 2  
C 3 4  
4 7 0 p  
R 2  
PVCC2  
Q
7
12  
13  
14  
15  
16  
17  
18  
19  
20  
6
Rt  
IR F 7 8 2 2  
6 2 k  
P V C C  
3
C 4 2  
1 u  
C 1  
4
30  
20  
12  
S W 2 _ IN  
S W 2 _ IN  
Vp  
PGND2  
Fb2  
J 5  
1 0 0 p  
R 2 9  
3 . 5 k  
5
1
R 3 6  
1 k  
R 1  
1 k  
6
C 2 5  
R 2 8  
C 3 2  
2 2 0 p  
R 3 3  
C 3 7  
1 0 n  
C 2  
C 4 0  
. 1 u  
R 3 5  
2 . 7 k  
7
31  
3 3 0  
8 . 2 n F  
Vref  
13  
1 0 0 p  
Comp2  
8
4 . 9 9 k  
PACKAGE: MLPQ32L  
9
S W 2 _ IN  
S W 2 _ IN  
Size  
Document Number  
Rev  
A
10  
NX2601-02 EVL BRD SCHEMATIC  
S W 1 _ IN  
T h u r s d a y , M a r c h 2 4 , 2 0 0 5  
1
1
Date:  
Sheet  
of  
Figure 2 - Demo board schematic based on ORCAD  
Rev. 2.3  
12/01/06  
9
NX2601  
Bill of Materials  
Item numbeQuantity  
Value  
100p  
150pf  
4TPE150M  
.1u  
Manufacture  
SANYO  
1
2 C2,C1  
2
3
4
1 C3  
5 C4,C5,C26,C27,C28  
5 C6,C11,C31,C39,C40  
1 C7  
5
47p  
6
7
8
9
1 C8  
1 C9  
16TQC33M  
6TPB68M  
1u  
SANYO  
SANYO  
5 C10,C24,C38,C41,C42  
2 C12,C34  
470p  
10  
11  
2 C14,C13  
9 Q3,R14,C15,C16,C20,C22, OP  
C29,C30,C35  
2R5TPD680M6  
SANYO  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
2 C17,C32  
1 C18  
1 C19  
2 C21,C33  
2 C36,C23  
1 C25  
220p  
8.2n  
2.7n  
16SVPA39MAA SANYO  
16SVPA180M  
8.2nF  
SANYO  
1 C37  
10n  
2 D1,D2  
5 J1,J4,J5,J6,J7  
3 J2,J3,J9  
1 J8  
1 L1  
2 L2,L4  
1 L3  
1 Q1  
1 Q2  
2 Q4,Q5  
2 Q7,Q6  
1 R1  
1 R2  
3 R3,R4,R5  
1 R6  
2 R7,R26  
1 R8  
2 R35,R9  
D1N5819  
SCOPE TP  
CON2  
Tektronics  
CON20B  
DO5010P-781HC Coilcraft  
DO1603C-102  
DO5010P-222HC  
MTD3055E  
2N3904  
IRF3706  
IRF7822  
1k  
International Rectifier  
International Rectifier  
62k  
1.25k  
2.35k  
1.5k  
6.8k  
2.7k  
8 R10,R12,R17,R18,R20,R21, 0  
R30,R31  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
5 R11,R13,R16,R24,R33  
4.99k  
1.65k  
10  
10.5k  
20k  
20.8k  
10.4k  
330  
1 R15  
1 R19  
1 R22  
2 R34,R23  
1 R25  
1 R27  
1 R28  
1 R29  
1 R32  
1 R36  
3.5k  
3k  
10k  
7 TP1,TP2,TP3,TP4,TP5,TP6, TP  
TP7  
50  
1 U1  
NX2601_MLPQ  
NEXSEM INC.  
Rev. 2.3  
12/01/06  
10  
NX2601  
Demoboard waveforms  
Figure 3 - Start up waveform of VCC by internal regulator.  
Ch1(AUXVCC), Ch3( VCC&PVCC)  
Figure 6 - Output ripple for power output CH1 and CH2  
Figure 4 - Soft start for Channel 1 1.2V and chanel 2  
1.8V output  
Figure 7-Transient response for first channel 1.2V output  
Figure 5 - Soft start for Channel 1 1.2V and LDO output Figure 8 -Transient reponse for Channel 1. (zoomed)  
Rev. 2.3  
12/01/06  
11  
NX2601  
Demo Board Waveforms (Cont')  
Figure 12 - Ch1 is short. All channels go into hiccup.  
Figure 9 - Ch2 1.8V output transient 0 to 9A.  
Figure 13 - Ch2 is in short. All channels are in hiccup.  
Figure 10 - Ch2 1.8V transient (zoomed)  
Figure 14 - LDO in short. All channels go into hiccup.  
Figure 11 - Transient response for 2.5V LDO output  
Rev. 2.3  
12/01/06  
12  
NX2601  
APPLICATION INFORMATION  
Symbol Used In Application Information:  
V -VOUT VOUT  
1
IN  
DIRIPPLE  
=
´
´
LOUT  
V
F
S
IN  
...(2)  
VIN  
- Input voltage  
- Output voltage  
- Output current  
12V-1.2V 1.2V  
1
=
´
´
= 4.6A  
VOUT  
IOUT  
0.78uH  
12V 300kHz  
VRIPPLE - Output voltage ripple  
- Switching frequency  
Output Capacitor Selection  
FS  
Output capacitor is basically decided by the  
amount of the output voltage ripple allowed during steady  
state(DC) load condition as well as specification for the  
load transient. The optimum design may require a couple  
of iterations to satisfy both condition.  
IRIPPLE - Inductor current ripple  
Design Example  
Power stage design requirements:  
VIN=12V  
Based on DC Load Condition  
The amount of voltage ripple during the DC load  
condition is determined by equation(3).  
VOUT=1.2V  
IOUT =15A  
DIRIPPLE  
VRIPPLE<=20mV  
VTRAN<=100mV @ 15A step  
FS=300kHz  
DVRIPPLE = ESR´ DIRIPPLE  
+
...(3)  
8´ F ´ COUT  
S
Where ESR is the output capacitors' equivalent  
series resistance,COUT is the value of output capacitors.  
Typically when large value capacitors are selected  
such as Aluminum Electrolytic,POSCAP and OSCON  
types are used, the amount of the output voltage ripple  
is dominated by the first term in equation(3) and the  
second term can be neglected.  
Output Inductor Selection  
The selection of inductor value is based on induc-  
tor ripple current, power rating, working frequency and  
efficiency. Larger inductor value normally means smaller  
ripple current. However if the inductance is chosen too  
large, it brings slow response and higher cost. Usually  
the ripple current ranges from 20% to 40% of the output  
current. This is a design freedom which can be decided  
by design engineer according to various application re-  
quirements. The inductor value can be calculated by using  
the following equations:  
For this example, POSCAP are chosen as output  
capacitors, the ESR and inductor current typically de-  
termines the output voltage ripple.  
DVRIPPLE  
DIRIPPLE  
20mV  
4.6A  
ESRdesire  
=
=
= 4.3mW  
...(4)  
If low ESR is required, for most applications, mul-  
tiple capacitors in parallel are better than a big capaci-  
tor. For example, for 20mV output ripple, POSCAP  
2R5TPD680M6 with 6mW are chosen.  
V -VOUT VOUT  
1
IN  
LOUT  
=
´
´
DIRIPPLE  
V
F
S
IN  
...(1)  
IRIPPLE =k ´ IOUTPUT  
where k is between 0.2 to 0.4.  
Select k=0.3, then  
E S R E ´ DIR IPPLE  
N =  
...(5)  
D VR IPPLE  
12V-1.2V 1.2V  
1
Number of Capacitor is calculated as  
LOUT  
=
´
´
0.3´ 15A 12V 300kHz  
LOUT =0.8uH  
6m4.6A  
N =  
20mV  
Choose LOUT=0.78uH, then coilcraft inductor  
DO5010P-781HC is a good choice.  
Current Ripple is calculated as  
N =1.38  
The number of capacitor has to be round up to a  
integer. Choose N =2.  
Rev. 2.3  
12/01/06  
13  
NX2601  
If ceramic capacitors are chosen as output ca- tiple capacitor in parallel. The number of capacitors can  
pacitors, both terms in equation (3) need to be evaluated be calculated by the following  
to determine the overall ripple. Usually when this type of  
ESRE ´ DIstep  
VOUT  
N =  
+
´ t 2  
...(9)  
capacitors are selected, the amount of capacitance per  
single unit is not sufficient to meet the transient specifi-  
cation, which results in parallel configuration of multiple  
capacitors.  
DV  
2´ L´ CE ´ DV  
tran  
tran  
where  
0
if L £ Lcrit  
ì
ï
L´ DI  
t =  
í
ï
î
Based On Transient Requirement  
Typically, the output voltage droop during transient  
is specified as  
step  
...(10)  
- ESRE ´ CE  
if L ³ Lcrit  
VOUT  
DV  
< DV  
@step load I  
tran  
droop  
STEP  
For example, assume voltage droop during tran-  
sient is 100mV for 15A load step.  
During the transient, the voltage droop during the  
transient is composed of two sections. One section is  
dependent on the ESR of capacitor, the other section is  
a function of the inductor, output capacitance as well as  
input, output voltage. For example, for the overshoot  
when load from high load to light load with a ISTEP tran-  
sient load, if assuming the bandwidth of system is high  
enough, the overshoot can be estimated as the following  
equation.  
If the POSCAP 2R5TPD680M6 (680uF, 6mohm  
ESR) is used, the crticial inductance is given as  
ESRE ´ CE ´ VOUT  
Lcrit  
=
=
DIstep  
6m680mF´ 1.2V  
= 0.33mH  
15A  
The selected inductor is 0.78uH which is bigger  
than critical inductance. In that case, the output voltage  
transient not only dependent on the ESR, but also ca-  
pacitance.  
VOUT  
DVovershoot = ESR ´ DIstep  
+
´ t 2  
...(6)  
2´ L´ COUT  
where is the a function of capacitor, etc.  
t
number of capacitors is  
0
if L £ Lcrit  
ì
L´ DIstep  
ï
t =  
- ESRE ´ CE  
L´ DI  
t =  
í
ï
î
step  
...(7)  
...(8)  
VOUT  
- ESR ´ COUT  
if L ³ Lcrit  
VOUT  
0.78mH´ 15A  
=
- 6m680mF = 5.67us  
where  
ESR ´ COUT ´ VOUT ESRE ´ CE ´ VOUT  
1.2V  
Lcrit  
=
=
ESRE ´ DIstep  
DIstep  
DIstep  
VOUT  
N =  
+
´ t 2  
DV  
2´ L´ CE ´ DV  
tran  
tran  
where ESRE and CE represents ESR and capaci-  
tance of each capacitor if multiple capacitors are used  
in parallel.  
6m15A  
=
+
100mV  
1.2V  
´ (5.67us)2  
The above equation shows that if the selected out-  
put inductor is smaller than the critical inductance, the  
voltage droop or overshoot is only dependent on the ESR  
of output capacitor. For low frequency capacitor such  
as electrolytic capacitor, the product of ESR and ca-  
2´ 0.78mH´ 680mF´ 100mV  
=1.3  
The number of capacitors has to satisfied both ripple  
and transient requirement. Overall, we can choose N=2.  
It should be considered that the proposed equa-  
tion is based on ideal case, in reality, the droop or over-  
shoot is typically more than the calculation. The equa-  
tion gives a good start. For more margin, more capaci-  
tors have to choose after the test. Typically, for high  
pacitance is high and L £ Lcrit is true. In that case, the  
transient spec is likely to dependent on the ESR of ca-  
pacitor.  
For most cases, the output capacitors are mul-  
Rev. 2.3  
12/01/06  
14  
NX2601  
frequency capacitor such as high quality POSCAP es-  
where FZ1,FZ2,FP1 and FP2 are poles and zeros in  
pecially ceramic capacitor, 20% up 100% (for ceramic) the compensator. Their locations are shown in figure 15.  
more capacitors have to be chosen since the ESR of The transfer function of type III compensator is  
capacitors is so low that the PCB parasitics can affect given by:  
the results tremendously. More capacitors have to be  
(1+sR ´ C )´ 1+s(R +R )´ C  
V
1
[
]
4
2
2
3
3
e
=
´
selected to compensate these parasitic parameters.  
C2 ´ C  
VOUT sR2 ´ (C2 +C )  
1 )´ 1+sR ´ C  
1
(1+sR4 ´  
(
)
3
3
C2 +C  
1
Compensator Design  
Due to the double pole generated by LC filter of the  
power stage, the power system has 180o phase shift ,  
and therefore, is unstable by itself. In order to achieve  
accurate output voltage and fast transient response,  
compensator is employed to provide highest possible  
bandwidth and enough phase margin.Ideally,the Bode  
plot of the closed loop system has crossover frequency  
between1/10 and 1/5 of the switching frequency, phase  
margin greater than 50o and the gain crossing 0db with -  
20db/decade. Power stage output capacitors usually  
decide the compensator type. If electrolytic capacitors  
are chosen as output capacitors, type II compensator  
can be used to compensate the system, because the  
zero caused by output capacitor ESR is lower than cross-  
over frequency. Otherwise type III compensator should  
be chosen.  
Zf  
Vout  
Zin  
C1  
R3  
R2  
C2  
R4  
C3  
Fb  
Ve  
R1  
Vref  
power stage  
A. Type III compensator design  
LC  
F
For low ESR output capacitors, typically such as  
Sanyo OSCON and POSCAP, the frequency of ESR zero  
caused by output capacitors is higher than the cross-  
over frequency. In this case, it is necessary to compen-  
sate the system with type III compensator. The follow-  
ing figures and equations show how to realize the type III  
compensator by voltage mode amplifier.  
40dB/decade  
loop gain  
ESR  
F
20dB/decade  
1
FZ1  
FZ2  
=
=
=
=
...(11)  
...(12)  
...(13)  
...(14)  
2´ p ´ R4 ´ C2  
compensator  
1
2´ p ´ (R2 + R3 )´ C3  
1
F
P1  
2´ p ´ R3 ´ C3  
FZ1  
FO  
FP2  
FZ2  
FP1  
1
F
P2  
C1 ´ C2  
2´ p ´ R4 ´  
C1 + C2  
Figure 15 - Type III compensator and its bode plot  
15  
Rev. 2.3  
12/01/06  
NX2601  
The crossover frequency usually is selected as  
FLC<FO<FESR, and FO<=1/10~1/5Fs for type III  
compensator .  
1
C2 =  
2 ´ p ´ FZ1 ´ R4  
1
1.Calculate the location of LC double pole  
=
2 ´ p ´ 0.75 ´ 4.89kHz ´ 5kW  
F and ESR zero F  
.
LC  
ESR  
= 8.8nF  
1
Choose C2=8.2nF  
F
=
=
LC  
2´ p ´  
L
OUT ´ COUT  
6. Calculate C1 by equation (14) with pole Fp2 at  
half the swithing frequency.  
1
2´ p ´ 0.78uH´ 1320uF  
1
= 4.89kHz  
C1 =  
2 ´ p ´ R4 ´ FP2  
1
1
F
=
=
ESR  
2´ p ´ ESR´ COUT  
1
2 ´ p ´ 5kW´ 150kHz  
= 212pF  
=
2´ p ´ 3m1360uF  
Choose C1=220pF  
= 39kHz  
7. Calculate R3 by equation (13).  
2.Set R2 equal to10.4kW.  
1
R3 =  
R2 ´ VREF  
10.4k0.8V  
2´ p ´ F ´ C3  
R1=  
=
= 20.8kW  
P1  
VOUT -VREF  
1.2V-0.8V  
1
=
Choose R1= 20.8kW.  
3. Set zero FZ2 = FLC and Fp1 =FESR  
4. Calculate R4 and C3 with the crossover frequency  
2´ p ´ 39kHz´ 2.7nF  
= 1.5kW  
Choose R3= 1.5kW.  
.
smaller than 1/10~ 1/5 of the swithing frequency. Set  
FO=25kHz.  
B. Type II compensator design  
If the electrolytic capacitors are chosen as power  
stage output capacitors, usually the Type II compensa-  
tor can be used to compensate the system.  
Type II compensator can be realized by simple  
RC circuit as shown in figure 16.R3 and C1 introduce a  
zero to cancel the double pole effect. C2 introduces a  
pole to suppress the switching noise. The following equa-  
tions show the compensator pole zero location and con-  
stant gain.  
1
1
1
C3 =  
´ (  
-
)
2´ p ´ R2  
Fz2 F  
p1  
1
1
1
=
´ (  
-
)
2´ p ´ 10.4kW 4.89kHz 39kHz  
=2.8nF  
Choose C3=2.7nF.  
VOSC 2´ p ´ F ´ L  
O
R4 =  
=
´
´ Cout  
V
C3  
1V 2´ p ´ 25kHz´ 0.8uH  
in  
R3  
´
´ 1360uF  
Gain=  
... (15)  
... (16)  
... (17)  
12V  
2.7nF  
R2  
=5.3kW  
1
F =  
z
2´ p ´ R3 ´ C1  
1
Choose R4=5k  
5. Calculate C2 with zero Fz1 at 75% of the LC  
double pole by equation (11).  
F =  
p
2´ p ´ R3 ´ C2  
Rev. 2.3  
12/01/06  
16  
NX2601  
1
C2  
C1  
F
=
=
LC  
2´ p ´  
L
OUT ´ COUT  
Vout  
R3  
1
R2  
2´ p ´ 1.5uH´ 4500uF  
Fb  
Ve  
= 1.94kHz  
R1  
Vref  
1
F
=
ESR  
2´ p ´ ESR´ COUT  
1
=
2´ p ´ 6.33m4500uF  
= 5.6kHz  
power stage  
loop gain  
2.Set crossover frequency FO=20kHz>>FESR  
.
3. Set R2 equal to10kW. Based on output voltage,  
using equation 18, the final selection of R1 is 20kW.  
4.Calculate R3 value by the following equation.  
40dB/decade  
20dB/decade  
VO S C  
Vin  
2 ´ p ´ FO ´ L  
R 3 =  
´
´ R 2  
E S R  
1V  
2 ´ p ´ 20kHz ´ 1.5uH  
6.33m W  
=
´
´ 10kW  
12V  
=24.8kW  
Choose R3 =24.8kW.  
compensator  
Gain  
5. Calculate C1 by setting compensator zero FZ  
at 75% of the LC double pole.  
1
C1=  
P
F
F
F
Z
LCFESR  
FO  
2´ p ´ R3 ´ F  
z
1
=
2´ p ´ 24.8k0.75´ 1.94kHz  
Figure 16 - Type II compensator and its bode plot  
=4.4nF  
For type II compensator, FO has to satisfy  
FLC<FESR<<FO<=1/10~1/5Fs.  
Choose C1=4.7nF.  
F
6. Calculate C2 by setting compensator pole  
at half the swithing frequency.  
p
The following parameters are used as an ex-  
ample for type II compensator design, three 1500uF  
with 19mohm Sanyo electrolytic CAP 6MV1500WGL  
are used as output capacitors. Coilcraft DO5010P-  
152HC 1.5uH is used as output inductor. The other  
power stage information is that:  
1
C 2 =  
p ´ R 3 ´ Fs  
1
=
p ´ 2 4 .8k W ´ 2 0 0 k H z  
= 6 4 p F  
V
IN=12V, VOUT=1.2V, IOUT =15A, FS=200kHz.  
1.Calculate the location of LC double pole FLC  
and ESR zero FESR  
Choose C2=68pF  
.
Rev. 2.3  
12/01/06  
17  
NX2601  
pacitors supply current to the MOSFETs. Usually 1uF  
ceramic capacitor is chosen to decouple the high fre-  
quency noise. The bulk input capacitors are decided by  
voltage rating and RMS current rating. The RMS current  
in the input capacitor can be calculated  
Output Voltage Calculation  
Output voltage is set by reference voltage and  
external voltage divider. The reference voltage is fixed  
at 0.8V. The divider consists of two ratioed resistors  
so that the output voltage applied at the Fb pin is 0.8V  
when the output voltage is at the desired value. The  
following equation and picture show the relationship  
between VOUT , VREF and voltage divider.  
IRMS = IOUT ´ D ´ 1-D  
VOUT  
D =  
V
IN  
...(19)  
R 2 ´ VREF  
R1=  
VIN = 12V, VOUT=1.2V, IOUT=15A, using equation  
(19), the result of input RMS current is 4.5A.  
For higher efficiency, low ESR capacitors are  
recommended.  
...(18)  
VOUT -VREF  
where R2 is part of the compensator, and the  
value of R1 value can be set by voltage divider.  
Choose R2=10kW, to set the output voltage at  
1.8V, the result of R1 is 8kW.  
Two Sanyo OS-CON SVPA180M 16V 180uF  
29mO with 3.4A RMS rating are chosen as input bulk  
capacitors.  
Vout  
Power MOSFETs Selection  
R2  
The NX2601 requires two N-Channel power  
Fb  
MOSFETs. The selection of MOSFETs is based on  
maximum drain source voltage, gate source voltage,  
maximum current rating, MOSFET on resistance and  
power dissipation. The main consideration is the power  
loss contribution of MOSFETs to the overall converter  
efficiency. In this design example, two IRFR3706 are  
used. They have the following parameters: VDS=30V, ID  
=75A,RDSON =9mW,QGATE =23nC.  
R1  
Vref  
Voltage divider  
Figure 17 - Voltage divider  
In general, the minimum output load impedance  
including the resistor divider should be less than 5kW to  
prevent overcharge the output voltage by leakage cur-  
rent (e.g. Error Amplifier feedback pin bias current). A  
minimum load for 5kW less (<1/16w for most of applica-  
tion) is recommended to put at the output. For example,  
in this application,  
There are three factors causing the MOSFET power  
loss:conduction loss, switching loss and gate driver loss.  
Gate driver loss is the loss generated by discharg-  
ing the gate capacitor and is dissipated in driver circuits.  
It is proportional to frequency and is defined as:  
Pgate = (QHGATE ´ VHGS + QLGATE ´ VLGS )´ FS  
...(20)  
Vout=1.6V  
where QHGATE is the high side MOSFETs gate  
charge,QLGATE is the low side MOSFETs gate charge,VHGS  
is the high side gate source voltage, and VLGS is  
the low side gate source voltage.  
The power loss is 1/16W less  
RLOAD = 1.6V ´ 1.6V /(1/16W) = 40W  
Select minimum load is 1kW should be good  
enough.  
According to equation (3), PGATE =0.07W. This  
power dissipation should not exceed maximum power  
dissipation of the driver device.  
Input Capacitor Selection  
Input capacitors are usually a mix of high frequency  
ceramic capacitors and bulk capacitors. Ceramic ca-  
pacitors bypass the high frequency noise, and bulk ca-  
Conduction loss is simply defined as:  
Rev. 2.3  
12/01/06  
18  
NX2601  
The start up of NX2601 can be programmed through  
resistor divider at Enable pin. For example, for channel  
1, if the input bus voltage is 12V and we want NX2601  
starts when Vbus is above 8V. We can select  
R2=1.24k  
P
HCON =IOUT2 ´ D´ RDS(ON) ´ K  
LCON=IOUT2 ´ (1- D)´ RDS(ON) ´ K  
PTOTAL =P + P  
P
...(21)  
HCON  
LCON  
where the RDS(ON) will increases as MOSFET junc-  
tion temperature increases, K is RDS(ON) temperature  
dependency. As a result, RDS(ON) should be selected for  
the worst case, in which K equals to 1.4 at 125oC  
according to IRFR3706 datasheet. Using equation (4),  
the result of PTOTAL is 0.54W. Conduction loss should  
not exceed package rating or overall system thermal  
budget.  
(8V - 1.25V)´ R2  
R1 =  
= 6.8kW  
1.25V  
The NX2601 can be turned off by pulling down the  
ENable pin by extra signal MOSFET as shown in the  
above Figure. When Enable pin (ENSW1) is below 1.15V,  
the digital soft start is reset to zero. In addition, all the  
high side is off and output voltage is turned off.  
Switching loss is mainly caused by crossover con-  
duction at the switching transition. The total switching  
loss can be approximated.  
Frequency Selection  
The frequency can be set by external Rt resistor.  
The relationship between frequency and RT pin is shown  
as follows.  
1
PSW  
=
´ V ´ IOUT ´ TSW ´ F  
IN S  
...(22)  
2
where IOUT is output current, TSW is the sum of TR and  
TF which can be found in mosfet datasheet, and FS is  
switching frequency. The result of PSW is 1.5W.  
Swithing loss PSW is frequency dependent.  
Frequency(kHz) vs. RT  
900  
800  
700  
600  
500  
400  
300  
200  
100  
0
Soft Start and Enable  
NX2601 has two switching controller and one LDO  
controller. Each of them has individual digital soft start.  
Each channel has one enable pin for start up. When the  
Power Ready (POR) signal is high and the voltage at  
enable pin is above 1.25V, the internal digital counter  
starts to operate and the voltage at positive input of Error  
amplifier starts to increase, the feedback network will  
force the output voltage follows the reference and starts  
the output slowly. After 2048 cycles, the soft start is  
complete and the output voltage is regulated to the de-  
sired voltage decided by the feedback resistor divider  
20  
30  
40  
50  
60  
70  
Rt(kohm)  
Figure 19 - Frequency versus Rt resistor  
Vbus  
For example, for 300kHz operation, Rt is about  
POR  
R1  
R2  
OFF  
10k  
Digital  
start  
up  
ENSW1  
62kohm.  
ON  
1.25/1.15  
Over Current Limit Protection  
Over current limit for step down converter is  
Figure 18 - Enable and Shut down the NX2601  
achieved by sensing current through the low side  
with Enable pin.  
Rev. 2.3  
12/01/06  
19  
NX2601  
MOSFET. Inside NX2601, the current through Rt pin is important is that MOSFET has to be selected right pack-  
mirrored and injecting to the pin OCP. Since the current age to handle the thermal capability. For LDO, maxi-  
through Rt pin is decided as  
1 .2 5  
mum power dissipation is given as  
PLOSS = (VLDOIN - VLDOOUT )´ ILOAD  
= (3.3V - 2.5V)´ 2A =1.6W  
IR T  
=
R
t
This current is very accurate and does not change  
with silicon process and temperature, the over current  
limit tripping point can be set more accurate than tradi-  
tional current source. This scheme is the property of  
Nexsem. When synchronous FET is on, the voltage at  
node SW is given as  
Select IR MOSFET IRFR3706 with 9mW RDSON is  
sufficient.  
LDO Compensation  
The diagram of LDO controller including VCC regu-  
lator is shown in above figure 20. For low frequency  
capacitor such as electrolytic, POSCAP, OSCON, etc,  
The compensation parameter can be calculated as fol-  
lows.  
VSW =-IL ´ RDSON  
The voltage at pin OCP is given as  
IOCP ´ ROCP +VSW  
gm ´ ESR  
1
When the voltage is below zero, the over current  
occurs. The over current limit can be set by the following  
equation  
CC =  
´
2´ p ´ FO ´ Rf1 1+gm ´ ESR  
where FO is the desired loop gain.  
ISET = IRT ´ ROCP/RDSON  
LDO input  
For example, For 20A current limit and 9mohm  
Rdson for IRFR3706, the OCP set resistor is calculated  
as  
Vref  
R
f1  
1.25V  
IRT  
=
= 20uA  
ESR  
R
f2  
62k  
Rload  
Rc  
Cc  
ISET  
IRT  
Co  
20A  
ROCP  
=
´ RDSON  
=
´ 9mohm = 9kohm  
20uA  
Select OCP set resistor R=10.5k.  
For NX2601, if one channel goes to hiccup current  
limit, the other channels include LDO will go to hiccup  
too.  
Figure 20 - NX2601 LDO controller.  
Typically, FO has to be higher than zero caused by  
ESR. FO is typically around several tens kHz to a few  
hundred kHz. For this example, we select Fo=100kHz.  
gm is the forward trans-conductance of MOSFET.  
For IRFR3706, gm=53.  
LDO Selection Guide  
NX2601 offers a LDO controller. The selection of  
MOSFET to meet LDO is more straight forward. The  
selection is that the Rdson of MOSFET should meet  
the dropout requirement. For example.  
VLDOIN =3.3V  
Select Rf1=5kohm.  
Output capacitor is Sanyo POSCAP 4TPE150MI  
with 150uF, ESR=18mohm.  
VLDOOUT =2.5V  
ILoad =2A  
The maximum Rdson of MOSFET should be  
1
53´ 18mW  
CC =  
´
=155pF  
2´ p ´ 100kHz´ 5kW 1+53´ 18mW  
RRDSON = (VLDOIN - VLDOOUT )´ ILOAD  
= (3.3V - 2.5V) / 2A = 0.4W  
Choose CC=150pF.  
Most of MOSFETs can meet the requirement. More  
Rev. 2.3  
12/01/06  
20  
NX2601  
For electrolytic or POSCAP, RC is typically  
selected to be zero.  
Rf2 is determined by the desired output voltage  
Rf 2 = Rf1 ´ VREF /(VLDOOUT - VREF  
= 5k0.8V /(2.5V - 0.8) = 2.35kW  
Choose Rf2=2.34kW.  
as to the load as possible and plane connection is re-  
quired.  
4. Drain of the low-side MOSFET and source of  
the high-side MOSFET need to be connected thru a plane  
ans as close as possible.A snubber nedds to be placed  
as close to this junction as possible.  
)
5. Source of the lower MOSFET needs to be con-  
nected to the GND plane with multiple vias. One is not  
enough. This is very important. The same applies to the  
output capacitors and input capacitors.  
Current Limit for LDO  
Current limit of LDO is achieved by sensing the  
LDO feedback voltage. When LDO_FB pin is below 0.4V,  
the IC goes into hiccup mode. The IC will turn off all the  
channel (Channel 1 and Channel 2 ) for 2096 cycles and  
start to restart system again.  
6. Hdrv and Ldrv pins should be as close to  
MOSFET gate as possible. The gate traces should be  
wide and short. A place for gate drv resistors is needed  
to fine tune noise if needed.  
7. Vcc capacitor, BST capacitor or any other by-  
passing capacitor needs to be placed first around the IC  
and as close as possible. The capacitor on comp to  
GND or comp back to FB needs to be place as close to  
the pin as well as resistor divider.  
Layout Considerations  
The layout is very important when designing high  
frequency switching converters. Layout will affect noise  
pickup and can cause a good design to perform with  
less than expected results.  
8. The output sense line which is sensing output  
back to the resistor divider should not go through high  
frequency signals.  
There are two sets of components considered in  
the layout which are power components and small sig-  
nal components. Power components usually consist of  
input capacitors, high-side MOSFET, low-side MOSFET,  
inductor and output capacitors. A noisy environment is  
generated by the power components due to the switch-  
ing power. Small signal components are connected to  
sensitive pins or nodes. A multilayer layout which in-  
cludes power plane, ground plane and signal plane is  
recommended .  
9. All GNDs need to go directly thru via to GND  
plane.  
10. The feedback part of the system should be  
kept away from the inductor and other noise sources,  
and be placed close to the IC.  
11. In multilayer PCB, separate power ground and  
analog ground. These two grounds must be connected  
together on the PC board layout at a single point. The  
goal is to localize the high current path to a separate  
loop that does not interfere with the more sensitive ana-  
log control function.  
Layout guidelines:  
1. First put all the power components in the top  
layer connected by wide, copper filled areas. The input  
capacitor, inductor, output capacitor and the MOSFETs  
should be close to each other as possible. This helps to  
reduce the EMI radiated by the power loop due to the  
high switching currents through them.  
2. Low ESR capacitor which can handle input RMS  
ripple current and a high frequency decoupling ceramic  
cap which usually is 1uF need to be practically touch-  
ing the drain pin of the upper MOSFET, a plane connec-  
tion is a must.  
3. The output capacitors should be placed as close  
Rev. 2.3  
12/01/06  
21  
NX2601  
TYPICALAPPLICATIONS  
10  
R11  
+5V  
C15  
1uF  
R12  
5k  
C17  
68uF  
5
23 C1  
1uF  
11  
R13  
1.65k  
VCC  
+5V  
D1  
REG FB  
PVCC1  
VIN1  
L1 1uH  
47pF  
C16  
VIN1  
+12V  
24  
C3  
100uF  
C2  
180uF  
BST1  
10  
2N3904  
M5  
REG OUT  
AUXVCC  
LDO OUT  
C4  
0.1uF  
M1  
9
8
VIN2  
+3.3V  
25  
26  
C24 1uF  
R15  
HDRV1  
L2 1.5uH  
C20  
VOUT1  
C18  
150uF  
SW1  
+1.2V@15A  
0
R1 10.5k  
150pF  
27  
C7  
VOUT3  
+2.5V/2A  
7
OCP1  
LDO FB  
3 x (1500uF,19mohm)  
R16  
5k  
R17  
2.35k  
C19  
150uF  
R3  
10k  
22  
21  
29  
LDRV1  
M2  
PGND1  
Fb1  
R18  
3
C5  
4.7nF  
R5  
R4  
ENLDO  
28  
OFF R25  
Comp1  
10k  
R19  
20.8k  
1.5k  
24.8k  
2N3904  
C25  
1uF  
ON  
C22  
1.25k  
R26  
10k  
68pF  
18 C8  
1uF  
+5V  
PVCC2  
R20  
6.8k  
D2  
1
ENSW1  
VIN1  
17  
C9  
180uF  
R21  
BST2  
C11  
0.1uF  
1.25k  
16  
15  
M3  
L4 1.5uH  
HDRV2  
R22  
6.8k  
2
6
VOUT2  
+1.6V/10A  
ENSW2  
RT  
OFF R27  
SW2  
10k  
R23  
R6  
3k  
2N3904  
14  
19  
C14  
2 x (1500uF,19mohm)  
ON  
1.25k  
OCP2  
R28  
10k  
M4  
R8  
10k  
LDRV2  
20  
12  
R24 100k  
PGND2  
Fb2  
30  
31  
VP  
VREF  
C12  
4.7nF  
R10  
R9  
13  
C21 1nF  
Comp2  
10k  
25k  
C23  
GND  
68pF  
4
Figure 21 - NX2601 application with electrolytic capacitors as output capacitors  
Rev. 2.3  
12/01/06  
22  
NX2601  
TYPICALAPPLICATIONS(cont')  
10  
R11  
+5V  
C15  
1uF  
R12  
5k  
C17  
2.2uF  
R29  
10k  
5
23 C1  
1uF  
11  
R13  
1.65k  
VCC  
+5V  
D1  
REG FB  
PVCC1  
VIN1  
L1 1uH  
VIN1  
+12V  
C16  
33pF  
24  
C3  
100uF  
C2  
180uF  
BST1  
10  
REG OUT  
AUXVCC  
LDO OUT  
2N3904  
C4  
0.1uF  
M1  
9
8
VIN2  
+3.3V  
25  
26  
C24 1uF  
R15  
HDRV1  
L2 0.68uH  
C20  
M5  
VOUT1  
+1.2V@10A  
C18  
10uF  
SW1  
2.5k  
R1 10.5k  
100pF  
27  
22  
C7  
VOUT3  
+2.5V/2A  
7
OCP1  
LDO FB  
R2  
440  
6 x 47uF  
R16  
5k  
R17  
2.35k  
C19  
47uF  
R3  
11k  
LDRV1  
M2  
21  
29  
C6  
1.2nF  
PGND1  
Fb1  
R18  
1.5k  
3
C5  
3.9nF  
R5  
5k  
R4  
ENLDO  
28  
OFF R25  
Comp1  
10k  
R19  
22k  
2N3904  
C25  
1uF  
ON  
C22  
1.25k  
R26  
10k  
100pF  
18 C8  
1uF  
+5V  
PVCC2  
R20  
6.8k  
D2  
1
ENSW1  
VIN1  
17  
C9  
39uF  
R21  
BST2  
C11  
0.1uF  
1.25k  
16  
15  
M3  
L4 2.2uH  
HDRV2  
R22  
6.8k  
2
6
VOUT2  
ENSW2  
RT  
OFF R27  
10k  
SW2  
R23  
+1.8V/5A  
R6  
3k  
2N3904  
14  
19  
C14  
2 x47uF  
ON  
1.25k  
OCP2  
R28  
10k  
R7  
440  
M4  
R8  
11k  
LDRV2  
20  
12  
C6  
1.2nF  
R24 30k  
C21 1nF  
PGND2  
Fb2  
30  
31  
VP  
VREF  
C12  
R10  
R9  
13  
Comp2  
8.9k  
5k  
3.9nF  
100pF  
GND  
C23  
4
Figure 22 - NX2601 application with ceramic capacitors as output capacitors  
Rev. 2.3  
12/01/06  
23  
NX2601  
MLPQ 32 PIN 5 x 5 PACKAGE OUTLINE DIMENSIONS  
D
D2  
D/ 2  
D2/ 2  
R
2
1
Exposed Pad  
N N-1  
B
TOP VIEW  
BTM VIEW  
SEATING  
PLANE  
SIDE VIEW  
SYMBOL  
NAME  
32 PIN 5 x 5  
NOM  
0.90  
0.02  
0.20REF  
0.25  
5.00BSC  
3.45  
5.00BSC  
3.45  
0.50BSC  
0.40  
MIN  
0.80  
0.00  
MAX  
1.00  
0.05  
A
A1  
A3  
B
D
D2  
E
E2  
e
L
0.18  
3.30  
3.30  
0.30  
3.55  
3.55  
0.30  
0.09  
0.50  
---  
R
---  
ND  
NE  
6
6
NOTE:ALL DIMENSIONSARE DISPLAYED IN MILLIMETERS.  
ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.  
Rev. 2.3  
12/01/06  
24  
NX2601  
MLPQ 32 PIN 5 x 5 TAPE AND REEL INFORMATION  
NOTE:  
1. R7 = 7 INCH LOCK REEL, R13 = 13 INCH LOCK REEL.  
2.ALL DIMENSIONSARE DISPLAYED IN MILLIMETERS.  
Rev. 2.3  
12/01/06  
25  
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