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STM-S3+-38.88MHZ

型号：

STM-S3+-38.88MHZ

描述：

周边IC\n[ Peripheral IC ]

品牌：

ETC[ ETC ]

页数：

12 页

PDF大小：

221 K

下载PDF手册
Stratum 3+ Simplified  
Control Timing Modules  
STM-S3+  
2111 Comprehensive Drive  
Aurora, Illinois 60505  
Phone: 630-851-4722  
Fax: 630- 851- 5040  
www.conwin.com  
Application  
Features  
The Connor-Winfield Stratum 3+  
• 4 Operational Modes  
Simplified Control Timing Module can be  
used as a complete system clock module  
for any Stratum 3 timing application in  
which the design requires the added  
capabilities of a Stratum 3E level Hold  
Over within 5°C variation in accordance  
with GR-1244-CORE-1995.  
Connor-Winfield’s Stratum 3+ Timing  
module helps reduce the cost of your  
design by minimizing your development  
time and maximizing your control of the  
system clock with our simplified design.  
• Stratum 3 Clocking System  
• Stratum 3E Hold Over  
Accuracy ±5°  
• Hitless Reference Switching  
• 5 Active Alarms  
• Guaranteed Free Run  
• Lock Time of 100 Secs  
• TVL Alarm  
US Headquarters:  
630-851-4722  
European Headquarters:  
+353-62-472221  
General Description  
Functional Block Diagram  
The Connor-Winfield Stratum 3+ Simplified Control  
Timing Module (STM-3+) meets every Stratum 3  
requirement of GR-1244-CORE-1995. In addition, it also  
provides the enhanced Hold Over accuracy of Statum  
3E specifications over 5° C range. Control loop filters  
effectively attenuate any reference jitter and smooth out  
phase transients.  
Figure 1  
Free Run  
0
Ref 1  
CNTL A  
CNTL B  
1
2
PLL TVL  
Free Run  
Ref 2  
3
Hold Over  
Hold Over  
Alarm  
Out  
The STM-3+ is designed to be controlled externally.  
Full external control input allows the user to select and  
monitor any of the four possible operating modes:  
• Free Run Mode (A=0, B=0 =>Free Run=1)  
• Normal Mode #1 (A=1, B=0 => Ref 1=1)  
• Normal Mode #2 (A=0, B=1 =>Ref 2=1)  
• Hold Over Mode (A=1, B=1 =>Hold Over=1)  
Table 4 illustrates the control signal inputs (A,B) and the  
corresponding operational modes. Real-time indication  
of the operational mode is indicated by unique  
operating mode outputs on pins 1-4. In addition, all  
outputs can be placed into a high impedence state  
when a high signal is placed on the Tri-State control pin  
Normal Mode #1 results in an output signal that is  
phase locked to the External Reference Input #1.  
Normal Mode #2 results in an output signal that is  
phase locked to External Reference Input #2. Hold Over  
mode results in an output signal at or near the  
frequency as determined by a past historical value and  
the holdover performance of the STM. The historical  
value is updated every 40 secs. In the absence of  
External Control Inputs, the STM enters the default Free  
Run mode and signals an external alarm. Free Run  
mode is a guaranteed 4.ꢀ ppm of the nominal  
frequency.  
PHASE  
Ex Ref 1  
Ex Ref 2  
LOCK DETECT  
2 :1  
COMPARATOR  
MUX  
Sync_Out  
Stratum 3+  
OCXO  
DAC  
DAC  
FIFO  
FILTERS  
TUNING  
LIMIT  
Stratum 3  
TCXO  
Clock_Out  
MONITOR  
PLL TVL  
STM-S3+  
Package Layout  
Figure 2  
.030  
(.762mm)  
.150  
(3.810mm)  
(2.08mm)  
(1.02mm)  
.082  
.040  
.120  
(3.05mm)  
“A-A”  
DETAIL “A-A”  
2.40 + 0.02  
(60.96mm)  
The STM-S3+ provides an alarm pin that goes high  
during an alarm condition. Alarm signals are generated  
at the Alarm Out pin during the following conditions:  
• Holdover  
.650 + 0.02  
(16.50mm)  
.192  
(4.876mm)  
2.000  
(50.80mm)  
.200  
(5.08mm)  
24  
1
23  
22  
2
3
PIN 1  
• Free Run  
• Loss of Lock (LOL)  
• Loss of Reference (LOR)  
• Tune-Limit (PLL_TVL)  
21  
20  
4
5
6
7
8
9
19  
3.95+ 0.02  
18  
(100.330mm)  
A Tune-Limit (PLL_TVL) alarm signal indicates that  
the Voltage Controlled OCXO tuning voltage is  
approaching within the 10% limit of its lock capability  
and LOL may soon occur.  
17  
16  
15  
10  
11  
.300 TYP  
(22)  
(7.62mm)  
14  
.445  
13  
12  
(11.30mm)  
Bottom view  
Tolerance  
ꢀXXX + ꢀ005  
Preliminary Data Sheet #: TM021  
Page 2of 12  
Rev: P03  
Date: 06/27/01  
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice  
Absolute Maximum Rating  
Table 1  
STM-S3+  
Symbol  
VCC  
Parameter  
Minimum  
-0.5  
Nominal  
Maximum  
+7.0  
Units  
Volts  
Notes  
1.0  
Power Supply Voltage (Vcc to GND)  
Input Voltage  
-
-
-
VIN  
-0.5  
+5.5  
Volts  
1.0  
TSTG  
Storage Temperature  
-40.0  
+90  
deg. C  
1.0  
Recommended Operating Conditions  
Table 2  
STM-S3+  
Symbol  
VCC  
Parameter  
Minimum  
4.75  
Nominal  
Maximum  
5.25  
Units  
V
Notes  
Power Supply Voltage (vcc to GND)  
Power-on Reset Voltage Level  
5.0  
VPOR  
VIH  
4.25  
4.5  
V
2.0  
High Level Input Voltage (TTL Compatible) 2.0  
Low Level Input Voltage (TTL Compatible) 0.0  
Input Signal Transition Time  
5.25  
V
VIL  
0.8  
V
TIN  
250.0  
15.0  
nS  
pF  
CIN  
Input Capacitance  
VOH  
High Level Output Voltage  
@IOH=8.0 mA, Vcc minimum  
2.4  
V
3.0  
VOL  
Low Level Output Voltage  
@IOH=8.0 mA, Vcc maximum  
0.4  
V
THL  
TLH  
TRIP  
Clock out transition time high-to-low, no load  
4.0  
4.0  
nS  
nS  
Clock out transition time low-to-high, no load  
Input 8 kHz reference signal  
positive pulse width  
30.0  
30.0  
nS  
TRIN  
Input 8 kHz reference signal  
Negative pulse width  
nS  
TAB  
TOP  
Mode Select Response  
2
mS  
Standard Opearting temperature  
0.0  
70.0  
deg. C  
Operating Specifications  
Table 3  
STM-S3+  
Parameter  
Specifications  
Notes  
Frequency Range  
1ꢀ.384 MHz, 19.44 MHz, 38.88 MHz  
Supply Current  
350 mA Typical, 550 mA during warmup  
GR-1244-CORE 3.2.1, R3-1  
GR-1244-CORE 4.2-4.4  
GR-1244-CORE 4.2-4.4  
4.ꢀ ppm  
Timing Reference Inputs  
Jitter, Phase Transient and Wander Tolerances  
Wander Genration  
Free Run Accuracy  
Holdover Stability  
Initial Offset  
(0° - 70°) 0.039 ppm  
( 5°C) 0.012 ppm  
4.0  
0.001 ppm  
0.035 ppm  
0.003 ppm  
0.001 ppm  
0.010 ppm  
0.001 ppm  
Temperature  
Drift  
Holdover History  
Pull-in / Hold-in Range  
Lock Time  
40 sec  
4.ꢀ ppm  
5.0  
ꢀ.0  
< 100 sec  
0.001 ppm  
Lock Accuracy  
PLL-TVL Alarm Limits  
Within 10% of Tuning Range Limit, See Fig 8  
Preliminary Data Sheet #: TM021  
Page 3of 12  
Rev: P03  
Date: 06/27/01  
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice  
Pin Assignment  
Typical Application  
Figure 3  
Figure 4  
+5VDC  
Ex Ref 1  
GND  
Hold Over  
Ref 1  
5 Volt DC  
Power  
Supply  
Ref 2  
5 VDC  
Hold Over  
Ref 1  
System  
Control  
and Data  
Inputs  
Network  
Ex Ref 2  
GND  
Free Run  
GND  
Ex Ref 1  
Timing  
Reference  
Input  
Ref 2  
GND  
eg. BITS  
Ex Ref 2  
GND  
Free Run  
GND  
N/C  
N/C  
Clock_Out  
GND  
N/C  
N/C  
N/C  
Independent  
Clock  
Clock_Out  
GND  
N/C  
Tri-State  
N/C  
Tri-State  
N/C  
N/C  
N/C  
Loss of  
Reference  
Monitor  
System Clock  
Alarm Out  
Sync_Out  
GND  
Alarm Out  
CNTL A  
CNTL B  
Sync_Out  
GND  
Section  
CNTL A  
CNTL B  
PLL TVL  
PLL TVL  
BOTTOM VIEW  
Operational Modes  
Table 4  
Control Input Pins  
Output Indicator Pins  
Operational Mode  
Tri-State A  
B
Ref 1  
Ref 2 Hold Over Free Run  
PLL_TVL  
Alarm Out *Clock-Out  
Sync Out  
0
0
0
1
0
Free Run (default)  
Normal  
0
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
1
0
2
0
1
1
0
1
1
1
Per Spec  
Per Spec  
Per Spec  
Per Spec  
Per Spec  
Per Spec  
Per Spec  
Per Spec  
0
0
0
1
Mode #1  
Tune Limit  
LOR + LOL  
Normal  
0
1
0
0
0
0
1
0
0
Mode #2  
Tune Limit  
LOR + LOL  
0
0
0
0
1
1
X
1
X
Hold Over Mode  
Tri-State Mode  
0
0 or 1  
High Impedence  
* See GR-1244-CORE, Issue 3 for Clock Out and Sync Out  
Preliminary Data Sheet #: TM021  
Page 4of 12  
Rev: P03  
Date: 06/27/01  
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice  
Pin Description  
Table 5  
Pin # Pin Name  
Pin Information  
1
Hold Over  
Ref 1  
Mode indicator. When the STM is in holdover mode, Hold Over will be a logic high output.  
2
Mode indicator. When the STM is using External Reference #1, Ref 1 will be a logic high output.  
3
Ref 2  
Mode indicator. When the STM is using External Reference #2, Ref 2 will be a logic high output.  
4
Free Run  
GND  
Mode indicator. When the STM is in free run mode, Free Run will be a logic high output.  
5
Ground.  
ꢀ
N/C  
No connection required  
No connection required  
Tri-State control for all outputs. 1=Hi-Z, 0=normal.  
No connection required  
Alarm indicator output.  
Mode control input.  
Mode control input.  
Tuning Voltage Alarm.  
Ground.  
7
N/C  
8
Tri-State  
N/C  
9
10  
11  
12  
13  
14  
15  
1ꢀ  
17  
18  
Alarm Out  
CNTL A  
CNTL B  
PLL TVL  
GND  
Sync_Out  
N/C  
System clock output.  
No connection required  
Ground.  
GND  
Clock_Out An independent Stratum 3 clock output with the required 4.ꢀ ppm.  
Can be used for general purpose clocking needs.  
19  
20  
21  
22  
23  
24  
N/C  
No connection required  
Ground.  
GND  
Ex Ref 2  
GND  
External Reference #2 Input.  
Ground.  
Ex Ref 1  
+5 V DC  
External Reference #1 Input.  
+5 Volt DC supply. (Vcc)  
Preliminary Data Sheet #: TM021  
Page 5of 12  
Rev: P03  
Date: 06/27/01  
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice  
Operational Mode Change Timing Diagram  
Loss of Reference Timing Diagram  
Figure 5  
Figure ꢀ  
Change in  
Operational Mode  
External  
Reference  
Input  
Operational Mode  
Indicator  
Alarm  
tm  
tAon  
tAoff  
2 msec < tm < 4.125 msec  
2 msec < tAon < 6.125 msec  
0 msec < tAoff < 2.125 msec  
TVL Alarm Timing Diagram  
TVL Alarm Range  
Figure 7  
Figure 8  
Frequency  
(ppm)  
TVL Limit High  
Frequency  
max = 14ppm  
Sync_Out  
(Nominal Frequency)  
min  
9ppm  
TVL Limit Low  
Frequency  
TVL Alarm  
&
Alarm Out  
min = -9ppm  
max -14ppm  
t
0 < t < 2.125 msec  
Voltage Controlled  
OCXO Voltage (V)  
0.5 V  
3.8 V  
*The DAC is updated only when the output changes level. The maximum  
update rate is 8 kHz  
Maximum Current Draw  
Mounting Clearances  
Figure 9  
Figure 10  
0.600  
0.550  
0.500  
0.450  
0.400  
0.350  
0.300  
.020" MAX.  
.020"  
.030"  
PIN LAND  
0
1
2
3
4
5
6
7
8
ALL SOLDER AND/OR WIRE TAGS  
SHALL NOT EXTEND MORE THAN .020"  
BELOW PC BOARD BOTTOM SURFACE  
Elapsed Time (min)  
Preliminary Data Sheet #: TM021  
Page 6of 12  
Rev: P03  
Date: 06/27/01  
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice  
Typical System Test Set-up  
Figure 11  
GPS or LORAN  
Timing Source  
This device supplies system time  
information. It can be thought of as  
supplying "absolute time" reference  
information  
S
a
mple  
M
T
IE  
D
ata for  
S
T
M
-S 3/M ST  
M
-S  
3
1
0
0
1
.0  
.0  
.0  
.0  
E
E
E
E
-6  
-9  
-9  
T
yp i c  
a
l
r
e
s
p
o
n
2
s
e
-
3
0
8
0
0
s
e
c
o
n
d
t
e
s
t
-
J
it  
t
e
r
a
p
p
li e  
d
(
2
U
I
@
1
0
H
z
)
re  
f
d
a
t
e
A
P
R
2 1 9 9  
Possible Choices Include  
Stanford Research Model: FS700  
Truetime Model XXX  
k d h  
1
0
10  
MHz  
MTIE  
1
1
1
1
2
2
2
44  
44  
44  
-
-
-
5.2 Ma  
5.2 Ma  
5.6 Ma  
s
s
s
k
(
(
A
B
)
k
k
)
G
R25 3 -5 .4 .4 .3 .2  
-9  
0
1
0
.0  
E
-
3
1
.
0
E
+0  
1
0
.
0
E
+0  
1
0
0
.0  
E
+0  
1
.
0
E
r
+3  
1
d
0 .0 E+3  
O
bs e rva tion Tim e (s )  
C
o
p
yrig  
h
t
19  
9
8
C
o
n
n
o
-
W
in fie ld  
a
ll  
r
ig  
h
t
s
r
e
s
e
r
v
e
Target System Under Test  
External  
Reference  
Input  
Standards  
Compliance  
Documents  
DS1 rate RZ (1.544 MHz), E1 rate RZ or 8 kHz  
clock RZ with noise modulation  
Arbitrary  
Waveform  
Generator  
Clock or BITS logic level  
clock input (TTL, CMOS,  
etc.)  
MTIE, TDEV, Wander Transfer,  
and Wander Generation Plots  
S
ample Wan de r G en e ration (T D E V) for S T M /M S T M -S3  
1
0
0
1
.
.
.
.
0
E-  
E-  
E-  
E-  
-1  
6
9
9
9
2
T
yp ic  
a
t
l
r
e
s
p
o
n
2
s
e
-
3
0
8
0
0
s
e
c
o
n
d
te  
s
t
-
J
it  
t
e
r
a
p
p
lie  
d
(
2
UI  
@
1
0
H
z
)
r
e
f
d
a
e
A
P
R
2 1 9 9  
k
d h  
10  
MHz  
1
0
0
0
0
E
. . . . ...  
1
TDEV  
G
G
R1 24 4-Fig5 .1  
R1 24 4-Fig5  
-
3
Arbitrary  
Waveform  
Generator  
[Noise  
1
0
0
.0  
1
0
.
0
E
-
3
1
0
0
.0  
E
-
3
1
.0  
E
+0  
1
0
.
0
E
+0  
1
0
0
o
.0  
n
E
n
+0  
1 .0 E+3  
C
o
p
y
rig  
h
t
1
9
9
8
C
o r-W in fie ld a lll rig h t s re s e rv e d  
In te  
g
r
a
tio n Tim e (s e c )  
External  
Reference  
Input  
Source]  
Time-stamped ensemble  
based on absolute time  
reference (10MHz input)  
10  
MHz  
DS1 rate [1.544 MHz] BITS Bipolar  
Phase Error data output  
DS-1, OC-3, OC-12 electrical or optical signals  
External  
Reference  
Input  
Tektronix  
SJ300E  
10  
MHz  
HP53310A  
Modulation Analyzer / Time Interval Analyzer  
Wander Analyzer data (IEEE-488)  
External  
Reference  
Input  
IEEE-488 Controller  
Platform for software  
HP 53305A Phase Analyzer  
HP E1748A Sync  
Measurement  
Tektronix Wander Analyzer  
Preliminary Data Sheet #: TM021  
Page 7of 12  
Rev: P03  
Date: 06/27/01  
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice  
Typical MTIE - Over Temperature with Noise  
Figure 12  
MTIE (ns)  
GR-1244-CORE Mask  
100  
10  
1
0.01  
0.1  
1
10  
100  
1000  
10000  
1000  
Observation Interval (sec)  
Typical TDEV - Over Temperature with Noise  
Figure 13  
TDEV (ns)  
GR-1244-CORE Mask  
10  
1
0.1  
0.01  
0.01  
0.1  
1
10  
100  
1000  
10000  
100000  
Observation Time (sec)  
Preliminary Data Sheet #: TM021  
Page 8of 12  
Rev: P03  
Date: 06/27/01  
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice  
1 µs Phase Transient  
Figure 14  
10000  
1000  
100  
MTIE (ns)  
GR-253-CORE Mask  
10  
1
0.01  
0.1  
1
10  
100  
1000  
Observation time (sec)  
Reference Switching Phase Transient  
Figure 15  
10000  
MTIE (ns)  
GR-253-CORE Mask  
1000  
100  
10  
1
0.01  
0.1  
1
10  
Observation Time (sec)  
100  
1000  
Preliminary Data Sheet #: TM021  
Page 9of 12  
Rev: P03  
Date: 06/27/01  
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice  
Hold Over Entry and Exit with Same Reference  
Figure 1  
10000  
1000  
100  
10  
Entry  
Exit  
GR-253-CORE Mask  
1
0.01  
0.1  
1
10  
100  
Observation Interval  
Wander Transfer  
Figure 17  
1000  
Wander Transfer  
GR-253-CORE Mask  
100  
10  
1
0.1  
0.01  
0.1  
1
10  
100  
1000  
10000  
Observation Time (sec)  
Preliminary Data Sheet #: TM021  
Page 10 of 12  
Rev: P03  
Date: 06/27/01  
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice  
NOTES:  
1.0 Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are  
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under  
Recommended Operating Conditions is not implied. Exposure ot Absolute Maximum Ratings conditions for extended  
periods of time may affect device reliability.  
2.0 Power-on reset will be acivated within this level.  
3.0 Nominal signal into a CMOS load is usually 3V or greater.  
4.0 Hold Over stability is the cumulative fractional frequency offset containing Initial Offset, Temperature, and Drift  
components as described by Bellcore GR-1244-CORE 5.2.  
5.0 Pull-in range is the maximum frequency deviation on the reference inputs to the timing module that can be overcome to  
pull itself into synchronization with the reference.  
6.0 After 100 seconds at stable room temperature.  
Ordering Information:  
STM-S3+ – 16.384 MHz  
STM-S3+ – 19.44 MHz  
STM-S3+ – 38.88 MHz  
REVISION REVISION DATE  
NOTE  
P00  
P01  
P02  
P03  
ꢀ/29/00  
2/05/00  
2/27/01  
ꢀ/27/01  
Preliminary informational release  
Changed Format  
Minor Corrections  
Reformatted Layout  
Preliminary Data Sheet #: TM021  
Page 11 of 12  
Rev: P03  
Date: 06/27/01  
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice  
Data Sheet #: TM021  
Page 12 of 12  
Rev: 02  
Date: 02/27/01  
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice  
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 		STM 68 页

SIRENZA

 		STM-1116 800 - 1000 MHz的高线性度有源混频器发送[ 800 - 1000 MHz High Linearity Active Transmit Mixer ] 6 页

ETC

 		STM-16 16倍的光谱放大器，鉴性和多重触发[ 16 fold Spectroscopy Amplifier with Discriminators and Multiplicity Trigger ] 6 页

STANFORD

 		STM-2016 1800至2200年兆赫高线性度的硅锗主动发射混频器[ 1800 - 2200 MHz High Linearity Silicon Germanium Active Transmit Mixer ] 7 页

SIRENZA

 		STM-2116 1800年至2100年MHz的高线性度有源混频器发送[ 1800 - 2100 MHz High Linearity Active Transmit Mixer ] 6 页

ETC

 		STM-300C 清道夫收发模块STM 300和STM 300C[ Scavenger Transceiver Module STM 300 and STM 300C ] 2 页

SIRENZA

 		STM-3116 2100至2500年MHz的高线性度有源混频器发送[ 2100 - 2500 MHz High Linearity Active Transmit Mixer ] 6 页

CONNOR-WINFIELD

 		STM-S3 第3层简化的控制计时模块[ STRATUM 3 SIMPLIFIED CONTROL TIMING MODULES ] 6 页

ETC

 		STM-S3+-16.384MHZ 周边IC\n[ Peripheral IC ] 12 页

ETC

 		STM-S3+-19.44MHZ 周边IC\n[ Peripheral IC ] 12 页

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