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WM8711 / WM8711L

Internet Audio DAC with Integrated Headphone Amplifier

DESCRIPTION

FEATURES

•

Audio Performance

The WM8711 or WM8711L (WM8711/L) is a low power

stereo DAC with an integrated headphone driver. The

WM8711/L is designed specifically for portable MP3 audio

and speech players. The WM8711/L is also ideal for MD,

CD machines and DAT players.

-

DAC SNR 100dB (‘A’ weighted) at AVDD = 3.3V

DAC SNR 90dB (‘A’ weighted) at AVDD = 1.8V

(WM8711L)

•

Low Power Headphone Playback

-

Down to 20mWat 3.3V

Down to 6mWat 1.8V (WM8711L)

1.42 – 3.6V Digital Supply Operation

2.7 – 3.6 V Analogue Supply Operation

1.8 – 3.6 V Analogue Supply Operation (‘L’ Variant)

Stereo 24-bit multi-bit sigma delta DACs are used with

oversampling digital interpolation filters. Digital audio input

word lengths from 16-32 bits and sampling rates from 8KHz

to 96KHz are supported.

•

DAC Sampling Frequency: 8KHz – 96KHz

2 or 3-Wire MPU Serial Control Interface

Programmable Audio Data Interface Modes

-

Stereo audio outputs are buffered for driving headphones

from a programmable volume control, line level outputs are

also provided along with anti-thump mute and power

up/down circuitry.

I²S, Left, Right Justified or DSP

16/20/24/32 bit Word Lengths

Master or Slave Clocking Mode

The device is controlled via a 2 or 3 wire serial interface.

The interface provides access to all features including

volume controls, mutes, de-emphasis and extensive power

management facilities. The device is available in a small 28-

pin SSOP package or the smaller 28-Pin QFN (5x5x0.9 mm

Body) package.

•

Stereo Audio Outputs

Output Volume and Mute Controls

Highly Efficient Headphone Driver

28-Pin SSOP or 28-Pin QFN (5x5x0.9 mm) package

A USB mode is provided where all audio rates can be

derived from a single 12MHz or 24MHz MCLK, saving on

the need for a PLL or multiple crystals.

APPLICATIONS

•

Portable MP3 Players

CD and Minidisc Players

BLOCK DIAGRAM

W

HPVDD

HPGND

WM8711

CONTROL INTERFACE

RLINEIN

MUTE

H/P

DRIVER

VOL/

MUTE

RHPOUT

+6 to -73dB

1 dB Steps

DAC

Σ

DACDAT

DACLRC

ROUT

LOUT

DIGITAL

FILTERS

BCLK

+6 to -73dB

1 dB Steps

DAC

Σ

VOL/

MUTE

H/P

DRIVER

LHPOUT

LLINEIN

MUTE

CLKIN

DIVIDER

(Div x1,

x2)

CLKIN

DIVIDER

(Div x1,

x2)

OSC

WOLFSONMICROELECTRONICS plc

Production Data December 2002, Rev 3.1

www.wolfsonmicro.com

WM8711 / WM8711L

PIN CONFIGURATION

Production Data

ORDERING INFORMATION

DEVICE

TEMP RANGE AVDD RANGE PACKAGE

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1

DGND

DCVDD

XTO

DBVDD

CLKOUT

BCLK

-25 to 85^oC

2.7 to 3.6V

2

XWM8711EDS

28-pin SSOP

3

28-pin SSOP

-25 to 85^oC

XWM8711EDS/R

4

XTI/MCLK

SCLK

DACDAT

DACLRC

NC

(tape and reel)

5

Note:

6

SDIN

Reel quantity = 2,000

CSB

7

NC

8

MODE

LLINEIN

RLINEIN

NC

HPVDD

LHPOUT

RHPOUT

HPGND

LOUT

9

10

11

12

13

14

NC

VMID

ROUT

AGND

AVDD

DEVICE

TEMP RANGE AVDD RANGE PACKAGE

XWM8711EFL

WM8711LEFL

-25 to 85^oC

2.7 to 3.6V

1.8 to 3.6V

28 pin QFN

21 20 19 18 17 16 15

28 pin QFN

(tape and reel)

28 pin QFN

XWM8711EFL/R -25 to 85^oC

WM8711LEFL/R -25 to 85^oC

2.7 to 3.6V

1.8 to 3.6V

14

RHPOUT

NC 22

13 LHPOUT

12 HPVDD

23

24

25

26

27

28

RLINEIN

LLINEIN

MODE

CSB

(tape and reel)

Note:

NC

11

Reel quantity = 3,500

10 NC

9

SDIN

SCLK

DACLRC

8

DACDAT

1

2

3

4

5

6

7

PD Rev 3.1 December 2002

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WM8711 / WM8711L

PINDESCRIPTION

Production Data

28 PIN

SSOP

1

28 PIN

QFN

5

NAME

TYPE

DESCRIPTION

DBVDD

CLKOUT

BCLK

Supply

Digital Buffers VDD

2

6

Digital Output

Buffered Clock Output

3

7

Digital Input/Output Digital Audio Bit Clock, Pull Down (see Note 1)

Digital Input

DAC Digital Audio Data Input

Digital Input/Output DAC Sample Rate Left/Right Clock, Pull Down (see Note 1)

4

8

DACDAT

DACLRC

5

9

6

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

NC

No Connection

7

No Connection

8

HPVDD

LHPOUT

RHPOUT

HPGND

LOUT

Supply

Headphone VDD

9

Analogue Output

Ground

Left Channel Headphone Output

Right Channel Headphone Output

Headphone GND

10

11

12

13

14

15

16

17

18

19

20

21

22

Analogue Output

Supply

Left Channel Line Output

Right Channel Line Output

Analogue VDD

ROUT

AVDD

AGND

Ground

Analogue GND

VMID

Analogue Output

NC

Mid-rail reference decoupling point

No Connection

NC

No Connection

RLINEIN

LLINEIN

MODE

CSB

Analogue Input

Digital Input

Right Channel Line Input (AC coupled)

Left Channel Line Input (AC coupled)

Control Interface Selection, Pull up (see Note 1)

3-Wire MPU Chip Select/ 2-Wire MPU interface address

selection, active low, Pull up (see Note 1)

23

24

25

26

27

28

27

28

1

SDIN

SCLK

Digital Input/Output 3-Wire MPU Data Input / 2-Wire MPU Data Input

Digital Input

Digital Output

Supply

3-Wire MPU Clock Input / 2-Wire MPU Clock Input

Crystal Input or Master Clock Input (MCLK)

Crystal Output

XTI/MCLK

XTO

2

3

DCVDD

DGND

Digital Core VDD

4

Ground

Digital GND

Note:

1. Pull Up/Down only present when Control Register Interface ACTIVE=0 to conserve power.

PD Rev 3.1 December 2002

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WM8711 / WM8711L

Production Data

ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at

or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical

Characteristics at the test conditions specified.

ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible

to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage

of this device.

The WM8711 and WM8711L (in both SSOP and QFN packages) have been classified as MSL1, which has an unlimited floor life

at <30°C / 85% Relative Humidity and therefore will not be supplied in moisture barrier bags.

CONDITION

MINMAX

-0.3V

Digital supply voltage

+3.63V

Analogue supply voltage

-0.3V

Voltage range digital inputs

DGND -0.3V

AGND -0.3V

DVDD +0.3V

AVDD +0.3V

40MHz

Voltage range analogue inputs

Master Clock Frequency (see Note 4)

Operating temperature range, T_A

Storage temperature prior to soldering

Storage temperature after soldering

Package body temperature (soldering 10 seconds)

Package body temperature (soldering 2 minutes)

-25°C

+85°C

30°C max / 85% RH max

-65°C

+150°C

+260°C

+183°C

Notes:

1. Analogue and digital grounds must always be within 0.3V of each other.

2. The digital supply core voltage (DCVDD) must always be less than or equal to the analogue supply voltage (AVDD) or

digital supply buffer voltage (DBVDD).

3. The digital supply buffer voltage (DBVDD) must always be less than or equal to the analogue supply voltage (AVDD).

4. When CLKIDIV2 = 1.

RECOMMENDED OPERATING CONDITIONS – WM8711

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Digital supply range (Core)

Digital supply range (Buffer)

Analogue supply range

Ground

DCVDD

DBVDD

1.42

2.7

1.5

3.3

0

3.6

V

AVDD, HPVDD

DGND,AGND,HPGND

2.7

RECOMMENDED OPERATING CONDITIONS – WM8711L

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Digital supply range (Core)

Digital supply range (Buffer)

Analogue supply range

Ground

DCVDD

DBVDD

1.42

1.8

1.5

3.6

V

AVDD, HPVDD

DGND,AGND,HPGND

1.8

0

PD Rev 3.1 December 2002

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WM8711 / WM8711L

Production Data

ELECTRICAL CHARACTERISTICS – WM8711

Test Conditions

AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, T_A= +25^oC, Slave Mode, fs = 48kHz, MCLK =

256fs unless otherwise stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Digital Logic Levels (CMOS Levels)

Input LOWlevel

V_IL

V_IH

V_OL

0.3 x DBVDD

V

Input HIGH level

0.7 x DBVDD

0.9 x DBVDD

Output LOW

I_OL= 1mA

0.10 x

DBVDD

Output HIGH

V_OH

I_OH= -1mA

V

Power On Reset Threshold (DCVDD)

DCVDD Threshold On -> Off

Hysteresis

0.9

0.3

0.6

V

DCVDD Threshold Off -> On

Analogue Reference Levels

Reference voltage (VMID)

Potential divider resistance

V_VMID

R_VMID

AVDD/2

50k

V

Ohms

Line Output for DAC Playback Only (Load = 10K ohms. 50pF)

0dBFs Full scale output voltage

At LINE outputs

1.0 x

AVDD/3.3

100

Vrms

dB

Signal to Noise Ratio

(Note 1,2)

SNR

A-weighted,

@ fs = 48kHz

A-weighted

95

85

100

98

@ fs = 96kHz

A-weighted,

@ fs = 48kHz, AVDD

= 2.7V

Dynamic Range (Note 2)

Total Harmonic Distortion

DR

A-weighted, -60dB

full scale input

100

dB

THD

1kHz, 0dBFs

1kHz, -3dBFs

1kHz 100mVpp

-86

-90

50

-80

Power Supply Rejection Ratio

PSRR

dB

20Hz to 20kHz

100mVpp

45

DAC channel separation

1kHz, 0dB signal

100

dB

Vrms

dB

Analogue Line Input to Line Output (Load = 10k ohms. 50pF, No Gain on Input ) Bypass Mode

0dB Full scale output voltage

1.0 x

AVDD/3.3

101

Signal to Noise Ratio

(Note 1,2)

SNR

THD

90

Total Harmonic Distortion

1kHz, 0dB

-93

-85

dB

PD Rev 3.1 December 2002

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WM8711 / WM8711L

Production Data

Test Conditions

AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, T_A= +25^oC, Slave Mode, fs = 48kHz, MCLK =

256fs unless otherwise stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Vrms

mW

Stereo Headphone Output

0dB Full scale output voltage

1.0 x

AVDD/3.3

30

Max Output Power

P_O

RL = 32 ohms

RL = 16 ohms

55

Signal to Noise Ratio (Note 1,2)

Total Harmonic Distortion

SNR

THD

A-weighted

90

98

dB

%

1kHz, R_L= 32 Ohms,

0.056

-65

0.1

-60

1.0

-40

P

_O= 10mW rms

dB

1kHz, R_L= 32 Ohms,

P_O= 20mW rms

1kHz 100mVpp

0.56

-45

Power Supply Rejection Ratio

PSRR

50

dB

20Hz to 20kHz

100mVpp

45

Programmable Gain

1kHz

-73

6

1

6

dB

Programmable Gain Step Size

Mute attenuation

1kHz, 0dB

80

Notes:

1. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’

weighted over a 20Hz to 20kHz bandwidth.

2. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such

a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical

Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic

specification values.

3. VMID decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance).

TERMINOLOGY

1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output

with no signal applied. (No Auto-zero or Automute function is employed in achieving these results).

2. Dynamic range (dB) - DR is a measure of the difference between the highest and lowest portions of a signal. Normally

a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it.

(e.g. THD+N @ -60dB= -32dB, DR= 92dB).

3. THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.

4. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band).

5. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from

the other. Normally measured by sending a full scale signal down one channel and measuring the other.

6. Pass-Band Ripple - Any variation of the frequency response in the pass-band region.

PD Rev 3.1 December 2002

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WM8711 / WM8711L

Production Data

POWER CONSUMPTION – WM8711

MODE DESCRIPTION

CURRENT CONSUMPTION

TYPICAL

AVDD

(3.3V)

HPVDD DCVDD DBVDD UNITS

(3.3V)

(1.5V)

(3.3V)

DAC Playback, oscillator

and CLKOUT enabled

0

1

0

1

0

1

3.5

1.7

1.3

1.5

mA

DAC Playback, using

external MCLK

3.5

1.7

1.3

0.1

Standby

0

1

17

0.4

0.3

0.7

0.2

0.1

µA

Power Down

0.4

Table 1 Powerdown Mode Current Consumption Examples

Notes:

1. T_A= +25^oC. Slave Mode, fs = 48kHz, MCLK = 256fs (12.288MHz).

2. All figures are quiescent, with no signal.

3. The power dissipation in the headphone itself not included in the above table.

ELECTRICAL CHARACTERISTICS – WM8711L

All Other Characteristics are as for the WM8711

Test Conditions

AVDD, HPVDD, DBVDD = 1.8V, AGND = 0V, DCVDD = 1.4V, DGND = 0V, T_A= +25^oC, Slave Mode, fs = 48kHz, MCLK =

256fs unless otherwise stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

90

MAX

UNIT

Line Output for DAC Playback Only (Load = 10K ohms. 50pF)

Signal to Noise Ratio

(Note 1,2)

SNR

A-weighted,

@ fs = 48kHz

A-weighted

85

dB

90

@ fs = 96kHz

Dynamic Range (Note 2)

Total Harmonic Distortion

DR

A-weighted, -60dB

full scale input

85

90

dB

THD

1kHz, 0dBFs

1kHz, -3dBFs

-81

-88

-75

Stereo Headphone Output

Max Output Power

P_O

RL = 32 ohms

RL = 16 ohms

A-weighted

9

mW

dB

18

86

Signal to Noise Ratio

(Note 1,2)

SNR

THD

80

Total Harmonic Distortion

1kHz, R_L= 32 ohms @

0.18

-55

%

P

_O= 9mW rms

dB

Notes:

1. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’

weighted over a 20Hz to 20kHz bandwidth.

2. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such

a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical

Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic

specification values.

PD Rev 3.1 December 2002

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7

WM8711 / WM8711L

TERMINOLOGY

Production Data

1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output

with no signal applied. (No Auto-zero or Automute function is employed in achieving these results).

2. Dynamic range (dB) - DR is a measure of the difference between the highest and lowest portions of a signal. Normally

a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it.

(e.g. THD+N @ -60dB= -32dB, DR= 92dB).

3. THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.

4. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band).

5. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from

the other. Normally measured by sending a full scale signal down one channel and measuring the other.

6. Pass-Band Ripple - Any variation of the frequency response in the pass-band region.

POWER CONSUMPTION – WM8711L

MODE DESCRIPTION

CURRENT CONSUMPTION

TYPICAL

AVDD

(1.8V)

HPVDD DCVDD DBVDD UNITS

(1.8V)

(1.5V)

(1.8V)

DAC Playback, oscillator

and CLKOUT enabled

0

1

0

1

0

1

1.7

0.5

1.2

0.8

mA

DAC Playback, using

external MCLK

1.7

0.5

1.2

0.03

Standby

0

1

9

-

0.1

-

0.4

0.3

-

µA

Power Down

Table 2 Powerdown Mode Current Consumption Examples

Notes:

1. T_A= +25^oC. Slave Mode, fs = 48kHz, MCLK = 256fs (12.288MHz).

2. All figures are quiescent, with no signal.

3. The power dissipation in the headphone itself not included in the above table.

PD Rev 3.1 December 2002

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WM8711 / WM8711L

Production Data

MASTER CLOCK TIMING

t_XTIL

MCLK

t_XTIH

t_XTIY

Figure 1 System Clock Timing Requirements

Test Conditions

AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, T_A= +25^oC, Slave Mode fs = 48kHz, MCLK = 256fs

unless otherwise stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

System Clock Timing Information

MCLK System clock pulse width

high

t_XTIH

t_XTIL

t_XTIY

18

ns

MCLK System clock pulse width

low

MCLK System clock cycle time

MCLK Duty cycle

54

40:60

60:40

DIGITAL AUDIO INTERFACE – MASTER MODE

BCLK

(Output)

t_DL

DACLRC

(Output)

t_DLT

t_DHT

DACDAT

Figure 2 Digital Audio Data Timing - Master Mode

Test Conditions

AVDD, HPVDD, DVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, T_A= +25^oC, Slave Mode, fs = 48kHz, XTI/MCLK =

256fs unless otherwise stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

DACLRC propagation delay

from BCLK falling edge

t_DL

0

10

ns

DACDAT setup time to

BCLCK rising edge

t_DST

t_DHT

10

DACDAT hold time from

BCLK rising edge

PD Rev 3.1 December 2002

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WM8711 / WM8711L

Production Data

DIGITAL AUDIO INTERFACE – SLAVE MODE

t_BCH

t_BCL

BCLK

(Input)

t_BCY

DACLRC

(Input)

t_LRSU

t_DS

t_LRH

DACDAT

Figure 3 Digital Audio Data Timing – Slave Mode

Test Conditions

AVDD, HPVDD, DVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, T_A= +25^oC, slave mode, fs = 48kHz, MCLK = 256fs

unless otherwise stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

BCLK cycle time

t_BCY

t_BCH

t_BCL

50

20

10

ns

BCLK pulse width high

BCLK pulse width low

DACLRC set-up time to

BCLK rising edge

t_LRSU

DACLRC hold time from

BCLK rising edge

t_LRH

t_DS

10

ns

DACDAT set-up time to

BCLK rising edge

DACDAT hold time from

BCLK rising edge

t_DH

MPU INTERFACE TIMING

t_CSL

t_CSH

CSB

t_CSS

t_SCY

t_SCS

t_SCH

t_SCL

SCLK

SDIN

LSB

t_DSU

t_DHO

Figure 4 Program Register Input Timing - 3-Wire MPU interface Timing

PD Rev 3.1 December 2002

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WM8711 / WM8711L

Production Data

Test Conditions

AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, T_A= +25^oC, Slave Mode, fs = 48kHz, MCLK =

256fs unless otherwise stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Program Register Input Information

SCLK rising edge to CSB rising

edge

t_SCS

60

ns

SCLK pulse cycle time

SCLK pulse width low

SCLK pulse width high

SDIN to SCLK set-up time

SCLK to SDIN hold time

CSB pulse width low

t_SCY

t_SCL

t_SCH

t_DSU

t_DHO

t_CSL

t_CSH

t_CSS

80

20

ns

CSB pulse width high

CSB rising to SCLK rising

t₃

t₅

SDIN

t₄

t₆

t₂

t₈

SCLK

t₇

t₁

t₁₀

Figure 5 Program Register Input Timing – 2-Wire MPU Interface Timing

Test Conditions

AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, T_A= +25^oC, Slave Mode, fs = 48kHz, MCLK =

256fs unless otherwise stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Program Register Input Information

SCLK Frequency

0

400

kHz

ns

us

ns

SCLK Low Pulsewidth

SCLK High Pulsewidth

Hold Time (Start Condition)

Setup Time (Start Condition)

Data Setup Time

t₁

t₂

600

1.3

600

100

t₃

t₄

t₅

SDIN, SCLK Rise Time

SDIN, SCLK Fall Time

Setup Time (Stop Condition)

Data Hold Time

t₆

300

t₇

t₈

600

t₁₀

900

PD Rev 3.1 December 2002

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WM8711 / WM8711L

Production Data

DEVICE DESCRIPTION

INTRODUCTION

The WM8711/L is a low power audio DAC designed specifically for portable audio products. Its

features, performance and low power consumption make it ideal for portable MP3, CD and mini-disc

players.

The WM8711/L includes line and headphone outputs from the on-board DAC, configurable digital

audio interface and a choice of 2 or 3 wire MPU control interface. It is fully compatible and an ideal

partner for a range of industry standard microprocessors, controllers and DSPs.

The on-board digital to analogue converter (DAC) accepts digital audio from the digital audio

interface. Digital filter de-emphasis at 32kHz, 44.1kHz and 48kHz can be applied to the digital data

under software control. The DAC employs

a high quality multi-bit high-order oversampling

architecture to again deliver optimum performance with low power consumption.

The DAC outputs and Line Inputs (BYPASS) are available both at line level and through a

headphone amplifier capable of efficiently driving low impedance headphones. The headphone

output volume is adjustable in the analogue domain over a range of +6dB to –73dB and can be

muted.

The design of the WM8711/L minimises power consumption without compromising performance. It

includes the ability to power off selective parts of the circuitry under software control, thus conserving

power. Separate power save modes can be configured under software control including a standby

and power off mode.

Special techniques allow the audio to be muted and the device safely placed into standby, sections

of the device powered off, volume levels adjusted without any audible clicks, pops or zipper noises.

Therefore standby and power off modes may be used dynamically under software control, whenever

playback is not required.

The device caters for a number of different sampling rates including industry standard 8kHz, 32kHz,

44.1kHz, 48kHz, 88.2kHz and 96kHz. The WM8711/L has two schemes to support the

programmable sample rates: Normal industry standard 256/384fs sampling mode may be used.

A

special USB mode is included, where all audio sampling rates can be generated from a 12.00MHz

USB clock. The digital filters used for playback are optimised for each sampling rate used.

The digital audio interface can support a range of audio data formats including I2S, DSP Mode (a

burst mode in which frame sync plus 2 data packed words are transmitted), MSB-First, left justified

and MSB-First, right justified. The digital audio interface can operate in both master or slave modes.

The software control uses either a 2 or 3-wire MPU interface.

AUDIO SIGNAL PATH

DAC FILTERS

The DAC filters perform true 24 bit signal processing to convert the incoming digital audio data from

the digital audio interface at the specified sample rate to multi-bit oversampled data for processing by

the analogue DAC. Figure 6 illustrates the DAC digital filter path.

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FROM DIGITAL

AUDIO

INTERFACE

DIGITAL

INTERPOLATION

FILTER

TO LINE

OUTPUTS

DIGITAL

DE_EMPHASIS

MUTE

DEEMP

DACMU

Figure 6 DAC Filter Schematic

The DAC digital filter can apply digital de-emphasis under software control, as shown in Table 3. The

DAC can also perform a soft mute where the audio data is digitally brought to a mute level. This

removes any abrupt step changes in the audio that might otherwise result in audible clicks in the

audio outputs.

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

De-emphasis Control

0000101

2:1

DEEMP[1:0]

00

(Digital)

Digital Audio

Path Control

11 = 48KHz

10 = 44.1KHz

01 = 32KHz

00 = Disable

3

DACMU

1

DAC Soft Mute Control

(Digital)

1 = Enable soft mute

0 = Disable soft mute

Table 3 DAC Software Control

DAC

The WM8711/L employs a multi-bit sigma delta oversampling digital to analogue converter. The

scheme for the converter is illustrated in Figure 7.

FROM DAC

DIGITAL

FILTERS

TO LINE OUTPUT

Figure 7 Multi-Bit Oversampling Sigma Delta Schematic

The DAC converts the multi-level digital audio data stream from the DAC digital filters into high

quality analogue audio.

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LINE OUTPUTS

The WM8711/L provides two low impedance line outputs LLINEOUT and RLINEOUT, suitable for

driving typical line loads of impedance 10K and capacitance 50pF.

The LLINEOUT and RLINEOUT outputs are only available at a line output level and are not level

adjustable in the analogue domain, having a fixed gain of 0dB. The level is fixed such that at the DAC

full scale level the output level is Vrms at AVDD = 3.3 volts. Note that the DAC full scale level tracks

directly with AVDD. The scheme is shown in Figure 8. The line output includes a low order audio low

pass filter for removing out-of band components from the sigma-delta DAC. Therefore no further

external filtering is required in most applications.

BYPASS

FROM LINE

INPUTS

DACSEL

FROM DAC

LINEOUT

VMID

TO HEADPHONE AMP

Figure 8 Line Output Schematic

The line output is muted by either muting the DAC (analogue) or Soft Muting (digital) and disabling

the BYPASS path. Refer to the DAC section for more details. Whenever the DAC is muted or the

device placed into standby mode the DC voltage is maintained at the line outputs to prevent any

audible clicks from being present.

The software control for the line outputs is shown in Table 4.

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Bypass Switch

0000100

Analogue

3

BYPASS

1

1 = Enable Bypass

0 = Disable Bypass

DAC Select

Audio

Path

Control

4

DACSEL

0

1 = Select DAC

0 = Don’t select DAC

Table 4 Output Software Control

The recommended external components are shown in Figure 9.

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R2

LINEOUT

C1

R1

AGND

Figure 9 Line Outputs Application Drawing

Recommended values are C1 = 10µF, R1 = 47k, R2 = 100 Ohms

C1 forms a DC blocking capacitor to the line outputs. R1 prevents the output voltage from drifting so

protecting equipment connected to the line output. R2 forms a de-coupling resistor preventing

abnormal loads from disturbing the device. Note that poor choice of dielectric material for C1 can

have dramatic effects on the measured signal distortion at the output.

HEADPHONE AMPLIFIER

The WM8711/L has a stereo headphone output available on LHPOUT and RHPOUT. The output is

designed specifically for driving 16 or 32 ohm headphones with maximum efficiency and low power

consumption. The headphone output includes a high quality volume level adjustment and mute

function.

The scheme of the circuit is shown in Figure 10.

FROM

DAC VIA

LINEOUT

HPOUT

VMID

Figure 10 Headphone Amplifier Schematic

LHPOUT and RHPOUT volumes can be independently adjusted under software control using the

LHPVOL[6:0] and RHPVOL[6:0] bits respectively of the headphone output control registers. The

adjustment is logarithmic with an 80dB range in 1dB steps from +6dB to –73dB.

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The headphone outputs can be separately muted by writing codes less than 0110000 to

LHPVOL[6:0] or RHPVO[6:0]L bits. Whenever the headphone outputs are muted or the device

placed into standby mode, the DC voltage is maintained at the line outputs to prevent any audible

clicks from being present.

A zero cross detect circuit is provided at the input to the headphones under the control of the LZCEN

and RZCEN bits of the headphone output control register. Using these controls the volume control

values are only updated when the input signal to the gain stage is close to the analogue ground level.

This minimises and audible clicks and zipper noise as the gain values are changed or the device

muted. Note that this circuit has no time out so if only DC levels are being applied to the gain stage

input of more than approximately 20mV, then the gain will not be updated. This zero cross function is

enabled when the LZCEN and RZCEN bit is set high during a volume register write. If there is

concern that a DC level may have blocked a volume change (one made with LZCEN or RZCEN set

high) then a subsequent volume write of the same value, but with the LZCEN or RZCEN bit set low

will force a volume update, regardless of the DC level.

LHPOUT and RHPOUT volume and zero-cross setting can be changed independently. Alternatively,

the user can lock the two channels together, allowing both to be updated simultaneously, halving the

number of serial writes required, provided that the same gain is needed for both channels. This is

achieved through writing to the HPBOTH bit of the control register. Setting LRHPBOTH whilst writing

to LHPVOL and LZCEN will simultaneously update the Right Headphone controls similarly. The

corresponding effect on updating RLHPBOTH is also achieved.

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The software control is given in Table 5.

REGISTER

ADDRESS

BIT

6:0

LABEL

DEFAULT

DESCRIPTION

0000010

LHPVOL[6:0]

1111001

( 0dB )

Left Channel Headphone Output

Volume Control

Left

Headphone

Out

1111111 = +6dB

. . 1dB steps down to

0110000 = -73dB

0000000 to 0101111 = MUTE

7

8

LZCEN

0

Left Channel Zero Cross detect

Enable

1 = Enable

0 = Disable

LRHPBOTH

Left to Right Channel Headphone

Volume, Mute and Zero Cross Data

Load Control

1 = Enable Simultaneous Load of

LHPVOL[6:0]

and

LZCEN

to

RHPVOL[6:0] and RZCEN

0 = Disable Simultaneous Load

0000011

6:0

RHPVOL[7:0]

1111001

( 0dB )

Right Channel Headphone Output

Volume Control

Right

Headphone

Out

1111111 = +6dB

. . 1dB steps down to

0110000 = -73dB

0000000 to 0101111 = MUTE

7

8

RZCEN

0

Right Channel Zero Cross Detect

Enable

1 = Enable

0 = Disable

RLHPBOTH

Right to Left Channel Headphone

Volume, Mute and Zero Cross Data

Load Control

1 = Enable Simultaneous Load of

RHPVOL[6:0] and RZCEN to

LHPVOL[6:0] and LZCEN

0 = Disable Simultaneous Load

Table 5 Headphone Output Software Control

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The recommended external components required to complete the application are shown in Figure 11.

HPOUT

C1

AGND

R1

AGND

Figure 11 Headphone Output Application Drawing

Recommended values are C1 = 220uF (10V electrolytic), R1 = 47k

C1 forms a DC blocking capacitor to isolate the dc of the HPOUT from the headphones. R1 form a

pull down resistor to discharge C1 to prevent the voltage at the connection to the headphones from

rising to a level that may damage the headphones.

DEVICE OPERATION

DEVICE RESETTING

The WM8711/L contains a power on reset circuit that resets the internal state of the device to a

known condition. The power on reset is applied as DCVDD powers on and released only after the

voltage level of DCVDD crosses a minimum turn off threshold. If DCVDD later falls below a minimum

turn on threshold voltage then the power on reset is re-applied. The threshold voltages and

associated hysteresis are shown in the Electrical Characteristics table.

The user also has the ability to reset the device to a known state under software control as shown in

the table below.

REGISTER

ADDRESS

BIT

LABEL

RESET

DEFAULT

DESCRIPTION

0001111

Reset Register

8:0

not reset

Reset Register

Writing 00000000 to register resets

device

Table 6 Software Control of Reset

When using the software reset. In 3-wire mode the reset is applied on the rising edge of CSB and

released on the next rising edge of SCLK. In 2-wire mode the reset is applied for the duration of the

ACK signal (approximately 1 SCLK period, refer to Figure 20).

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CLOCKING SCHEMES

In a typical digital audio system there is only one central clock source producing a reference clock to

which all audio data processing is synchronised. This clock is often referred to as the audio system’s

Master Clock. To allow WM8711/L to be used in a centrally clocked system, the WM8711/L is

capable of either generating this system clock itself or receiving it from an external source as will be

discussed.

For applications where it is desirable that the WM8711/L is the system clock source, then clock

generation is achieved through the use of a suitable crystal connected between the XTI/MCLK input

and XTO output pins (see CRYSTAL OSCILLATOR section).

For applications where a component other than the WM8711/L will generate the reference clock, the

external system Master Clock can be applied directly through the XTI/MCLK input pin with no

software configuration necessary. Note that in this situation, the oscillator circuit of the WM8711/L

can be safely powered down to conserve power (see POWER DOWN section)

CORE CLOCK

The WM8711/L DSP core can be clocked either by MCLK or MCLK divided by 2. This is controlled by

software as shown in Table 7 below.

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0001000

6

CLKIDIV2

0

Core Clock divider select

Sampling

Control

1 = Core Clock is MCLK divides by 2

0 = Core Clock is MCLK

Table 7 Software Control of Core Clock

Having a programmable MCLK divider allows the device to be used in applications where higher

frequency master Clocks are available. For example the device can support 512fs master clocks

whilst fundamentally operating in a 256fs mode.

CRYSTAL OSCILLATOR

The WM8711/L includes a crystal oscillator circuit that allows the audio system’s reference clock to

be generated on the device. This is available to the rest of the audio system in buffered form on

CLKOUT. The crystal oscillator is a low radiation type, designed for low EMI. A typical application

circuit is shown Figure 12.

XTI/MCLK

XTO

Cp

DGND

Figure 12 Crystal Oscillator Application Circuit

For crystal frequencies in the 12MHz range, a Cp of 10pF is recommended. For crystal frequencies

in the 18MHz range, 15pF Cp is recommended.

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The WM8711/L crystal oscillator provides an extremely low jitter clock source. Low jitter clocks are a

requirement for high quality audio DACs, regardless of the converter architecture. The WM8711/L

architecture is less susceptible than most converter techniques but still requires clocks with less than

approximately 1ns of jitter to maintain performance. In applications where there is more than one

source for the master clock, it is recommended that the clock is generated by the WM8711/L to

minimise such problems.

CLOCKOUT

The Core Clock is internally buffered and made available externally to the audio system on the

CLKOUT output pin. CLKOUT provides a replication of the Core Clock, but buffered as suitable for

driving external loads.

There is no phase inversion between XTI/MCLK, the Core Clock and CLOCKOUT but there will

inevitably be some delay. The delay will be dependent on the load that CLOCKOUT drives. Refer to

Electrical Characteristics.

CLKOUT can also be divided by 2 under software control, refer to Table 8. Note that if CLKOUT is

not required then the CLKOUT buffer on the WM8711/L can be safely powered down to conserve

power (see POWER DOWN section). If the system architect has the choice between using F_CLKOUT

=

F_MCLKor F_CLKOUT= F_MCLK/2 in the interface, the latter is recommended to conserve power. When the

divide by two is selected CLKOUT changes on the rising edge of MCLK. Please refer to Electrical

Characteristics for timing information.

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0001000

7

CLKODIV2

0

CLKOUT divider select

CLOCKOUT is Core Clock

divides by 2

Sampling

Control

1

=

0 = CLOCKOUT is Core Clock

Table 8 Programming CLKOUT

CLKOUT is disabled and set low whenever the device is in reset.

DIGITAL AUDIO INTERFACES

WM8711/L may be operated in either one of the 4 offered audio interface modes. These are:

•

Right justified

Left justified

I²S

DSP mode

All four of these modes are MSB first and operate with data 16 to 32 bits, except in right justified

mode where 32 bit data is not supported.

The digital audio interface receives the digital audio data for the internal DAC digital filters on the

DACDAT input. DACDAT is the formatted digital audio data stream output to the DAC digital filters

with left and right channels multiplexed together. DACLRC is an alignment clock that controls

whether Left or Right channel data is present on DATDAT. DACDAT and DACLRC are synchronous

with the BCLK signal with each data bit transition signified by a BCLK transition. DACDAT is always

an input. BCLK and DACLRC are either outputs or inputs depending whether the device is in master

or slave mode. Refer to the MASTER/SLAVE OPERATION section

There are four digital audio interface formats accommodated by the WM8711/L. These are shown in

the figures below. Refer to the Electrical Characteristic section for timing information.

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Left Justified mode is where the MSB is available on the first rising edge of BCLK following a

DACLRC transition.

1/fs

LEFT CHANNEL

RIGHT CHANNEL

DACLRC

BCLK

DACDAT

1

2

3

n

n-2 n-1

1

2

3

n

n-2 n-1

MSB

LSB

MSB

LSB

Figure 13 Left Justified Mode

I²S mode is where the MSB is available on the 2nd rising edge of BCLK following a DACLRC

transition.

1/fs

LEFT CHANNEL

RIGHT CHANNEL

DACLRC

BCLK

1 BCLK

DACDAT

1

2

3

n

1

2

3

n

n-2 n-1

LSB

MSB

Figure 14 I²S Mode

Right Justified mode is where the LSB is available on the rising edge of BCLK preceding a DACLRC

transition, yet MSB is still transmitted first.

1/fs

LEFT CHANNEL

RIGHT CHANNEL

DACLRC

BCLK

DACDAT

1

2

3

n

1

2

3

n

n-2 n-1

MSB

LSB

MSB

LSB

Figure 15 Right Justified Mode

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DSP mode is where the left channel MSB is available on either the 1^stor 2^ndrising edge of BCLK

(selectable by LRP) following an DACLRC transition high. Right channel data immediately follows

left channel data.

1/fs

1 BCLK

DACLRC

BCLK

RIGHT CHANNEL

LEFT CHANNEL

DACDAT

1

2

3

n

1

2

3

n

n-2 n-1

MSB

LSB

Input Word Length (IWL)

Note: Input word length is defined by the IWL register, LRP = 1

Figure 16 DSP Mode

In all modes DACLRC must always change on the falling edge of BCLK, refer to Figures 13,14,15

and 16. Operating the digital audio interface in DSP mode allows ease of use for supporting the

various sample rates and word lengths. The only requirement is that all data is transferred within the

correct number of BCLK cycles to suit the chosen word length.

In order for the digital audio interface to offer similar support in the three other modes (Left Justified,

I²S and Right Justified), the DACLRC and BCLK frequencies, continuity and mark-space ratios need

more careful consideration.

In Slave mode, DACLRC inputs are not required to have a 50:50 mark-space ratio. BCLK input need

not be continuous. It is however required that there are sufficient BCLK cycles for each DACLRC

transition to clock the chosen data word length. The non-50:50 requirement on the LRC is of use in

some situations such as with a USB 12MHZ clock. Here simply dividing down a 12MHz clock within

the DSP to generate LRC and BCLK will not generate the appropriate DACLRC since it will no longer

change on the falling edge of BCLK. For example, with 12MHz/32k fs mode there are 375 MCLK per

LRC. In these situations DACLRC can be made non 50:50.

In Master mode, DACLRC will be output with a 50:50 mark-space ratio with BCLK output at 64fs x

Base Frequency (ie 48kHz). The exception is in 96/88.2k mode where BCLK is MCLK and in USB

mode where BCLK is always 12MHz. So for example in 12MHz/32k fs mode there are 375 master

clocks per LRC period. Therefore the DACLRC output will have a mark space ratio of 187:188.

The DAC digital audio interface modes are software configurable as indicated in Table 8. Note that

dynamically changing the software format may result in erroneous operation of the interfaces and is

therefore not recommended.

The length of the digital audio data is programmable at 16/20/24 or 32 bits. Refer to the software

control table below. The data is signed 2’s complement. The DAC digital filters process data using 24

bits. If the DAC is programmed to receive 16 or 20 bit data, the WM8711/L packs the LSBs with

zeros. If the DAC is programmed to receive 32 bit data, then it strips the LSBs.

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The DAC outputs can be swapped under software control using LRP and LRSWAP as shown in

Table 9. Stereo samples are normally generated as a Left/Right sampled pair. LRSWAP reverses the

order so that a Left sample goes to the right DAC output and a Right sample goes to the left DAC

output. LRP swaps the phasing so that a Right/Left sampled pair is expected and preserves the

correct channel phase difference, except in DSP mode, where LRP controls the positioning of the

MSB relative to the rising edge of DACLRC.

To accommodate system timing requirements the interpretation of BCLK maybe inverted, this is

controlled via the software shown in Table 9. This is especially appropriate for DSP mode.

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0000111

Digital

Interface Format

1:0

FORMAT[1:0]

10

Audio Data Format Select

Audio

11 = DSP Mode, frame sync + 2 data

packed words

10

=

I²S Format, MSB-First left-1

justified

01 = MSB-First, left justified

00 = MSB-First, right justified

3:2

IWL[1:0]

LRP

10

0

Input Audio Data Bit Length Select

11 = 32 bits

10 = 24 bits

01 = 20 bits

00 = 16 bits

4

DACLRC phase control (in left, right

or I²S modes)

1 = Right Channel DAC data when

DACLRC high

0 = Right Channel DAC data when

DACLRC low

(opposite phasing in I²S mode)

or

DSP mode A/B select ( in DSP mode

only)

1 = MSB is available on 2^ndBCLK

rising edge after DACLRC rising

edge

0 = MSB is available on 1st BCLK

rising edge after DACLRC rising

edge

5

6

7

LRSWAP

MS

0

DAC Left Right Clock Swap

1 = Right Channel DAC Data Left

0 = Right Channel DAC Data Right

Master Slave Mode Control

1 = Enable Master Mode

0 = Enable Slave Mode

BCLKINV

Bit Clock Invert

1 = Invert BCLK

0 = Don’t invert BCLK

Table 9 Digital Audio Interface Control

Note: If right justified 32 bit mode is selected then the WM8711/L defaults to 24 bits.

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MASTER AND SLAVE MODE OPERATION

The WM8711/L can be configured as either a master or slave mode device. As a master mode

device the WM8711/L controls sequencing of the data and clocks on the digital audio interface. As a

slave device the WM8711/L responds with data to the clocks it receives over the digital audio

interface. The mode is set with the MS bit of the control register as shown in Table 10.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Master Slave Mode Control

1 = Enable Master Mode

0 = Enable Slave Mode

0000111

6

MS

0

Digital Audio Interface

Format

Table 10 Programming Master/Slave Modes

As a master mode device the WM8711/L controls the sequencing of data transfer (DACDAT) and

output of clocks (BCLK, DACLRC) over the digital audio interface. It uses the timing generated from

the MCLK input as the reference for the clock and data transitions. This is illustrated in Figure 17.

DACDAT is always an input to the WM8711/L independent of master or slave mode.

BCLK

DSP

DECODER

WM8711

DAC

DACLRC

DACDAT

Figure 17 Master Mode

As a slave device the WM8711/L sequences the data transfer (DACDAT) over the digital audio

interface in response to the external applied clocks (BCLK, DACLRC). This is illustrated in Figure 18.

BCLK

DSP

DECODER

WM8711

DAC

DACLRC

DACDAT

Figure 18 Slave Mode

Note that the WM8711/L relies on controlled phase relationships between audio interface BCLK,

DACLRC and the master MCLK or CLKOUT. To avoid any timing hazards, refer to the timing section

for detailed information.

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AUDIO DATA SAMPLING RATES

The WM8711/L provides for two modes of operation (normal and USB) to generate the required DAC

sampling rates. Normal and USB modes are programmed under software control according to the

table below.

In Normal mode, the user controls the sample rate by using an appropriate MCLK frequency and the

sample rate control register setting. The WM8711/L can support sample rates from 8ks/s up to

96ks/s.

In USB mode, the user must use a fixed MLCK frequency of 12MHz to generate sample rates from

8ks/s to 96ks/s. It is called USB mode since the common USB (Universal Serial Bus) clock is at

12MHz and the WM8711/L can be directly used within such systems. WM8711/L can generate all the

normal audio sample rates from this one Master Clock frequency, removing the need for different

master clocks or PLL circuits.

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0001000

0

USB/

0

Mode Select

NORMAL

BOSR

Sampling

Control

1 = USB mode (250/272fs)

0 = Normal mode (256/384fs)

Base Over-Sampling Rate

1

0

USB Mode

0 = 250fs

1 = 272fs

Normal Mode

0 = 256fs

1 = 384fs

5:2

SR[3:0]

0000

DAC sample rate control;

See USB Mode and Normal Mode

Sample Rate sections for operation

Table 11 Sample Rate Control

N ORMAL MODE SAMPLE RATES

In normal mode MCLK is set up according to the desired sample rates of the DAC. For DAC

sampling rates of 8, 32, 48 or 96kHz, MCLK frequencies of either 12.288MHz (256fs) or 18.432MHz

(384fs) can be used. DAC sampling rates of 8, 44.1 or 88.2kHz from MCLK frequencies of either

11.2896MHz (256fs) or 16.9344MHz (384fs) can be used.

The table below should be used to set up the device to work with the various sample rate

combinations. Refer to Digital Filter Characteristics section for an explanation of the different filter

types.

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SAMPLING RATE

DAC

MCLK

FREQUENCY

SAMPLE

RATE

REGISTER SETTINGS

DIGITAL

FILTER

TYPE

kHz

MHz

BOSR

SR3

0

SR2

0

SR1

0

SR0

0

48

12.288

18.432

12.288

18.432

12.288

18.432

12.288

18.432

11.2896

16.9344

11.2896

16.9344

11.2896

16.9344

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

1

2

0

8

32

0

1

0

1

0

1

0

1

0

96

0

1

0

1

44.1

1

0

1

0

8

1

0

1

(Note 1)

1

0

1

88.2

1

Table 12 Normal Mode Sample Rate Look-up Table

Notes:

1. 8k not exact, actual = 8.018kHz

2. All other combinations of BOSR and SR[3:0] that are not in the truth table are invalid

The BOSR bit represents the base over-sampling rate. This is the rate that the WM8711/L digital

signal processing is carried out at. In Normal mode, with BOSR = 0, the base over-sampling rate is at

256fs, with BOSR = 1, the base over-sampling rate is at 384fs. This can be used to determine the

actual audio data rate required by the DAC.

The exact sample rates achieved are defined by the relationships in Table 13 below.

TARGET

ACTUAL SAMPLING RATE

SAMPLING

RATE

BOSR=0

(256FS)

BOSR=1

(384FS)

MCLK=12.288

MCLK=11.2896

kHz

MCLK=18.432

kHz

MCLK=16.9344

kHz

8

kHz

8.018

8

8.018

8

12.288MHz/256 x 1/6

32

11.2896MHz/256 x 2/11

not available

18.432MHz/384 x 1/6

32

16.9344MHz/384 x 2/11

not available

32

12.288MHz/256 x 2/3

not available

18.432MHz/384x 2/3

not available

44.1

48

44.1

11.2896MHz/256

not available

16.9344MHz /384

not available

48

12.288MHz/256

not available

18.432MHz/384

not available

88.2

96

88.2

11.2896MHz/256 x 2

16.9344MHz /384 x 2

96

not available

96

not available

12.288MHz/256 x 2

18.432MHz/384 x 2

Table 13 Normal Mode Actual Sample Rates

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128/192FS NORMAL MODE

The Normal Mode sample rates are designed for standard 256fs and 384fs MCLK rates. However the

WM8711/L is also capable of being clocked from a 128/192fs MCLK for application over limited

sampling rates as shown in the table below.

SAMPLING RATE

DAC

MCLK

FREQUENCY

SAMPLE

RATE

REGISTER SETTINGS

DIGITAL

FILTER

TYPE

kHz

MHz

6.144

9.216

5.6448

8.4672

BOSR

SR3

SR2

SR1

SR0

48

0

1

0

1

0

1

2

44.1

Table 14 128/192fs Normal Mode Sample Rate Look-up Table

512/768FS NORMAL MODE

512fs and 768fs MCLK rates can be accommodated by using the CLKIDIV2 bit. The core clock to

the DSP will be divided by 2 so an external 512/768 MCLK will become 256/384fs internally and the

device otherwise operates as in Table 10 but with MCLK at twice the specified rate.

USB MODE SAMPLE RATES

In USB mode the MCLK input is 12MHz only.

SAMPLING RATE

DAC

MCLK

FREQUENCY

SAMPLE

RATE

REGISTER SETTINGS

DIGITAL

FILTER

TYPE

kHz

MHz

BOSR

SR3

SR2

SR1

SR0

48

12.000

0

1

0

1

0

3

2

44.1

12.000

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

(Note 2)

8

(Note 1)

32

96

88.2

(Note 3)

Table 15 USB Mode Sample Rate Look-Up Table

Notes:

1. 8k not exact, actual = 8.021kHz

2. 44.1k not exact, actual = 44.118kHz

3. 88.1k not exact, actual = 88.235kHz

4. All other combinations of BOSR and SR[3:0] that are not in the truth table are invalid

The BOSR bit represents the base over-sampling rate. This is the rate that the WM8711/L digital

signal processing is carried out at and the sampling rate will always be a sub-multiple of this. In USB

mode, with BOSR = 0, the base over-sampling rate is defined at 250Fs, with BOSR = 1, the base

over-sampling rate is defined at 272Fs. This can be used to determine the actual audio sampling rate

required by the DAC.

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The exact sample rates supported for all combinations are defined by the relationships in Table 16

below.

TARGET

ACTUAL SAMPLING RATE

SAMPLING

RATE

BOSR=0

BOSR=1

(272FS)

kHz

( 250FS)

kHz

8

8.021

12MHz/(250 x 48/8)

32

12MHz/(272 x 11/2)

not available

32

12MHz/(250 x 48/32)

not available

44.1

48

44.117

12MHz/272

not available

48

12MHz/250

not available

88.2

96

88.235

12MHz/136

not available

96

12MHz/125

Table 16 USB Mode Actual Sample Rates

ACTIVATING DSP AND DIGITAL AUDIO INTERFACE

To prevent any communication problems from arising across the Digital Audio Interface is disabled

(tristate with weak 100k pulldown) at power on. Once the Audio Interface and the Sampling Control

has been programmed it is activated by setting the ACTIVE bit under Software Control.

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0001001

Active Control

0

ACTIVE

0

Activate Interface

1 = Active

0 = Inactive

Table 17 Activating DSP and Digital Audio Interface

It is recommended that between changing any content of Digital Audio Interface or Sampling Control

Register that the active bit is reset then set.

SOFTWARE CONTROL INTERFACE

The software control interface may be operated using either a 3-wire or 2-wire MPU interface.

Selection of interface format is achieved by setting the state of the MODE pin.

In 3-wire mode, SDIN is used for the program data, SCLK is used to clock in the program data and

CSB is used to latch in the program data. In 2-wire mode, SDIN is used for serial data and SCLK is

used for the serial clock. In 2-wire mode, the state of CSB pin allows the user to select one of two

addresses.

SELECTIONOF SERIAL CONTROL MODE

The serial control interface may be selected to operate in either 2 or 3-wire modes. This is achieved

by setting the state of the MODE pin.

MODE

INTERFACE

FORMAT

0

1

2 wire

3 wire

Table 18 Control Interface Mode Selection

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3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE

The WM8711/L can be controlled using a 3-wire serial interface. SDIN is used for the program data,

SCLK is used to clock in the program data and CSB is use to latch in the program data. The 3-wire

interface protocol is shown in Figure 19.

CSB

SCLK

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

SDIN

Figure 19 3-Wire Serial Interface

Notes:

1. B[15:9] are Control Address Bits

2. B[8:0] are Control Data Bits

3. CSB is edge sensitive not level sensitive. The data is latched on the rising edge of CSB.

2-WIRE SERIAL CONTROL MODE

The WM8711/L supports a 2-wire MPU serial interface. The device operates as a slave device only.

The WM8711/L has one of two slave addresses that are selected by setting the state of pin 22

(SSOP) / 26 (QFN), (CSB).

ACK

DATA B15-8

R ADDR

R/W

DATA B7-0

SDIN

SCLK

START

STOP

Figure 20 2-Wire Serial Interface

Notes:

1. B[15:9] are Control Address Bits

2. B[8:0] are Control Data Bits

CSB STATE

ADDRESS

0

1

0011010

0011011

Table 19 2-Wire MPU Interface Address Selection

To control the WM8711/L on the 2-wire bus the master control device must initiate a data transfer by

establishing a start condition, defined by a high to low transition on SDIN while SCLK remains high.

This indicates that an address and data transfer will follow. All peripherals on the 2-wire bus respond

to the start condition and shift in the next eight bits (7-bit address + R/Wbit). The transfer is MSB

first. The 7-bit address consists of a 6-bit base address + a single programmable bit to select one of

two available addresses for this device (see Table 19). If the correct address is received and the R/W

bit is ‘0’, indicating a write, then the WM8711/L will respond by pulling SDIN low on the next clock

pulse (ACK). The WM8711/L is a write only device and will only respond to the R/W bit indicating a

write. If the address is not recognised the device will return to the idle condition and wait for a new

start condition and valid address.

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Once the WM8711/L has acknowledged a correct address, the controller will send eight data bits

(bits B[15]-B[8]). WM8711/L will then acknowledge the sent data by pulling SDIN low for one clock

pulse. The controller will then send the remaining eight data bits (bits B[7]-B[0]) and the WM8711/L

will then acknowledge again by pulling SDIN low.

A stop condition is defined when there is a low to high transition on SDIN while SCLK is high. If a

start or stop condition is detected out of sequence at any point in the data transfer then the device

will jump to the idle condition.

After receiving a complete address and data sequence the WM8711/L returns to the idle state and

waits for another start condition. Each write to a register requires the complete sequence of start

condition, device address and R/Wbit followed by the 16 register address and data bits.

POWER DOWNMODES

The WM8711/L contains power conservation modes in which various circuit blocks may be safely

powered down in order to conserve power. This is software programmable as shown in the table

below.

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0000110

0

3

4

5

6

7

LINEINPD

1

Line Input Power Down

1 = Enable Power Down

0 = Disable Power Down

DAC Power Down

Power

Control

Down

DACPD

1

0

1

1 = Enable Power Down

0 = Disable Power Down

Line Output Power Down

1 = Enable Power Down

0 = Disable Power Down

Oscillator Power Down

1 = Enable Power Down

0 = Disable Power Down

CLKOUT Power Down

1 = Enable Power Down

0 = Disable Power Down

Power Off Device

OUTPD

OSCPD

CLKOUTPD

POWEROFF

1 = Device Power Off

0 = Device Power On

Table 20 Power Conservation Modes Software Control

The power down control can be used to either a) permanently disable functions when not required in

certain applications or b) to dynamically power up and down functions depending on the operating

mode, e.g.: during playback or record. Please follow the special instructions below if dynamic

implementations are being used.

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DACPD: Powers down the DAC and DAC Digital Filters. If this is done dynamically then audible pops

will result unless the following guidelines are followed. In order to prevent pops, the DAC should first

be soft-muted (DACMU), the output should then be de-selected from the line and headphone output

(DACSEL), then the DAC powered down (DACPD). This is of use when the device enters Pause or

Stop modes. During DACPD the digital audio interface is remains active.

OUTPD: Powers down the Line and Headphone Outputs. If this is done dynamically then audible

pops may result unless the DAC is first soft-muted (DACMU). This is of use when the device enters

Record, Pause or Stop modes.

LINEINPD: Simultaneously powers down both the Line Inputs. This can be done dynamically without

any audible effects on the Line Outputs. For pure DAC playback, set LINEINPD = 1 to save power.

The device can be put into a standby mode (STANDBY) by powering down all the audio circuitry

under software control as shown in Table 20.

DESCRIPTION

0

1

0

1

STANDBY, but with Crystal Oscillator OS and

CLKOUT available

STANDBY, but with Crystal Oscillator OS

available, CLKOUT not-available

STANDBY, Crystal oscillator and CLKOUT not-

available.

Table 21 Standby Mode

In STANDBY mode the Control Interface, a small portion of the digital and areas of the analogue

circuitry remain active. The active analogue includes the analogue VMID reference so that the

analogue line outputs and headphone outputs remain biased to VMID. This reduces any audible

effects caused by DC glitches when entering or leaving STANDBY mode.

The device can be powered off by writing to the POWEROFF bit of the Power Down register. In

POWEROFF mode the Control Interface and a small portion of the digital remain active. The

analogue VMID reference is disabled. Refer to Table 22.

DESCRIPTION

1

0

1

0

1

X

1

POWEROFF, but with Crystal Oscillator OS and

CLKOUT available

POWEROFF, but with Crystal Oscillator OS

available, CLKOUT not-available

POWEROFF, Crystal oscillator and CLKOUT

not-available.

Table 22 Poweroff Mode

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REGISTER MAP

Production Data

The complete register map is shown in Table 24. The detailed description can be found in the

relevant text of the device description. There are 8 registers with 9 bits per register. These can be

controlled using either the 2 wire or 3 wire MPU interface.

REGISTER

B

9

B8

B7

B6

B5

B4

B3

B2

B1

B0

15 14 13 12 11 10

LRHP

BOTH

RLHP

BOTH

0

R2 (04h)

R3 (06h)

0

1

0

1

LZCEN

RZCEN

LHPVOL

RHPVOL

R4 (08h)

R5 (0Ah)

0

1

0

1

0

DAC SEL BYPASS

DAC MU

0

1

0

DEEMPH

POWER

OFF

BCLK

INV

CLK

OUTPD

R6 (0Ch)

R7 (0Eh)

R8 (10h)

0

1

0

1

0

1

0

OSCPD OUTPD DACPD

1

LINEINPD

MS

LR SWAP LRP

IWL

FORMAT

CLK0

DIV2

0

CLKI

DIV2

0

USB/

NORM

ACTIVE

0

SR

BOSR

0

R9 (12h)

R15(1Eh)

0

1

0

1

0

1

0

RESET

ADDRESS

DATA

Table 23 Mapping of Program Registers

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0000010

6:0

LHPVOL

[6:0]

1111001

( 0dB )

Left Channel Headphone Output

Volume Control

Left Headphone

Out

1111111 = +6dB

. . 1dB steps down to

0110000 = -73dB

0000000 to 0101111 = MUTE

Left Channel Zero Cross detect Enable

1 = Enable

7

8

LZCEN

0

0 = Disable

LRHPBOTH

Left to Right Channel Headphone

Volume, Mute and Zero Cross Data

Load Control

1

=

Enable Simultaneous Load of

LHPVOL[6:0] and LZCEN to

RHPVOL[6:0] and RZCEN

0 = Disable Simultaneous Load

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DESCRIPTION

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

0000011

6:0

RHPVOL

[6:0]

1111001

( 0dB )

Right Channel Headphone Output

Volume Control

Right

Headphone Out

1111111 = +6dB

. . 1dB steps down to

0110000 = -73dB

0000000 to 0101111 = MUTE

7

8

RZCEN

0

Right Channel Zero Cross detect

Enable

1 = Enable

0 = Disable

RLHPBOTH

Right to Left Channel Headphone

Volume, Mute and Zero Cross Data

Load Control

1

=

Enable Simultaneous Load of

RHPVOL[60] and RZCEN to

LHPVOL[6:0] and LZCEN

0 = Disable Simultaneous Load

Bypass Switch

0000100

3

BYPASS

1

Audio

Path

1 = Enable Bypass

Control

0 = Disable Bypass

DAC Select (Analogue)

1 =Select DAC

4

DACSEL

0

0 = Don’t select DAC

De-emphasis Control (Digital)

11 = 48kHz

0000101

Digital

2:1

DEEMP[1:0]

00

Audio

Path Control

10 = 44.1kHz

01 = 32kHz

00 = Disable

3

0

3

4

5

6

7

DACMU

1

0

1

DAC Soft Mute Control (Digital)

1 = Enable soft mute

0 = Disable soft mute

Line Input Power Down

1 = Enable Power Down

0 = Disable Power Down

DAC Power Down

0000110

LINEINPD

DACPD

Power

Control

Down

1 = Enable Power Down

0 = Disable Power Down

Outputs Power Down

1 = Enable Power Down

0 = Disable Power Down

Oscillator Power Down

1 = Enable Power Down

0 = Disable Power Down

CLKOUT Power Down

1 = Enable Power Down

0 = Disable Power Down

POWEROFF mode

OUTPD

OSCPD

CLKOUTPD

POWEROFF

1 = Enable POWEROFF

0 = Disable POW EROFF

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Production Data

DESCRIPTION

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

0000111

Digital

Interface Format

1:0

FORMAT[1:0]

10

Audio Data Format Select

Audio

11 = DSP Mode, frame sync + 2 data

packed words

10

= I2S Format, MSB-First left-1

justified

01 = MSB-First, left justified

00 = MSB-First, right justified

Input Audio Data Bit Length Select

11 = 32 bits

3:2

IWL[1:0]

LRP

10

0

10 = 24 bits

01 = 20 bits

00 = 16 bits

4

DACLRC phase control (in left, right or

I²S modes)

1 = Right Channel DAC data when

DACLRC high

0 = Right Channel DAC data when

DACLRC low

(opposite phasing in I²S mode)

or

DSP mode A/B select ( in DSP mode

only)

1 = MSB is available on 2^ndBCLK

rising edge after DACLRC rising edge

0 = MSB is available on 1st BCLK

rising edge after DACLRC rising edge

5

6

7

LRSWAP

MS

0

DAC Left Right Clock Swap

1 = Right Channel DAC Data Left

0 = Right Channel DAC Data Right

Master Slave Mode Control

1 = Enable Master Mode

0 = Enable Slave Mode

Bit Clock Invert

BCLKINV

1 = Invert BCLK

0 = Don’t invert BCLK

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DESCRIPTION

Mode Select

REGISTER

ADDRESS

BIT

LABEL

USB/

DEFAULT

0001000

0

NORMAL

Sampling

Control

1 = USB mode (250/272fs)

0 = Normal mode (256/384fs)

Base Over-Sampling Rate

USB Mode

1

BOSR

0

0 = 250fs

1 = 272fs

5:2

SR[3:0]

0000

DAC sample rate Normal Mode

control;

0 = 256fs

1 = 384fs

See USB Mode

and

Mode

Normal

Sample

Rate sections for

operation

6

CLKIDIV2

CLKODIV2

ACTIVE

0

Core Clock divider select

1 = Core Clock is MCLK divide by 2

0 = Core Clock is MCLK

CLKOUT divider select

1 = CLOCKOUT is MCLK divide by 2

0 = CLOCKOUT is MCLK

Activate Interface

7

0

0001001

0

Active Control

1 = Active

0 = Inactive

0001111

8:0

RESET

not reset

Reset Register

Writing 00000000 to register resets

device

Table 24 Register Map Description

Note:

All other bits not explicitly defined in the register table should be set to zero unless specified

otherwise.

DIGITAL FILTER CHARACTERISTICS

The DAC employ different digital filters. There are 4 types of digital filter, called Type 0, 1, 2 and 3.

The performance of Types 0 and 1 is listed in the table below, the responses of all filters is shown in

the proceeding pages.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

0.416fs

+/-0.03

UNIT

DAC Filter Type 0 (USB mode, 250fs operation)

Passband

+/- 0.03dB

-6dB

0

0.5fs

Passband Ripple

Stopband

dB

0.584fs

-50

Stopband Attenuation

f > 0.584fs

DAC Filter Type 1 (USB mode, 272fs or Normal mode operation)

Passband

+/- 0.03dB

-6dB

0

0.4535fs

+/- 0.03

0.5fs

Passband Ripple

Stopband

dB

0.5465fs

-50

Stopband Attenuation

f > 0.5465fs

Table 25 Digital Filter Characteristics

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DAC FILTER RESPONSES

0.04

0.03

0.02

0.01

0

-20

-40

-60

-0.01

-0.02

-0.03

-0.04

-80

-100

0

0.5

1

1.5

2

2.5

3

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.2

0.45

0.5

Frequency (Fs)

Figure 21 DAC Digital Filter Frequency Response–Type 0

Figure 22 DAC Digital Filter Ripple–Type 0

0.04

0.03

0.02

0.01

0

-20

-40

-60

-0.01

-0.02

-0.03

-0.04

-80

-100

0

0.5

1

1.5

2

2.5

3

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.45

0.5

Frequency (Fs)

Figure 23 DAC Digital Filter Frequency Response–Type 1

Figure 24 DAC Digital Filter Ripple–Type 1

0.02

0.01

0

-20

-0.01

-0.02

-0.03

-0.04

-0.05

-0.06

-40

-60

-80

-100

0

0.5

1

1.5

2

2.5

3

0

0.05

0.1

0.15

0.25

Frequency (Fs)

Figure 25 DAC Digital Filter Frequency Response–Type 2

Figure 26 DAC Digital Filter Ripple–Type 2

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Production Data

0

0.05

0

-20

-40

-0.05

-0.1

-0.15

-0.2

-0.25

-60

-80

-100

0

0.5

1

1.5

2

2.5

3

0

0.05

0.1

0.15

0.2

0.25

Frequency (Fs)

Figure 27 DAC Digital Filter Frequency Response–Type 3

Figure 28 DAC Digital Filter Ripple–Type 3

DIGITAL DE-EMPHASIS CHARACTERISTICS

0

0.4

0.3

0.2

0.1

0

-2

-4

-6

-0.1

-0.2

-0.3

-0.4

-8

-10

0

2000

4000

6000

8000

10000 12000 14000 16000

0

2000

4000

6000

8000

10000 12000 14000 16000

Frequency (Fs)

Figure 29 De-Emphasis Frequency Response (32kHz)

Figure 30 De-Emphasis Error (32kHz)

0

-2

0.4

0.3

0.2

0.1

0

-4

-6

-0.1

-0.2

-0.3

-0.4

-8

-10

0

5000

10000

Frequency (Fs)

15000

20000

0

5000

10000

Frequency (Fs)

15000

20000

Figure 31 De-Emphasis Frequency Response (44.1kHz)

Figure 32 De-Emphasis Error (44.1kHz)

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0

0.4

0.3

0.2

0.1

0

-2

-4

-6

-0.1

-0.2

-0.3

-0.4

-8

-10

0

5000

10000

15000

20000

0

5000

10000

15000

20000

Frequency (Fs)

Figure 33 De-Emphasis Frequency Response (48kHz)

Figure 34 De-Emphasis Error (48kHz)

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RECOMMENDED EXTERNAL COMPONENTS

3.3V

+

1

14

15

DBVDD

DGND

+

AVDD

AGND

10µ

µ

F

0.1 F

µ

0.1 F

µ

10 F

28

µ

10 F

µ

0.1 F

3.3V

1.5V - 3.3V

+

8

27

HPVDD

HPGND

+

DCVDD

LLINEIN

µ

10 F

0.1 F

+

Ω

5.6k

20

11

µ

1 F

+

Ω

100

12

VREF

LOUT

ROUT

8711L Only

+

Ω

5.6k

19

µ

1 F

Ω

47k

RLINEIN

µ

1 F

+

13

Ω

100

VREF

WM8711

DAC

µ

1 F

Ω

47k

5

4

3

DACLRC

DACDAT

BCLK

Audio Serial Data

I/F

+

9

LHPOUT

µ

Ω

47k

220 F

3.3V

3-wire Interface

2-wire Interface

Ω

10k

+

21

22

10

MODE

CSB

SDIN

SCLK

DGND

RHPOUT

3-wire or 2-wire

MPU Interface

23

24

µ

Ω

47k

220 F

2

CLKOUT

VMID

Ω

100

16

+

µ

0.1 F

µ

10 F

XTI/MCLK XTO

26

25

15pF

Note

1. Where possible, it is recommended that NPO or COG type capacitors should be used for best performance.

2. The recommended external components are the same for both the QFN and SSOP packages.

Figure 35 External Components Diagram

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Production Data

PACKAGE DIMENSIONS - SSOP

DS: 28 PINSSOP (10.2 x 5.3 x 1.75 mm)

DM007.D

b

e

28

15

E1

E

GAUGE

PLANE

Θ

14

1

D

0.25

L

c

A1

L₁

A A2

-C-

0.10 C

SEATING PLANE

Dimensions

(mm)

Symbols

OMMINN MAX

A

A₁

A₂

b

c

D

e

E

E₁

L

-----

0.05

1.65

0.22

0.09

9.90

-----

1.75

0.30

2.0

0.25

1.85

0.38

0.25

10.50

-----

10.20

0.65 BSC

7.80

7.40

5.00

0.55

8.20

5.60

0.95

5.30

0.75

L₁

θ

0.125 REF

0^o

4^o

8^o

JEDEC.95, MO-150

REF:

NOTES:

A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.

B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.

C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM.

D. MEETS JEDEC.95 MO-150, VARIATION= AH. REFER TO THIS SPECIFICATIONFOR FURTHER DETAILS.

PD Rev 3.1 December 2002

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Production Data

PACKAGE DIMENSIONS – QFN

FL: 28 PINQFNPLASTIC PACKAGE 5

X 5 X 0.9 mm BODY, 0.50 mm LEAD PITCH

DM023.D

TOP VIEW

SEE DETAIL A

CORNER

TIE BAR

D2

B

D2/2

27 28

D

5

22

INDEX AREA

(D/2 X E/2)

L

21

1

2

E2/2

A

E2

E

15

7

SEE DETAIL B

aaa

C

14 13

e

8

2 X

b

M

ccc

C

A

B

aaa

C

DETAIL A

CORNER

TIE BAR

ccc

C

1

(A3)

1

A

28x b

5

M

A

B

0.08

C

bbb

C

A1

SEATING PLANE

C

DETAIL B

EXPOSED

CENTRE

PAD

1

L1

Dimensions (mm)

OMMINN MAX OTE

Symbols

N

A

A1

A3

b

D

D2

E

E2

e

L

L1

R

K

0.85

0

0.90

0.02

1.00

0.05

0.2 REF

0.23

5.00 BSC

3.3

5.00 BSC

3.3

0.5 BSC

0.4

0.18

3.2

0.30

3.4

1

2

3.2

3.4

0.35

0.45

0.1

1

b(min)/2

0.20

Tolerances of Form and Position

aaa

bbb

ccc

0.15

0.10

JEDEC, MO-220, VARIATION VKKD-2

REF:

NOTES:

1. DIMENSION b APPLIED TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. DIMENSION L1 REPRESENTS TERMINAL PULL BACK FROM

PACKAGE SIDE WALL. MAXIMUM OF 0.1mm IS ACCEPTABLE. WHERE TERMINAL PULL BACK EXISTS, ONLY UPPER HALF OF LEAD IS VISIBLE ON PACKAGE SIDE WALL DUE TO HALF

ETCHING OF LEADFRAME.

2. FALLS WITHINJEDEC, MO-220 WITH THE EXCEPTIONOF D2, E2:

D2,E2: LARGER PAD SIZE CHOSENWHICH IS JUST OUTSIDE JEDEC SPECIFICATION

3. ALL DIMENSIONS ARE IN MILLIMETRES

4. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.

5. SHAPE AND SIZE OF CORNER TIE BAR MAY VARY WITH PACKAGE TERMINAL COUNT. CORNER TIE BAR IS CONNECTED TO EXPOSED PAD INTERNALLY

PD Rev 3.1 December 2002

41

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WM8711 / WM8711L

IMPORTANT NOTICE

Production Data

Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or

service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing

orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale

supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation

of liability.

WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM’s

standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support

this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by

government requirements.

In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used

by the customer to minimise inherent or procedural hazards.

WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that

any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual

property right of WM covering or relating to any combination, machine, or process in which such products or services might

be or are used. WM’s publication of information regarding any third party’s products or services does not constitute WM’s

approval, license, warranty or endorsement thereof.

Reproduction of information from the WM web site or datasheets is permissable only if reproduction is without alteration

and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this

information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive

business practice, and WM is not responsible nor liable for any such use.

Resale of WM’s products or services with statements different from or beyond the parameters stated by WM for that

product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and

deceptive business practice, and WM is not responsible nor liable for any such use.

ADDRESS:

Wolfson Microelectronics plc

20 Bernard Terrace

Edinburgh

EH8 9NX

United Kingdom

Tel :: +44 (0)131 272 7000

Fax :: +44 (0)131 272 7001

Email :: sales@wolfsonmicro.com

PD Rev 3.1 December 2002

42

w

厂商	型号	描述	页数
WOLFSON	XWM8146CDW/V	12位（8 + 4位）的线性传感器图像处理器[ 12-bit(8+4-bit) Linear Sensor Image Processor ]	17 页
WOLFSON	XWM8148CFT/V	12位/ 12MSPS CCD / CIS模拟前端/数字转换器[ 12-bit/12MSPS CCD/CIS Analogue Front End/Digitiser ]	43 页
WOLFSON	XWM8170CFT/V	3.3V集成信号处理器的面阵CCD的[ 3.3V Integrated Signal Processor for Area Array CCDs ]	41 页
WOLFSON	XWM8181CDW	12位2MSPS串行输出CIS / CCD数字转换器[ 12-bit 2MSPS Serial Output CIS/CCD Digitiser ]	14 页
WOLFSON	XWM8190CDW/V	（ 8 + 6 ）位输出14位CIS / CCD AFE /数字转换器[ (8+6) Bit Output 14-bit CIS/CCD AFE/Digitiser ]	25 页
WOLFSON	XWM8191CFT	14位6MSPS CIS / CCD模拟前端/数字转换器[ 14-bit 6MSPS CIS/CCD Analogue Front End/Digitiser ]	27 页
WOLFSON	XWM8192	（88）位输出16位CIS / CCD AFE /数字转换器[ (88) Bit Output 16-bit CIS/CCD AFE/Digitiser ]	24 页
WOLFSON	XWM8192CDW/V	（88）位输出16位CIS / CCD AFE /数字转换器[ (88) Bit Output 16-bit CIS/CCD AFE/Digitiser ]	24 页
CIRRUS	XWM8194CDW/V	[ Analog Circuit, 1 Func, CMOS, PDSO28, 7.50 MM, 1.27 MM PITCH, MS-013AE, SOIC-28 ]	27 页
WOLFSON	XWM81955CFT/RV	14位12MSPS CIS / CCD模拟前端/数字转换器[ 14-bit 12MSPS CIS/CCD Analogue Front End/Digitiser ]	33 页