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5T9070PAGI8

型号：

5T9070PAGI8

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

9 页

PDF大小：

178 K

下载PDF手册
2.5V Single Data Rate 1:10 Clock Buffer  
Terabuffer™ Jr.  
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016 DATASHEET  
5T9070  
DESCRIPTION:  
FEATURES:  
The 5t9070 2.5V single data rate (SDR) clock buffer is a single-ended  
input to ten single-ended outputs buffer built on advanced metal CMOS  
technology. The SDR clock buffer fanout from a single input to ten sin-  
gle-endedoutputsreducestheloadingontheprecedingdriverandprovides  
an efficient clock distribution network.  
• Optimized for 2.5V LVTTL  
• Guaranteed Low Skew < 125ps (max)  
• Very low duty cycle distortion < 300ps (max)  
• High speed propagation delay < 2ns. (max)  
• Up to 200MHz operation  
• Very low CMOS power levels  
• Hot insertable and over-voltage tolerant inputs  
• 1:10 fanout buffer  
The 5t9070 has two output banks that can be asynchronously enabled/  
disabled. Multiple power and grounds reduce noise.  
• 2.5V VDD  
• Available in TSSOP package  
• NOT RECOMMENDED FOR NEW DESIGNS  
• For replacement part use 8T39S11  
APPLICATIONS:  
• Clock and signal distribution  
FUNCTIONAL BLOCK DIAGRAM  
5T9070 REVISION A 4/14/15  
1
©2015 Integrated Device Technology, Inc.  
5T9070 DATA SHEET  
PIN CONFIGURATION  
ABSOLUTE MAXIMUM RATINGS(1)  
Symbol  
VDD  
VI  
Description  
Power Supply Voltage  
Max  
–0.5 to +3.6  
–0.5 to +3.6  
–0.5 to VDD +0.5  
–65 to +165  
150  
Unit  
V
Input Voltage  
V
VO  
Output Voltage  
V
TSTG  
TJ  
Storage Temperature  
Junction Temperature  
°C  
°C  
NOTE:  
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause  
permanentdamagetothedevice.Thisisastressratingonlyandfunctionaloperationofthe  
device at these or any other conditions above those indicated in the operational sections  
of this specification is not implied. Exposure to absolute maximum rating conditions for  
extended periods may affect reliability.  
CAPACITANCE(1) (TA = +25°C, F = 1.0MHz)  
Symbol  
Parameter  
Min  
Typ.  
Max.  
Unit  
pF  
CIN  
Input Capacitance  
—
6
—
NOTE:  
1. This parameter is measured at characterization but not tested.  
TSSOP  
TOP VIEW  
RECOMMENDED OPERATING RANGE  
Symbol  
Description  
Min.  
–40  
2.3  
Typ.  
+25  
2.5  
Max.  
+85  
2.7  
Unit  
°C  
V
TA  
Ambient Operating Temperature  
Internal Power Supply Voltage  
VDD  
2.5V SINGLE DATA RATE  
1:10 CLOCK BUFFER  
TERABUFFER™ JR.  
2
REVISION A 4/14/15  
5T9070 DATA SHEET  
PIN DESCRIPTION  
Symbol  
I/O  
Type  
LVTTL  
LVTTL  
Description  
A
I
I
Clock input  
G1  
Gate for outputs Q1 through Q5. When G1 is LOW, these outputs are enabled. When G1 is HIGH, these outputs are asynchro-  
nously disabled to the level designated by GL(1).  
G2  
I
LVTTL  
Gate for outputs Q6 through Q10. When G2 is LOW, these outputs are enabled. When G2 is HIGH, these outputs are asyn-  
chronously disabled to the level designated by GL(1).  
GL  
Qn  
I
LVTTL  
LVTTL  
PWR  
Specifies output disable level. If HIGH, the outputs disable HIGH. If LOW, the outputs disable LOW.  
O
Clock outputs  
VDD  
Power supply for the device core, inputs, and outputs  
Power supply return for power  
GND  
PWR  
NOTE:  
1. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize the possibility of runt pulses or  
be able to tolerate them in down stream circuitry.  
(1)  
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE  
Symbol  
IIH  
Parameter  
Input HIGH Current  
Input LOW Current  
Clamp Diode Voltage  
DC Input Voltage  
Test Conditions  
Min.  
—
Typ.(4)  
—
Max  
±5  
Unit  
VDD = 2.7V  
VDD = 2.7V  
VI = VDD/GND  
VI = GND/VDD  
μA  
IIL  
—
—
±5  
VIK  
VDD = 2.3V, IIN = -18mA  
—
- 0.7  
- 1.2  
+3.6  
—
V
V
V
V
V
V
V
V
VIN  
- 0.3  
1.7  
VIH  
DC Input HIGH(2)  
VIL  
DC Input LOW(3)  
—
0.7  
—
VOH  
Output HIGH Voltage  
IOH = -12mA  
IOH = -100μA  
IOL = 12mA  
IOL = 100μA  
VDD - 0.4  
VDD - 0.1  
—
—
VOL  
Output LOW Voltage  
0.4  
0.1  
—
NOTES:  
1. See RECOMMENDED OPERATING RANGE table.  
2. Voltage required to maintain a logic HIGH.  
3. Voltage required to maintain a logic LOW.  
4. Typical values are at VDD = 2.5V, +25°C ambient.  
REVISION A 4/14/15  
3
2.5V SINGLE DATA RATE  
1:10 CLOCK BUFFER  
TERABUFFER™ JR.  
5T9070 DATA SHEET  
POWER SUPPLY CHARACTERISTICS  
Symbol  
Parameter  
Test Conditions(1)  
Typ.  
Max  
Unit  
IDDQ  
Quiescent VDD Power Supply Current  
VDD = Max., Reference Clock = LOW  
Outputs enabled, All outputs unloaded  
VDD = Max., VDD = Max., CL = 0pF  
1.5  
2
mA  
IDDD  
ITOT  
Dynamic VDD Power Supply  
Current per Output  
150  
200  
μA/MHz  
Total Power VDD Supply Current  
VDD = 2.5V., FREFERENCE CLOCK = 100MHz, CL = 15pF  
VDD = 2.5V., FREFERENCE CLOCK = 200MHz, CL = 15pF  
70  
90  
mA  
100  
150  
NOTE:  
1. The termination resistors are excluded from these measurements.  
INPUT AC TEST CONDITIONS  
Symbol  
VIH  
Parameter  
Value  
Units  
Input HIGH Voltage  
VDD  
0
V
V
VIL  
Input LOW Voltage  
VTH  
Input Timing Measurement Reference Level(1)  
Input Signal Edge Rate(2)  
VDD/2  
2
V
tR, tF  
V/ns  
NOTES:  
1. A nominal 1.25V timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE) environment.  
2. The input signal edge rate of 2V/ns or greater is to be maintained in the 10% to 90% range of the input waveform.  
AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE(4)  
Symbol  
Parameter  
Min.  
Typ.  
Max  
Unit  
Skew Parameters  
tSK(O)  
Same Device Output Pin-to-Pin Skew(1)  
Pulse Skew(2)  
Part-to-Part Skew(3)  
—
—
—
—
—
—
125  
300  
300  
ps  
ps  
ps  
tSK(P)  
tSK(PP)  
Propagation Delay  
tPLH  
tPHL  
tR  
Propagation Delay A to Qn  
—
—
2
ns  
Output Rise Time (20% to 80%)  
Output Fall Time (20% to 80%)  
Frequency Range  
350  
350  
—
—
—
—
850  
850  
200  
ps  
ps  
tF  
fO  
MHz  
Output Gate Enable/Disable Delay  
tPGE Output Gate Enable to Qn  
tPGD Output Gate Enable to Qn Driven to GL Designated Level  
—
—
—
—
3.5  
3
ns  
ns  
NOTES:  
1. Skew measured between all outputs under identical input and output transitions and load conditions on any one device.  
2. Skew measured is the difference between propagation delay times tPHL and tPLH of any output under identical input and output transitions and load conditions on any one device.  
3. Skew measured is the magnitude of the difference in propagation times between any outputs of two devices, given identical transitions and load conditions at identical VDD levels and  
temperature.  
4. Guaranteed by design.  
2.5V SINGLE DATA RATE  
1:10 CLOCK BUFFER  
TERABUFFER™ JR.  
4
REVISION A 4/14/15  
5T9070 DATA SHEET  
AC TIMING WAVEFORMS  
Propagation and Skew Waveforms  
NOTE: Pulse Skew is calculated using the following expression:  
tSK(P) = | tPHL - tPLH |  
where tPHL and tPLH are measured on the controlled edges of any one output from rising and falling edges of a single pulse. Please note that the tPHL and tPLH shown are not valid  
measurements for this calculation because they are not taken from the same pulse.  
Gate Disable/Enable Runt Pulse Generation  
NOTE:  
As shown, it is possible to generate runt pulses on gate disable and enable of the outputs. It is the user's responsibility to time their Gx signals to avoid this problem.  
REVISION A 4/14/15  
5
2.5V SINGLE DATA RATE  
1:10 CLOCK BUFFER  
TERABUFFER™ JR.  
5T9070 DATA SHEET  
TEST CIRCUIT AND CONDITIONS  
Test Circuit for Input/Output  
INPUT/OUTPUT TEST CONDITIONS  
Symbol  
VDD = 2.5V ± 0.2V  
Unit  
VTH  
VDD / 2  
100  
V
R1  
Ω
R2  
100  
Ω
CL  
15  
pF  
2.5V SINGLE DATA RATE  
1:10 CLOCK BUFFER  
TERABUFFER™ JR.  
6
REVISION A 4/14/15  
5T9070 DATA SHEET  
ORDERING INFORMATION  
XXXXX  
XX  
X
Device Type  
Package  
Process  
-40°C to + 85°C (Industrial)  
TSSOP - Green  
I
PAG  
5T9070  
2.5V Single Data Rate 1:10 Clock Buffer  
Terabuffer™ Jr.  
REVISION A 4/14/15  
7
2.5V SINGLE DATA RATE  
1:10 CLOCK BUFFER  
TERABUFFER™ JR.  
5T9070 DATA SHEET  
REVISION HISTORY  
Rev  
Table  
Page  
Discription of Change  
Date  
A
A
1
7
NRND - Not Recommended for New Designs  
5/5/13  
Ordering Information - removed PA leaded device  
Updated datsheet format  
4/14/15  
Product Discontinuation Notice - Last Time Buy Expires September 7, 2016.  
PDN# N-16-02.  
A
1
3/10/16  
2.5V SINGLE DATA RATE  
1:10 CLOCK BUFFER  
TERABUFFER™ JR.  
8
REVISION A 4/14/15  
Corporate Headquarters  
6024 Silver Creek Valley Road  
San Jose, California 95138  
Sales  
800-345-7015 or +408-284-8200  
Fax: 408-284-2775  
www.IDT.com  
Technical Support  
email: clocks@idt.com  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in  
this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined  
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, wheth-  
er express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others.  
This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.  
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reason-  
ably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or  
their respective third party owners.  
Copyright 2015. All rights reserved.  
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