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5T905PGI

型号：

5T905PGI

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

17 页

PDF大小：

113 K

下载PDF手册
2.5V SINGLE DATA RATE  
IDT5T905  
1:5 CLOCK BUFFER  
TERABUFFER™  
DESCRIPTION:  
FEATURES:  
TheIDT5T9052.5Vsingledatarate(SDR)clockbufferisauser-selectable  
single-ended or differential input to five single-ended outputs buffer built on  
advancedmetalCMOStechnology. TheSDRclockbufferfanoutfromasingle  
or differential input to five single-ended outputs reduces the loading on the  
preceding driver and provides an efficient clock distribution network. The  
IDT5T905canactasatranslatorfromadifferentialHSTL,eHSTL,1.8V/2.5V  
LVTTL,LVEPECL,orsingle-ended1.8V/2.5VLVTTLinputtoHSTL,eHSTL,  
1.8V/2.5VLVTTLoutputs. Selectableinterfaceiscontrolledby3-levelinput  
signals that may be hard-wired to appropriate high-mid-low levels. Multiple  
power and grounds reduce noise.  
• Guaranteed Low Skew < 25ps (max)  
• Very low duty cycle distortion  
• High speed propagation delay < 2.5ns. (max)  
• Up to 250MHz operation  
• Very low CMOS power levels  
• 1.5V VDDQ for HSTL interface  
• Hot insertable and over-voltage tolerant inputs  
• 3-level inputs for selectable interface  
• Selectable HSTL, eHSTL, 1.8V / 2.5V LVTTL, or LVEPECL input  
interface  
• Selectable differential or single-ended inputs and five single-  
ended outputs  
• 2.5V VDD  
• Available in TSSOP package  
APPLICATIONS:  
• Clock and signal distribution  
FUNCTIONALBLOCKDIAGRAM  
TxS  
GL  
OUTPUT  
CONTROL  
G
Q1  
OUTPUT  
CONTROL  
Q2  
RxS  
A
A/VREF  
OUTPUT  
CONTROL  
Q3  
OUTPUT  
CONTROL  
Q4  
OUTPUT  
CONTROL  
Q5  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
FEBRUARY 2009  
1
© 2003 Integrated Device Technology, Inc.  
DSC-5942/26  
IDT5T905  
2.5VSINGLEDATARATE1:5CLOCKBUFFERTERABUFFER  
INDUSTRIALTEMPERATURERANGE  
PINCONFIGURATION  
ABSOLUTEMAXIMUMRATINGS(1)  
Symbol  
VDD  
VDDQ  
VI  
Description  
Max  
–0.5 to +3.6  
–0.5 to +3.6  
–0.5 to +3.6  
–0.5 to VDDQ +0.5  
–0.5 to +3.6  
–65 to +165  
150  
Unit  
V
Power Supply Voltage(2)  
(2)  
Output Power Supply  
V
GL  
VDD  
1
GND  
VDDQ  
GND  
GND  
VDDQ  
Q2  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
Input Voltage  
Output Voltage(3)  
Reference Voltage(3)  
Storage Temperature  
Junction Temperature  
V
2
VO  
V
GND  
3
VREF  
TSTG  
TJ  
V
4
° C  
° C  
G
VDDQ  
Q1  
5
NOTES:  
6
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause  
permanent damage to the device. This is a stress rating only and functional operation  
of the device at these or any other conditions above those indicated in the operational  
sections of this specification is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect reliability.  
2. VDDQ and VDD internally operate independently. No power sequencing requirements  
need to be met.  
3. Not to exceed 3.6V.  
A/VREF  
A
7
GND  
Q3  
8
Q5  
9
Q4  
VDDQ  
GND  
VDD  
10  
11  
12  
13  
14  
VDDQ  
GND  
GND  
VDDQ  
TxS  
VDD  
CAPACITANCE(1,2) (TA = +25°C, F = 1.0MHz)  
RxS  
Symbol  
Parameter  
Min  
Typ.  
Max.  
Unit  
CIN  
Input Capacitance  
—
3.5  
—
pF  
NOTES:  
TSSOP  
1. This parameter is measured at characterization but not tested.  
2. Capacitance applies to all inputs except RxS and TxS.  
TOP VIEW  
RECOMMENDEDOPERATINGRANGE  
Symbol  
Description  
Min.  
–40  
2.4  
Typ.  
+25  
2.5  
Max.  
+85  
2.6  
Unit  
° C  
V
TA  
AmbientOperatingTemperature  
InternalPowerSupplyVoltage  
(1)  
VDD  
HSTLOutputPowerSupplyVoltage  
ExtendedHSTLand1.8VLVTTLOutputPowerSupplyVoltage  
1.4  
1.65  
1.5  
1.8  
1.6  
1.95  
V
V
(1)  
VDDQ  
2.5VLVTTLOutputPowerSupplyVoltage  
TerminationVoltage  
VDD  
V
V
VT  
VDDQ / 2  
NOTE:  
1. All power supplies should operate in tandem. If VDD or VDDQ is at maximum, then VDDQ or VDD (respectively) should be at maximum, and vice-versa.  
2
IDT5T905  
2.5VSINGLEDATARATE1:5CLOCKBUFFERTERABUFFER  
INDUSTRIALTEMPERATURERANGE  
PINDESCRIPTION  
Symbol  
A
I/O  
Type  
Description  
I
I
Adjustable(1) Clockinput. Ais the "true"side ofthe differentialclockinput. Ifoperatinginsingle-endedmode, Ais the clockinput.  
A/VREF  
Adjustable(1) Complementaryclockinput. A/VREF isthe"complementary"sideofAiftheinputisindifferentialmode. Ifoperatinginsingle-ended  
mode,A/VREF isconnectedtoGND. Forsingle-endedoperationindifferentialmode, A/VREF shouldbesettothedesiredtoggle  
voltage forA:  
2.5VLVTTL  
VREF = 1250mV  
1.8VLVTTL,eHSTL VREF = 900mV  
HSTL  
VREF = 750mV  
VREF = 1082mV  
LVEPECL  
(5)  
G
I
LVTTL  
Gate control for Qn outputs. When G is LOW, these outputs are enabled. When G is HIGH, these outputs are asynchronously  
(4)  
disabledtotheleveldesignatedbyGL .  
(5)  
GL  
Qn  
I
O
I
LVTTL  
Specifies output disable level. If HIGH, the outputs disable HIGH. If LOW, the outputs disable LOW.  
Adjustable(2) Clockoutputs  
(3)  
RxS  
TxS  
3Level  
Selectssingle-ended2.5VLVTTL(HIGH),1.8VLVTTL(MID)clockinputordifferential(LOW)clockinput  
(3)  
I
3Level  
Sets the drive strength of the output drivers to be 2.5V LVTTL (HIGH), 1.8V LVTTL (MID) or HSTL (LOW) compatible. Used in  
conjunctionwithVDDQ tosettheinterfacelevels.  
VDD  
VDDQ  
PWR  
PWR  
PWR  
Powersupplyforthe device core andinputs  
Powersupplyforthedeviceoutputs. Whenutilizing2.5VLVTTLoutputs,VDDQ shouldbeconnectedtoVDD.  
Powersupplyreturnforallpower  
GND  
NOTES:  
1. Inputs are capable of translating the following interface standards. User can select between:  
Single-ended 2.5V LVTTL levels  
Single-ended 1.8V LVTTL levels  
or  
Differential 2.5V/1.8V LVTTL levels  
Differential HSTL and eHSTL levels  
Differential LVEPECL levels  
2. Outputs are user selectable to drive 2.5V, 1.8V LVTTL, eHSTL, or HSTL interface levels when used with the appropriate VDDQ voltage.  
3. 3 level inputs are static inputs and must be tied to VDD or GND or left floating. These inputs are not hot-insertable or over-voltage tolerant.  
4. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize the possibility of runt  
pulses or be able to tolerate them in down stream circuitry.  
5. Pins listed as LVTTL inputs will accept 2.5V signals when RxS = HIGH or 1.8V signals when RxS = LOW or MID.  
3
IDT5T905  
2.5VSINGLEDATARATE1:5CLOCKBUFFERTERABUFFER  
INDUSTRIALTEMPERATURERANGE  
INPUT/OUTPUTSELECTION(1)  
Input  
Output  
Input  
Output  
2.5V LVTTL SE  
1.8V LVTTL SE  
2.5V LVTTL DSE  
1.8V LVTTL DSE  
LVEPECL DSE  
eHSTL DSE  
eHSTL  
2.5V LVTTL SE  
1.8V LVTTL SE  
2.5V LVTTL DSE  
1.8V LVTTL DSE  
LVEPECL DSE  
eHSTL DSE  
2.5VLVTTL  
HSTL DSE  
HSTL DSE  
2.5VLVTTLDIF  
1.8VLVTTLDIF  
LVEPECL DIF  
eHSTL DIF  
2.5VLVTTLDIF  
1.8VLVTTLDIF  
LVEPECL DIF  
eHSTL DIF  
HSTL DIF  
HSTL DIF  
2.5V LVTTL SE  
1.8V LVTTL SE  
2.5V LVTTL DSE  
1.8V LVTTL DSE  
LVEPECL DSE  
eHSTL DSE  
HSTL  
2.5V LVTTL SE  
1.8V LVTTL SE  
2.5V LVTTL DSE  
1.8V LVTTL DSE  
LVEPECL DSE  
eHSTL DSE  
1.8VLVTTL  
HSTL DSE  
HSTL DSE  
2.5VLVTTLDIF  
1.8VLVTTLDIF  
LVEPECL DIF  
eHSTL DIF  
2.5VLVTTLDIF  
1.8VLVTTLDIF  
LVEPECL DIF  
eHSTL DIF  
HSTL DIF  
HSTL DIF  
NOTE:  
1. The INPUT/OUTPUT SELECTION Table describes the total possible combinations of input and output interfaces. Single-Ended (SE) inputs in a single-ended mode require the  
A/VREF pin to be connected to GND. Differential Single-Ended (DSE) is for single-ended operation in differential mode, requiring a VREF. Differential (DIF) inputs are used only in  
differential mode.  
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE  
Symbol  
VIHH  
Parameter  
Test Conditions  
Min.  
Max  
Unit  
V
(1)  
Input HIGH Voltage Level  
3-Level Inputs Only  
3-Level Inputs Only  
3-Level Inputs Only  
VIN = VDD  
VDD – 0.4  
—
(1)  
VIMM  
InputMIDVoltage Level  
VDD/2 – 0.2 VDD/2 + 0.2  
V
(1)  
VILL  
InputLOWVoltageLevel  
—
—
0.4  
200  
+50  
—
V
HIGH Level  
MID Level  
LOW Level  
I3  
3-Level Input DC Current (RxS, TxS)  
VIN = VDD/2  
–50  
–200  
μA  
VIN = GND  
NOTE:  
1. These inputs are normally wired to VDD, GND, or left floating. Internal termination resistors bias unconnected unputs to VDD/2.  
4
IDT5T905  
2.5VSINGLEDATARATE1:5CLOCKBUFFERTERABUFFER  
INDUSTRIALTEMPERATURERANGE  
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGEFORHSTL(1)  
Symbol  
Parameter  
Test Conditions  
Min.  
Typ.(7)  
Max  
Unit  
InputCharacteristics  
(9)  
IIH  
IIL  
Input HIGH Current  
InputLOWCurrent(9)  
VDD = 2.6V  
VDD = 2.6V  
VI = VDDQ/GND  
VI = GND/VDDQ  
—
—
—
—
±5  
±5  
μA  
VIK  
ClampDiodeVoltage  
VDD = 2.4V, IIN = -18mA  
—
- 0.7  
- 1.2  
+3.6  
—
V
VIN  
VDIF  
VCM  
VIH  
VIL  
DCInputVoltage  
- 0.3  
0.2  
V
DCDifferentialVoltage(2,8)  
DC Common Mode Input Voltage(3,8)  
V
680  
750  
750  
900  
mV  
mV  
mV  
mV  
(4,5,8)  
DC Input HIGH  
VREF + 100  
—
—
(4,6,8)  
DC Input LOW  
VREF - 100  
—
VREF  
Single-EndedReferenceVoltage(4,8)  
—
OutputCharacteristics  
VOH  
VOL  
OutputHIGHVoltage  
IOH = -8mA  
IOH = -100μA  
IOL = 8mA  
VDDQ - 0.4  
VDDQ - 0.1  
—
—
—
0.4  
0.1  
V
V
V
V
OutputLOWVoltage  
IOL = 100μA  
—
NOTES:  
1. See RECOMMENDED OPERATING RANGE table.  
2. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode  
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching  
to a new state.  
3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.  
4. For single-ended operation, in differential mode, A/VREF is tied to the DC voltage VREF.  
5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.  
6. Voltage required to maintain a logic LOW, single-ended operation in differential mode.  
7. Typical values are at VDD = 2.5V, VDDQ = 1.5V, +25°C ambient.  
8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface table should be  
referenced.  
9. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.  
POWERSUPPLYCHARACTERISTICSFORHSTLOUTPUTS(1)  
Symbol  
Parameter  
Test Conditions(2)  
Typ.  
Max  
Unit  
(3)  
IDDQ  
Quiescent VDD Power Supply Current  
VDDQ = Max., Reference Clock = LOW  
20  
30  
mA  
Outputsenabled,Alloutputsunloaded  
(3)  
IDDQQ  
IDDD  
IDDDQ  
ITOT  
Quiescent VDDQ Power Supply Current  
VDDQ = Max., Reference Clock = LOW  
Outputsenabled,Alloutputsunloaded  
VDD = Max., VDDQ = Max., CL = 0pF  
0.1  
10  
15  
0.3  
20  
30  
mA  
μA/MHz  
μA/MHz  
mA  
Dynamic VDD Power Supply  
CurrentperOutput  
Dynamic VDDQ Power Supply  
CurrentperOutput  
VDD = Max., VDDQ = Max., CL = 0pF  
Total Power VDD Supply Current  
VDDQ = 1.5V, FREFERENCE CLOCK = 100MHz, CL = 15pF  
VDDQ = 1.5V, FREFERENCE CLOCK = 250MHz, CL = 15pF  
VDDQ = 1.5V, FREFERENCE CLOCK = 100MHz, CL = 15pF  
VDDQ = 1.5V, FREFERENCE CLOCK = 250MHz, CL = 15pF  
20  
25  
15  
30  
30  
40  
30  
60  
ITOTQ  
Total Power VDDQ Supply Current  
mA  
NOTES:  
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.  
2. The termination resistors are excluded from these measurements.  
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.  
5
IDT5T905  
2.5VSINGLEDATARATE1:5CLOCKBUFFERTERABUFFER  
INDUSTRIALTEMPERATURERANGE  
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR HSTL  
Symbol  
VDIF  
Parameter  
Value  
Units  
V
InputSignalSwing(1)  
1
(2)  
VX  
DifferentialInputSignalCrossingPoint  
750  
CrossingPoint  
1
mV  
V
(3)  
VTHI  
InputTimingMeasurementReferenceLevel  
InputSignalEdgeRate(4)  
tR,tF  
V/ns  
NOTES:  
1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the  
VDIF (AC) specification under actual use conditions.  
2. A 750mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VX specification  
under actual use conditions.  
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.  
4. The input signal edge rate of 1V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.  
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGEFOReHSTL(1)  
Symbol  
Parameter  
Test Conditions  
Min.  
Typ.(7)  
Max  
Unit  
InputCharacteristics  
IIH  
IIL  
Input HIGH Current(9)  
InputLOWCurrent(9)  
VDD = 2.6V  
VDD = 2.6V  
VI = VDDQ/GND  
VI = GND/VDDQ  
—
—
—
—
±5  
±5  
μA  
VIK  
ClampDiodeVoltage  
VDD = 2.4V, IIN = -18mA  
—
- 0.7  
- 1.2  
+3.6  
—
V
VIN  
VDIF  
VCM  
VIH  
VIL  
DCInputVoltage  
- 0.3  
0.2  
V
DCDifferentialVoltage(2,8)  
DC Common Mode Input Voltage(3,8)  
V
800  
900  
900  
1000  
—
mV  
mV  
mV  
mV  
(4,5,8)  
DC Input HIGH  
VREF + 100  
—
(4,6,8)  
DC Input LOW  
VREF - 100  
—
VREF  
Single-EndedReferenceVoltage(4,8)  
—
OutputCharacteristics  
VOH  
VOL  
OutputHIGHVoltage  
IOH = -8mA  
IOH = -100μA  
IOL = 8mA  
VDDQ - 0.4  
VDDQ - 0.1  
—
—
—
0.4  
0.1  
V
V
V
V
OutputLOWVoltage  
IOL = 100μA  
—
NOTES:  
1. See RECOMMENDED OPERATING RANGE table.  
2. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode  
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching  
to a new state.  
3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.  
4. For single-ended operation, in a differential mode, A/VREF is tied to the DC voltage VREF.  
5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.  
6. Voltage required to maintain a logic LOW, single-ended operation in differential mode.  
7. Typical values are at VDD = 2.5V, VDDQ = 1.8V, +25°C ambient.  
8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface table should be  
referenced.  
9. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.  
6
IDT5T905  
2.5VSINGLEDATARATE1:5CLOCKBUFFERTERABUFFER  
INDUSTRIALTEMPERATURERANGE  
POWERSUPPLYCHARACTERISTICSFOReHSTLOUTPUTS(1)  
Symbol  
Parameter  
Test Conditions(2)  
Typ.  
Max  
Unit  
(3)  
IDDQ  
Quiescent VDD Power Supply Current  
VDDQ = Max., Reference Clock = LOW  
20  
30  
mA  
Outputsenabled,Alloutputsunloaded  
(3)  
IDDQQ  
IDDD  
IDDDQ  
ITOT  
Quiescent VDDQ Power Supply Current  
VDDQ = Max., Reference Clock = LOW  
Outputsenabled,Alloutputsunloaded  
VDD = Max., VDDQ = Max., CL = 0pF  
0.1  
10  
20  
0.3  
20  
30  
mA  
μA/MHz  
μA/MHz  
mA  
Dynamic VDD Power Supply  
CurrentperOutput  
Dynamic VDDQ Power Supply  
CurrentperOutput  
VDD = Max., VDDQ = Max., CL = 0pF  
Total Power VDD Supply Current  
VDDQ = 1.8V, FREFERENCE CLOCK = 100MHz, CL = 15pF  
VDDQ = 1.8V, FREFERENCE CLOCK = 250MHz, CL = 15pF  
VDDQ = 1.8V, FREFERENCE CLOCK = 100MHz, CL = 15pF  
VDDQ = 1.8V, FREFERENCE CLOCK = 250MHz, CL = 15pF  
20  
25  
20  
40  
30  
40  
40  
80  
ITOTQ  
Total Power VDDQ Supply Current  
mA  
NOTES:  
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.  
2. The termination resistors are excluded from these measurements.  
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.  
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR eHSTL  
Symbol  
VDIF  
Parameter  
Value  
Units  
InputSignalSwing(1)  
1
V
mV  
V
VX  
DifferentialInputSignalCrossingPoint(2)  
900  
CrossingPoint  
1
(3)  
VTHI  
InputTimingMeasurementReferenceLevel  
InputSignalEdgeRate(4)  
tR,tF  
V/ns  
NOTES:  
1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the  
VDIF (AC) specification under actual use conditions.  
2. A 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VX specification  
under actual use conditions.  
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.  
4. The input signal edge rate of 1V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.  
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGEFOR  
LVEPECL(1)  
Symbol  
Parameter  
Test Conditions  
Min.  
Typ.(2)  
Max  
Unit  
InputCharacteristics  
(6)  
IIH  
IIL  
Input HIGH Current  
InputLOWCurrent(6)  
VDD = 2.6V  
VDD = 2.6V  
VI = VDDQ/GND  
VI = GND/VDDQ  
—
—
—
—
±5  
±5  
μA  
VIK  
VIN  
VCM  
VREF  
VIH  
VIL  
ClampDiodeVoltage  
DCInputVoltage  
DC Common Mode Input Voltage(3,5)  
Single-EndedReferenceVoltage(4,5)  
DC Input HIGH  
VDD = 2.4V, IIN = -18mA  
—
- 0.7  
—
- 1.2  
3.6  
V
- 0.3  
915  
—
V
1082  
1082  
—
1248  
—
mV  
mV  
mV  
mV  
1275  
555  
1620  
875  
DC Input LOW  
—
NOTES:  
1. See RECOMMENDED OPERATING RANGE table.  
2. Typical values are at VDD = 2.5V, +25°C ambient.  
3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.  
4. For single-ended operation while in differential mode, A/VREF is tied to the DC voltage VREF.  
5. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface table should  
be referenced.  
6. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.  
7
IDT5T905  
2.5VSINGLEDATARATE1:5CLOCKBUFFERTERABUFFER  
INDUSTRIALTEMPERATURERANGE  
DIFFERENTIALINPUTACTESTCONDITIONSFORLVEPECL  
Symbol  
VDIF  
Parameter  
Value  
Units  
mV  
mV  
V
InputSignalSwing(1)  
732  
(2)  
VX  
DifferentialInputSignalCrossingPoint  
1082  
CrossingPoint  
1
(3)  
VTHI  
InputTimingMeasurementReferenceLevel  
InputSignalEdgeRate(4)  
tR,tF  
V/ns  
NOTES:  
1. The 732mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet  
the VDIF (AC) specification under actual use conditions.  
2. A 1082mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VX specification  
under actual use conditions.  
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.  
4. The input signal edge rate of 1V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.  
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGEFOR2.5V  
LVTTL(1)  
Symbol  
Parameter  
Test Conditions  
Min.  
Typ.(8)  
Max  
Unit  
InputCharacteristics  
IIH  
IIL  
Input HIGH Current(10)  
InputLOWCurrent(10)  
ClampDiodeVoltage  
DCInputVoltage  
VDD = 2.6V  
VDD = 2.6V  
VI = VDDQ/GND  
VI = GND/VDDQ  
—
—
—
—
±5  
±5  
μA  
VIK  
VIN  
VDD = 2.4V, IIN = -18mA  
—
- 0.7  
- 1.2  
+3.6  
V
V
- 0.3  
Single-Ended Inputs(2)  
VIH  
DC Input HIGH  
DC Input LOW  
1.7  
—
—
V
V
VIL  
0.7  
DifferentialInputs  
VDIF  
VCM  
VIH  
DCDifferentialVoltage(3,9)  
DC Common Mode Input Voltage(4,9)  
0.2  
1150  
—
1350  
V
1250  
1250  
mV  
mV  
mV  
mV  
(5,6,9)  
DC Input HIGH  
VREF + 100  
—
—
(5,7,9)  
VIL  
DC Input LOW  
VREF - 100  
—
VREF  
Single-EndedReferenceVoltage(5,9)  
—
OutputCharacteristics  
VOH  
VOL  
OutputHIGHVoltage  
IOH = -12mA  
IOH = -100μA  
IOL = 12mA  
IOL = 100μA  
VDDQ - 0.4  
VDDQ - 0.1  
—
—
—
0.4  
0.1  
V
V
V
V
OutputLOWVoltage  
—
NOTES:  
1. See RECOMMENDED OPERATING RANGE table.  
2. For 2.5V LVTTL single-ended operation, the RxS pin is tied HIGH and A/VREF is tied to GND.  
3. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode  
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching  
to a new state.  
4. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.  
5. For single-ended operation, in differential mode, A/VREF is tied to the DC voltage VREF.  
6. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.  
7. Voltage required to maintain a logic LOW, single-ended operation in differential mode.  
8. Typical values are at VDD = 2.5V, VDDQ = VDD, +25°C ambient.  
9. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface table should be  
referenced.  
10. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.  
8
IDT5T905  
2.5VSINGLEDATARATE1:5CLOCKBUFFERTERABUFFER  
INDUSTRIALTEMPERATURERANGE  
POWERSUPPLYCHARACTERISTICSFOR2.5VLVTTLOUTPUTS(1)  
Symbol  
Parameter  
Test Conditions(2)  
Typ.  
Max  
Unit  
(3)  
IDDQ  
Quiescent VDD Power Supply Current  
VDDQ = Max., Reference Clock = LOW  
Outputsenabled,Alloutputsunloaded  
20  
30  
mA  
(3)  
IDDQQ  
IDDD  
IDDDQ  
ITOT  
Quiescent VDDQ Power Supply Current  
VDDQ = Max., Reference Clock = LOW  
Outputsenabled,Alloutputsunloaded  
VDD = Max., VDDQ = Max., CL = 0pF  
0.1  
15  
30  
0.3  
20  
40  
mA  
μA/MHz  
μA/MHz  
mA  
Dynamic VDD Power Supply  
CurrentperOutput  
Dynamic VDDQ Power Supply  
CurrentperOutput  
VDD = Max., VDDQ = Max., CL = 0pF  
Total Power VDD Supply Current  
VDDQ = 2.5V, FREFERENCE CLOCK = 100MHz, CL = 15pF  
VDDQ = 2.5V, FREFERENCE CLOCK = 200MHz, CL = 15pF  
VDDQ = 2.5V, FREFERENCE CLOCK = 100MHz, CL = 15pF  
VDDQ = 2.5V, FREFERENCE CLOCK = 200MHz, CL = 15pF  
20  
30  
30  
70  
40  
50  
ITOTQ  
Total Power VDDQ Supply Current  
50  
mA  
100  
NOTES:  
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.  
2. The termination resistors are excluded from these measurements.  
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.  
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR 2.5V LVTTL  
Symbol  
VDIF  
Parameter  
Value  
VDD  
Units  
InputSignalSwing(1)  
V
V
VX  
DifferentialInputSignalCrossingPoint(2)  
VDD/2  
(3)  
VTHI  
InputTimingMeasurementReferenceLevel  
InputSignalEdgeRate(4)  
CrossingPoint  
2.5  
V
tR,tF  
V/ns  
NOTES:  
1. A nominal 2.5V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must  
meet the VDIF (AC) specification under actual use conditions.  
2. A nominal 1.25V crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the  
VX specification under actual use conditions.  
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.  
4. The input signal edge rate of 2.5V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.  
SINGLE-ENDED INPUT AC TEST CONDITIONS FOR 2.5V LVTTL  
Symbol  
VIH  
Parameter  
Value  
VDD  
0
Units  
V
Input HIGH Voltage  
InputLOWVoltage  
VIL  
V
(1)  
VTHI  
InputTimingMeasurementReferenceLevel  
InputSignalEdgeRate(2)  
VDD/2  
2
V
tR,tF  
V/ns  
NOTES:  
1. A nominal 1.25V timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE) environment.  
2. The input signal edge rate of 2V/ns or greater is to be maintained in the 10% to 90% range of the input waveform.  
9
IDT5T905  
2.5VSINGLEDATARATE1:5CLOCKBUFFERTERABUFFER  
INDUSTRIALTEMPERATURERANGE  
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGEFOR1.8V  
LVTTL(1)  
Symbol  
Parameter  
Test Conditions  
Min.  
Typ.(8)  
Max  
Unit  
InputCharacteristics  
IIH  
IIL  
Input HIGH Current(12)  
InputLOWCurrent(12)  
ClampDiodeVoltage  
DCInputVoltage  
VDD = 2.6V  
VDD = 2.6V  
VI = VDDQ/GND  
VI = GND/VDDQ  
—
—
—
—
±5  
±5  
μA  
VIK  
VIN  
VDD = 2.4V, IIN = -18mA  
—
- 0.7  
- 1.2  
V
V
- 0.3  
VDDQ + 0.3  
Single-Ended Inputs(2)  
VIH  
DC Input HIGH  
DC Input LOW  
1.073(10)  
—
—
V
V
(11)  
VIL  
0.683  
DifferentialInputs  
VDIF  
VCM  
VIH  
DCDifferentialVoltage(3,9)  
DC Common Mode Input Voltage(4,9)  
0.2  
825  
—
975  
V
900  
900  
mV  
mV  
mV  
mV  
(5,6,9)  
DC Input HIGH  
VREF + 100  
—
—
(5,7,9)  
VIL  
DC Input LOW  
VREF - 100  
—
VREF  
Single-EndedReferenceVoltage(5,9)  
—
OutputCharacteristics  
VOH  
VOL  
OutputHIGHVoltage  
IOH = -6mA  
IOH = -100μA  
IOL = 6mA  
VDDQ - 0.4  
VDDQ - 0.1  
—
—
—
0.4  
0.1  
V
V
V
V
OutputLOWVoltage  
IOL = 100μA  
—
NOTES:  
1. See RECOMMENDED OPERATING RANGE table.  
2. For 1.8V LVTTL single-ended operation, the RxS pin is allowed to float or tied to VDD/2 and A/VREF is tied to GND.  
3. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode  
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching  
to a new state.  
4. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.  
5. For single-ended operation in differential mode, A/VREF is tied to the DC voltage VREF. The input is guaranteed to toggle within ±200mV of VREF when VREF is constrained within  
+600mV and VDDI-600mV, where VDDI is the nominal 1.8V power supply of the device driving the A input. To guarantee switching in voltage range specified in the JEDEC 1.8V  
LVTTL interface specification, VREF must be maintained at 900mV with appropriate tolerances.  
6. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.  
7. Voltage required to maintain a logic LOW, single-ended operation in differential mode.  
8. Typical values are at VDD = 2.5V, VDDQ = 1.8V, +25°C ambient.  
9. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface table should be  
referenced.  
10. This value is the worst case minimum VIH over the specification range of the 1.8V power supply. The 1.8V LVTTL specification is VIH = 0.65 • VDD where VDD is 1.8V ± 0.15V.  
However, the LVTTL translator is supplied by a 2.5V nominal supply on this part. To ensure compliance with the specification, the translator was designed to accept the calculated  
worst case value ( VIH = 0.65 • [1.8 - 0.15V]) rather than reference against a nominal 1.8V supply.  
11. This value is the worst case maximum VIL over the specification range of the 1.8V power supply. The 1.8V LVTTL specification is VIL = 0.35 • VDD where VDD is 1.8V ± 0.15V.  
However, the LVTTL translator is supplied by a 2.5V nominal supply on this part. To ensure compliance with the specification, the translator was designed to accept the calculated  
worst case value ( VIH = 0.35 • [1.8 + 0.15V]) rather than reference against a nominal 1.8V supply.  
12. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.  
10  
IDT5T905  
2.5VSINGLEDATARATE1:5CLOCKBUFFERTERABUFFER  
INDUSTRIALTEMPERATURERANGE  
POWERSUPPLYCHARACTERISTICSFOR1.8VLVTTLOUTPUTS(1)  
Symbol  
Parameter  
Test Conditions(2)  
Typ.  
Max  
Unit  
(3)  
IDDQ  
Quiescent VDD Power Supply Current  
VDDQ = Max., Reference Clock = LOW  
20  
30  
mA  
Outputsenabled,Alloutputsunloaded  
(3)  
IDDQQ  
IDDD  
IDDDQ  
ITOT  
Quiescent VDDQ Power Supply Current  
VDDQ = Max., Reference Clock = LOW  
Outputsenabled,Alloutputsunloaded  
VDD = Max., VDDQ = Max., CL = 0pF  
0.1  
20  
20  
0.3  
30  
30  
mA  
μA/MHz  
μA/MHz  
mA  
Dynamic VDD Power Supply  
CurrentperOutput  
Dynamic VDDQ Power Supply  
CurrentperOutput  
VDD = Max., VDDQ = Max., CL = 0pF  
Total Power VDD Supply Current  
VDDQ = 1.8V, FREFERENCE CLOCK = 100MHz, CL = 15pF  
VDDQ = 1.8V, FREFERENCE CLOCK = 200MHz, CL = 15pF  
VDDQ = 1.8V, FREFERENCE CLOCK = 100MHz, CL = 15pF  
VDDQ = 1.8V, FREFERENCE CLOCK = 200MHz, CL = 15pF  
20  
30  
20  
45  
30  
40  
40  
80  
ITOTQ  
Total Power VDDQ Supply Current  
mA  
NOTES:  
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.  
2. The termination resistors are excluded from these measurements.  
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.  
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR 1.8V LVTTL  
Symbol  
VDIF  
Parameter  
Value  
VDDI  
Units  
InputSignalSwing(1)  
V
mV  
V
VX  
DifferentialInputSignalCrossingPoint(2)  
VDDI/2  
(3)  
VTHI  
InputTimingMeasurementReferenceLevel  
InputSignalEdgeRate(4)  
CrossingPoint  
1.8  
tR,tF  
V/ns  
NOTES:  
1. VDDI is the nominal 1.8V supply (1.8V ± 0.15V) of the part or source driving the input. A nominal 1.8V peak-to-peak input pulse level is specified to allow consistent, repeatable  
results in an automatic test equipment (ATE) environment. Compliant devices must meet the VDIF (AC) specification under actual use conditions.  
2. A nominal 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the  
VX specification under actual use conditions.  
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.  
4. The input signal edge rate of 1.8V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.  
SINGLE-ENDED INPUT AC TEST CONDITIONS FOR 1.8V LVTTL  
Symbol  
VIH  
Parameter  
Value  
VDDI  
0
Units  
V
Input HIGH Voltage(1)  
VIL  
InputLOWVoltage  
V
(2)  
VTHI  
InputTimingMeasurementReferenceLevel  
InputSignalEdgeRate(3)  
VDDI/2  
2
mV  
V/ns  
tR,tF  
NOTES:  
1. VDDI is the nominal 1.8V supply (1.8V ± 0.15V) of the part or source driving the input.  
2. A nominal 900mV timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE) environment.  
3. The input signal edge rate of 2V/ns or greater is to be maintained in the 10% to 90% range of the input waveform.  
11  
IDT5T905  
2.5VSINGLEDATARATE1:5CLOCKBUFFERTERABUFFER  
INDUSTRIALTEMPERATURERANGE  
ACELECTRICALCHARACTERISTICSOVEROPERATINGRANGE(6)  
Symbol  
SkewParameters  
tSK(O)  
Parameter  
Min.  
Typ.  
Max  
Unit  
ps  
(1)  
Same Device Output Pin-to-Pin Skew  
Single-EndedandDifferentialModes  
Single-EndedinDifferentialMode(DSE)  
Single-EndedandDifferentialModes  
Single-EndedinDifferentialMode(DSE)  
—
—
—
—
40  
—
25  
25  
—
300  
—
60  
(2)  
(3)  
tSK(P)  
Pulse Skew  
—
300  
—
—
300  
ps  
(4)  
dT  
Duty Cycle  
%
ps  
(5)  
tSK(PP)  
Part-to-PartSkew  
Single-EndedandDifferentialModes  
—
—
300  
—
Single-EndedinDifferentialMode(DSE)  
PropagationDelay  
tPLH  
tPHL  
tR  
PropagationDelayAtoQn  
—
—
2.5  
ns  
ps  
Output Rise Time (20% to 80%)  
Output Fall Time (20% to 80%)  
2.5V/1.8VLVTTLOutputs  
HSTL / eHSTL Outputs  
2.5V/1.8VLVTTLOutputs  
HSTL / eHSTL Outputs  
350  
350  
350  
350  
—
—
—
—
—
—
—
1050  
1350  
1050  
1350  
250  
tF  
ps  
fO  
FrequencyRange(HSTL/eHSTLoutputs)  
FrequencyRange(2.5V/1.8VLVTTLoutputs)  
MHz  
—
200  
OutputGateEnable/DisableDelay  
tPGE  
tPGD  
OutputGateEnabletoQn  
OutputGateEnabletoQnDriventoGLDesignatedLevel  
—
—
—
—
3.5  
3
ns  
ns  
NOTES:  
1. Skew measured between all outputs under identical input and output interfaces, transitions, and load conditions on any one device.  
2. For only 1.8V/2.5V LVTTL and eHSTL outputs.  
3. Skew measured is difference between propagation times tPLH and tPHL of any output under identical input and output interfaces, transitions, and load conditions on any one device.  
4. For only HSTL outputs.  
5. Skew measured is the magnitude of the difference in propagation times between any outputs of two devices, given identical transitions and load conditions at identical VDD/VDDQ  
levels and temperature.  
6. Guaranteed by design.  
12  
IDT5T905  
2.5VSINGLEDATARATE1:5CLOCKBUFFERTERABUFFER  
INDUSTRIALTEMPERATURERANGE  
ACDIFFERENTIALINPUTSPECIFICATIONS(1)  
Symbol  
Parameter  
Min.  
1.73  
2.17  
Typ.  
—
Max  
—
Unit  
(2)  
tW  
Reference Clock Pulse Width HIGH or LOW (HSTL/eHSTL outputs)  
Reference Clock Pulse Width HIGH or LOW (2.5V / 1.8V LVTTL outputs)  
HSTL/eHSTL/1.8V LVTTL/2.5V LVTTL  
ns  
(2)  
—
—
VDIF  
VIH  
ACDifferentialVoltage(3)  
400  
Vx + 200  
—
—
—
—
—
—
mV  
mV  
mV  
(4,5)  
AC Input HIGH  
(4,6)  
VIL  
AC Input LOW  
Vx - 200  
LVEPECL  
VDIF  
ACDifferentialVoltage(3)  
400  
1275  
—
—
—
—
—
—
mV  
mV  
mV  
(4)  
VIH  
AC Input HIGH  
(4)  
VIL  
AC Input LOW  
875  
NOTES:  
1. For differential input mode, RxS is tied to GND.  
2. Both differential input signals should not be driven to the same level simultaneously. The input will not change state until the inputs have crossed and the voltage range defined  
by VDIF has been met or exceeded.  
3. Differential mode only. VDIF specifies the minimum input voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level.  
The AC differential voltage must be achieved to guarantee switching to a new state.  
4. For single-ended operation, A/VREF is tied to DC voltage (VREF). Refer to each input interface's DC specification for the correct VREF range.  
5. Voltage required to switch to a logic HIGH, single-ended operation only.  
6. Voltage required to switch to a logic LOW, single-ended operation only.  
13  
IDT5T905  
2.5VSINGLEDATARATE1:5CLOCKBUFFERTERABUFFER  
INDUSTRIALTEMPERATURERANGE  
ACTIMING WAVEFORMS  
1/fo  
tW  
tW  
VIH  
VTHI  
VIL  
A
A
VIH  
VTHI  
VIL  
tPHL  
tPLH  
VOH  
VTHO  
VOL  
Qn  
Qm  
tSK(O)  
tSK(O)  
VOH  
VTHO  
VOL  
Propagation and Skew Waveforms  
NOTES:  
1. tPHL and tPLH signals are measured from the input passing through VTHI or input pair crossing to Qn passing through VTHO.  
2. Pulse Skew is calculated using the following expression:  
tSK(P) = | tPHL - tPLH |  
where tPHL and tPLH are measured on the controlled edges of any one output from rising and falling edges of a single pulse. Please note that the tPHL and tPLH shown are not  
valid measurements for this calculation because they are not taken from the same pulse.  
VIH  
VTHI  
VIL  
A
A
VIH  
VTHI  
VIL  
VIH  
VTHI  
VIL  
GL  
G
tPLH  
VIH  
VTHI  
VIL  
tPGD  
tPGE  
VOH  
VTHO  
VOL  
Qn  
Gate Disable/Enable Showing Runt Pulse Generation  
NOTE:  
As shown, it is possible to generate runt pulses on gate disable and enable of the outputs. It is the user's responsibility to time their Gx signals to avoid this problem.  
14  
IDT5T905  
2.5VSINGLEDATARATE1:5CLOCKBUFFERTERABUFFER  
INDUSTRIALTEMPERATURERANGE  
TESTCIRCUITSANDCONDITIONS  
VDDI  
R1  
R2  
3 inch, ~50Ω  
Transmission Line  
VIN  
VDDQ  
VDD  
VDDI  
A
D.U.T.  
Pulse  
Generator  
R1  
R2  
A
3 inch, ~50Ω  
Transmission Line  
VIN  
Test Circuit for Differential Input(1)  
DIFFERENTIALINPUTTESTCONDITIONS  
Symbol  
VDD = 2.5V ± 0.1V  
Unit  
R1  
100  
Ω
R2  
100  
Ω
VDDI  
VCM*2  
V
HSTL: Crossing of A and A  
eHSTL: Crossing of A and A  
LVEPECL: Crossing of A and A  
1.8V LVTTL: VDDI/2  
2.5V LVTTL: VDD/2  
VTHI  
V
NOTE:  
1. This input configuration is used for all input interfaces. For single-ended testing,  
the VIN input is tied to GND. For testing single-ended in differential input mode,  
the VIN is left floating.  
15  
IDT5T905  
2.5VSINGLEDATARATE1:5CLOCKBUFFERTERABUFFER  
INDUSTRIALTEMPERATURERANGE  
VDDQ  
VDDQ  
VDD  
R1  
D.U.T.  
Qn  
R2  
CL  
Test Circuit for SDR Outputs  
SDROUTPUTTESTCONDITIONS  
Symbol  
VDD = 2.5V ± 0.1V  
Unit  
VDDQ = Interface Specified  
CL  
R1  
15  
100  
pF  
Ω
Ω
V
R2  
100  
VTHO  
VDDQ / 2  
16  
IDT5T905  
2.5VSINGLEDATARATE1:5CLOCKBUFFERTERABUFFER  
INDUSTRIALTEMPERATURERANGE  
ORDERINGINFORMATION  
XX  
X
XXXXX  
Package Package  
Device Type  
I
-40°C to +85°C (Industrial)  
PG  
PGG  
Thin Shrink Small Outline Package  
TSSOP - Green  
2.5V Single Data Rate 1:5 Clock Buffer Terabuffer™  
5T905  
CORPORATE HEADQUARTERS  
for SALES:  
for Tech Support:  
6024 Silver Creek Valley Road  
San Jose, CA 95138  
800-345-7015 or 408-284-8200  
fax: 408-284-2775  
www.idt.com  
clockhelp@idt.com  
17  
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IDT

 		5T9010BBGI8 [ PLL Based Clock Driver, 5T Series, 5 True Output(s), 0 Inverted Output(s), PBGA144, LEAD FREE, PLASTIC, BGA-144 ] 25 页

IDT

 		5T9050PGI [ Low Skew Clock Driver, 5T Series, 5 True Output(s), 0 Inverted Output(s), CMOS, PDSO28, TSSOP-28 ] 7 页

IDT

 		5T9070PAGI8 [ Low Skew Clock Driver, 5T Series, 10 True Output(s), 0 Inverted Output(s), CMOS, PDSO48, GREEN, TSSOP-48 ] 9 页

IDT

 		5T9070PAI [ Clock Driver, CMOS, PDSO48 ] 9 页

IDT

 		5T9070PAI8 [ Clock Driver, CMOS, PDSO48 ] 9 页

IDT

 		5T907PAI [ Clock Driver, 5T Series, 10 True Output(s), 0 Inverted Output(s), CMOS, PDSO48, TSSOP-48 ] 19 页

IDT

 		5T907PAI8 [ Clock Driver, PDSO48 ] 19 页

IDT

 		5T9110BBGI8 [ PLL Based Clock Driver, 5T Series, 5 True Output(s), 0 Inverted Output(s), PBGA144, GREEN, PLASTIC, BGA-144 ] 23 页

IDT

 		5T915PAI [ Clock Driver, CMOS, PDSO48 ] 19 页

IDT

 		5T915PAI8 [ Clock Driver, CMOS, PDSO48 ] 19 页

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