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5T9050PGI

型号:

5T9050PGI

品牌:

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数:

7 页

PDF大小:

148 K

2.5V SINGLE DATA RATE  
IDT5T9050  
1:5 CLOCK BUFFER  
TERABUFFER™ JR.  
DESCRIPTION:  
FEATURES:  
TheIDT5T90502.5Vsingledatarate(SDR)clockbufferisasingle-ended  
input to five single-ended outputs buffer built on advanced metal CMOS  
technology. TheSDRclockbufferfanoutfromasingleinputtofivesingle-ended  
outputsreducestheloadingontheprecedingdriverandprovidesanefficient  
clockdistributionnetwork. Multiplepowerandgroundsreducenoise.  
• Optimized for 2.5V LVTTL  
• Guaranteed Low Skew < 25ps (max)  
Very low duty cycle distortion < 300 (max)  
High speed propagation delay < 1.8ns. (max)  
Up to 200MHz operation  
Very low CMOS power levels  
Hot insertable and over-voltage tolerant inputs  
• 1:5 fanout buffer  
• 2.5V VDD  
Available in TSSOP package  
APPLICATIONS:  
• Clock and signal distribution  
FUNCTIONALBLOCKDIAGRAM  
GL  
G
OUTPUT  
CONTROL  
Q1  
OUTPUT  
CONTROL  
Q2  
A
OUTPUT  
Q3  
CONTROL  
OUTPUT  
CONTROL  
Q4  
OUTPUT  
CONTROL  
Q5  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
OCTOBER 2008  
1
© 2002 Integrated Device Technology, Inc.  
DSC-5958/19  
IDT5T9050  
2.5VSINGLEDATARATE1:5CLOCKBUFFERTERABUFFERJR.  
INDUSTRIALTEMPERATURERANGE  
PINCONFIGURATION  
ABSOLUTEMAXIMUMRATINGS(1)  
Symbol  
VDD  
VI  
Description  
Max  
–0.5 to +3.6  
–0.5 to +3.6  
–0.5 to VDD +0.5  
–65 to +165  
150  
Unit  
V
Power Supply Voltage  
Input Voltage  
V
GL  
VDD  
GND  
G
1
GND  
VDD  
GND  
GND  
VDD  
Q2  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
VO  
Output Voltage  
V
2
TSTG  
TJ  
Storage Temperature  
Junction Temperature  
° C  
° C  
3
4
NOTE:  
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause  
permanent damage to the device. This is a stress rating only and functional operation  
of the device at these or any other conditions above those indicated in the operational  
sections of this specification is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect reliability.  
VDD  
Q1  
5
6
GND  
A
7
GND  
Q3  
8
Q5  
9
Q4  
VDD  
GND  
VDD  
VDD  
NC  
10  
11  
12  
13  
14  
VDD  
GND  
GND  
VDD  
NC  
CAPACITANCE(1) (TA = +25°C, F = 1.0MHz)  
Symbol  
Parameter  
Min  
Typ.  
Max.  
Unit  
CIN  
Input Capacitance  
6
pF  
NOTE:  
1. This parameter is measured at characterization but not tested.  
TSSOP  
TOP VIEW  
RECOMMENDEDOPERATINGRANGE  
Symbol  
Description  
Min.  
–40  
2.3  
Typ.  
+25  
2.5  
Max.  
+85  
2.7  
Unit  
° C  
V
TA  
AmbientOperatingTemperature  
InternalPowerSupplyVoltage  
VDD  
PINDESCRIPTION  
Symbol  
I/O  
Type  
Description  
A
I
I
LVTTL  
LVTTL  
Clockinput  
G
Gate control for Qn outputs. When G is LOW, these outputs are enabled. When G is HIGH, these outputs are asynchronously  
disabledtotheleveldesignatedbyGL .  
(1)  
GL  
Qn  
I
LVTTL  
LVTTL  
PWR  
Specifies output disable level. If HIGH, the outputs disable HIGH. If LOW, the outputs disable LOW.  
O
Clockoutputs  
VDD  
Powersupplyforthedevicecore,inputs,andoutputs  
Powersupplyreturnforpower  
GND  
PWR  
NOTE:  
1. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize the possibility of runt  
pulses or be able to tolerate them in down stream circuitry.  
2
IDT5T9050  
2.5VSINGLEDATARATE1:5CLOCKBUFFERTERABUFFERJR.  
INDUSTRIALTEMPERATURERANGE  
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE(1)  
Symbol  
IIH  
Parameter  
Input HIGH Current  
InputLOWCurrent  
ClampDiodeVoltage  
DCInputVoltage  
Test Conditions  
Min.  
Typ.(4)  
Max  
±5  
Unit  
VDD = 2.7V  
VDD = 2.7V  
VI = VDD/GND  
VI = GND/VDD  
μA  
IIL  
±5  
VIK  
VDD = 2.3V, IIN = -18mA  
- 0.7  
- 1.2  
+3.6  
V
V
V
V
V
V
V
V
VIN  
- 0.3  
1.7  
(2)  
VIH  
DC Input HIGH  
(3)  
VIL  
DC Input LOW  
0.7  
VOH  
OutputHIGHVoltage  
OutputLOWVoltage  
IOH = -12mA  
IOH = -100μA  
IOL = 12mA  
IOL = 100μA  
VDD - 0.4  
VDD - 0.1  
VOL  
0.4  
0.1  
NOTES:  
1. See RECOMMENDED OPERATING RANGE table.  
2. Voltage required to maintain a logic HIGH.  
3. Voltage required to maintain a logic LOW.  
4. Typical values are at VDD = 2.5V, +25°C ambient.  
POWERSUPPLYCHARACTERISTICS  
Symbol  
Parameter  
Test Conditions(1)  
Typ.  
Max  
Unit  
IDDQ  
Quiescent VDD Power Supply Current  
VDD = Max., Reference Clock = LOW  
Outputsenabled,Alloutputsunloaded  
VDD = Max., CL = 0pF  
1
1.5  
mA  
IDDD  
ITOT  
Dynamic VDD Power Supply  
CurrentperOutput  
100  
150  
μA/MHz  
Total Power VDD Supply Current  
VDD = 2.5V., FREFERENCE CLOCK = 100MHz, CL = 15pF  
VDD = 2.5V., FREFERENCE CLOCK = 200MHz, CL = 15pF  
50  
75  
65  
mA  
100  
NOTE:  
1. The termination resistors are excluded from these measurements.  
INPUT AC TEST CONDITIONS  
Symbol  
VIH  
Parameter  
Value  
Units  
Input HIGH Voltage  
InputLOWVoltage  
VDD  
0
V
V
VIL  
(1)  
VTH  
InputTimingMeasurementReferenceLevel  
InputSignalEdgeRate(2)  
VDD/2  
2
V
tR,tF  
V/ns  
NOTES:  
1. A nominal 1.25V timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE) environment.  
2. The input signal edge rate of 2V/ns or greater is to be maintained in the 10% to 90% range of the input waveform.  
3
IDT5T9050  
2.5VSINGLEDATARATE1:5CLOCKBUFFERTERABUFFERJR.  
INDUSTRIALTEMPERATURERANGE  
ACELECTRICALCHARACTERISTICSOVEROPERATINGRANGE(4)  
Symbol  
Parameter  
Min.  
Typ.  
Max  
Unit  
SkewParameters  
(1)  
tSK(O)  
Same Device Output Pin-to-Pin Skew  
25  
ps  
ps  
ps  
(2)  
tSK(P)  
Pulse Skew  
300  
300  
(3)  
tSK(PP)  
Part-to-PartSkew  
PropagationDelay  
tPLH  
tPHL  
tR  
PropagationDelayAtoQn  
1.8  
ns  
Output Rise Time (20% to 80%)  
Output Fall Time (20% to 80%)  
FrequencyRange  
350  
350  
850  
850  
200  
ps  
ps  
tF  
fO  
MHz  
OutputGateEnable/DisableDelay  
tPGE  
OutputGateEnabletoQn  
OutputGateEnabletoQnDriventoGLDesignatedLevel  
3.5  
3
ns  
ns  
tPGD  
NOTES:  
1. Skew measured between all outputs under identical input and output transitions and load conditions on any one device.  
2. Skew measured is the difference between propagation delay times tPHL and tPLH of any output under identical input and output transitions and load conditions on any one device.  
3. Skew measured is the magnitude of the difference in propagation times between any outputs of two devices, given identical transitions and load conditions at identical VDD levels  
and temperature.  
4. Guaranteed by design.  
ACTIMING WAVEFORMS  
1/fo  
tW  
tW  
VIH  
VTH  
VIL  
A
Qn  
Qm  
tPHL  
tPLH  
VOH  
VTH  
VOL  
tSK(O)  
tSK(O)  
VOH  
VTH  
VOL  
Propagation and Skew Waveforms  
NOTE: Pulse Skew is calculated using the following expression:  
tSK(P) = | tPHL - tPLH |  
where tPHL and tPLH are measured on the controlled edges of any one output from rising and falling edges of a single pulse. Please note that the tPHL and tPLH shown are not  
valid measurements for this calculation because they are not taken from the same pulse.  
4
IDT5T9050  
2.5VSINGLEDATARATE1:5CLOCKBUFFERTERABUFFERJR.  
INDUSTRIALTEMPERATURERANGE  
VIH  
VTH  
VIL  
A
VIH  
VTH  
VIL  
GL  
tPLH  
VIH  
VTH  
VIL  
G
tPGD  
tPGE  
VOH  
VTH  
VOL  
Qn  
Gate Disable/Enable Showing Runt Pulse Generation  
NOTE:  
As shown, it is possible to generate runt pulses on gate disable and enable of the outputs. It is the user's responsibility to time their G signal to avoid this problem.  
5
IDT5T9050  
2.5VSINGLEDATARATE1:5CLOCKBUFFERTERABUFFERJR.  
INDUSTRIALTEMPERATURERANGE  
TEST CIRCUIT AND CONDITIONS  
VDD  
VDD  
VDD  
R1  
R1  
3 inch, ~50Ω  
Transmission Line  
D.U.T.  
VIN  
Pulse  
A
Qn  
Generator  
R2  
R2  
CL  
Test Circuit for Input/Output  
INPUT/OUTPUTTESTCONDITIONS  
Symbol  
VTH  
R1  
VDD = 2.5V ± 0.2V  
Unit  
V
VDD / 2  
100  
Ω
R2  
100  
Ω
CL  
15  
pF  
6
IDT5T9050  
2.5VSINGLEDATARATE1:5CLOCKBUFFERTERABUFFERJR.  
INDUSTRIALTEMPERATURERANGE  
ORDERINGINFORMATION  
XX  
X
XXXXX  
Package Package  
Device Type  
I
-40°C to +85°C (Industrial)  
PG  
PGG  
Thin Shrink Small Outline Package  
TSSOP - Green  
2.5V Single Data Rate 1:5 Clock Buffer  
Terabuffer Jr.  
5T9050  
CORPORATE HEADQUARTERS  
6024 Silver Creek Valley Road  
San Jose, CA 95138  
for SALES:  
800-345-7015 or 408-284-8200  
fax: 408-284-2775  
www.idt.com  
for Tech Support:  
clockhelp@idt.com  
7
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