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XWM8716EDS/R

型号：

XWM8716EDS/R

品牌：

CIRRUS[ CIRRUS LOGIC ]

页数：

26 页

PDF大小：

424 K

下载PDF手册
WM8716  
w
High Performance 24-bit, 192kHz Stereo DAC  
DESCRIPTION  
FEATURES  
•
112dB SNR (‘A’ weighted @ 48kHz), THD: -97dB @  
-1dB FS  
The WM8716 is a high performance stereo DAC designed  
for audio applications such as CD, DVD, home theatre  
systems, set top boxes and digital TV. The WM8716  
supports data input word lengths from 16 to 24-bits and  
sampling rates up to 192kHz. The WM8716 consists of a  
serial interface port, digital interpolation filter, multi-bit sigma  
delta modulator and stereo DAC in a small 28-pin SSOP  
package. The WM8716 also includes a digitally controllable  
mute and attenuator function on each channel.  
•
•
•
•
•
•
Sampling frequency: 8kHz to 192kHz  
Selectable digital filter roll-off  
Optional interface to industry standard external filters  
Differential mono mode  
Input data word: 16 to 24-bit  
Hardware or SPI compatible serial port control modes:  
−
Hardware mode: mute, de-emphasis, audio format  
control  
The internal digital filter has two selectable roll-off  
characteristics. A sharp or slow roll-off can be selected  
dependent on application requirements. Additionally, the  
internal digital filter can be by-passed and the WM8716  
used with an external digital filter.  
−
Serial mode: mute, de-emphasis, attenuation (256  
steps), phase reversal  
•
Compatible upgrade to PCM1716  
The WM8716 supports two connection schemes for audio  
DAC control. The SPI-compatible serial control port  
provides access to a wide range of features including on-  
chip mute, attenuation and phase reversal. A hardware  
controllable interface is also available.  
APPLICATIONS  
•
•
•
•
CD, DVD audio  
Home theatre systems  
Set top boxes  
Digital TV  
BLOCK DIAGRAM  
WOLFSON MICROELECTRONICS plc  
Production Data, May 2004, Rev 4.0  
2004 Wolfson Microelectronics plc  
www.wolfsonmicro.com  
WM8716  
Production Data  
TABLE OF CONTENTS  
DESCRIPTION .......................................................................................................1  
FEATURES.............................................................................................................1  
APPLICATIONS .....................................................................................................1  
BLOCK DIAGRAM .................................................................................................1  
TABLE OF CONTENTS .........................................................................................2  
PIN CONFIGURATION...........................................................................................3  
ORDERING INFORMATION ..................................................................................3  
ABSOLUTE MAXIMUM RATINGS.........................................................................4  
RECOMMENDED OPERATING CONDITIONS .....................................................4  
ELECTRICAL CHARACTERISTICS ......................................................................5  
TERMINOLOGY............................................................................................................ 6  
PIN DESCRIPTION ................................................................................................7  
DEVICE DESCRIPTION.........................................................................................9  
SYSTEM CLOCK .......................................................................................................... 9  
AUDIO DATA INTERFACE ..................................................................................10  
NORMAL SAMPLE RATE ........................................................................................... 10  
8 X FS INPUT SAMPLE RATE.................................................................................... 11  
MODES OF OPERATION ........................................................................................... 12  
HARDWARE CONTROL MODES ............................................................................... 12  
SOFTWARE CONTROL INTERFACE......................................................................... 13  
REGISTER MAP ......................................................................................................... 13  
MUTE MODES ............................................................................................................ 18  
FILTER RESPONSES................................................................................................. 19  
APPLICATIONS INFORMATION .........................................................................22  
RECOMMENDED EXTERNAL COMPONENTS.......................................................... 22  
RECOMMENDED EXTERNAL COMPONENTS VALUES........................................... 22  
PACKAGE DIMENSIONS ....................................................................................25  
IMPORTANT NOTICE..........................................................................................26  
ADDRESS: .................................................................................................................. 26  
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PD Rev 4.0 May 2004  
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Production Data  
WM8716  
PIN CONFIGURATION  
ML/I2S  
MC/DM1  
MD/DM0  
MUTEB  
MODE  
LRCIN  
DIN  
1
2
3
4
5
6
7
8
9
10  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
BCKIN  
CLKO  
XTI  
XTO  
CSBIWO  
RSTB  
DGND  
DVDD  
AVDDR  
AGNDR  
VMIDR  
ZERO  
AVDDL  
AGNDL  
VMIDL  
DIFFHW  
VOUTL  
AVDD  
11  
12  
13  
14  
MODE8X  
VOUTR  
AGND  
ORDERING INFORMATION  
MOISTURE  
SENSITIVITY  
TEMPERATURE  
PEAK SOLDERING  
TEMPERATURE  
DEVICE  
RANGE  
PACKAGE  
LEVEL  
28-pin SSOP  
XWM8716EDS  
XWM8716EDS/R  
WM8716SEDS  
WM8716SEDS/R  
-25 to +85°C  
-25 to +85°C  
-25 to +85°C  
-25 to +85°C  
MSL1  
240°C  
240°C  
260°C  
260°C  
28-pin SSOP  
(tape and reel)  
MSL1  
MSL1  
MSL1  
28-pin SSOP  
(lead free)  
28-pin SSOP  
(lead free, tape and reel)  
Note:  
Reel quantity = 2,000  
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PD Rev 4.0 May 2004  
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WM8716  
Production Data  
ABSOLUTE MAXIMUM RATINGS  
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at  
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical  
Characteristics at the test conditions specified.  
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine  
acceptable storage conditions prior to surface mount assembly. These levels are:  
MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag.  
MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.  
MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.  
CONDITION  
MIN  
MAX  
Supply voltage  
-0.3V  
+7.0V  
Reference input  
VDD + 0.3V  
Operating temperature range, TA  
Storage temperature  
°
°
+85 C  
-25 C  
°
°
+150 C  
-65 C  
RECOMMENDED OPERATING CONDITIONS  
PARAMETER  
SYMBOL  
DVDD  
TEST CONDITIONS  
MIN  
TYP  
3.3 to 5  
3.3 to 5  
0
MAX  
UNIT  
V
Digital supply range  
Analogue supply range  
Ground  
-10%  
-10%  
+10%  
+10%  
AVDD  
V
AGND, DGND  
V
Difference DGND to AGND  
Analogue supply current  
Digital supply current  
Analogue supply current  
Digital supply current  
-0.3  
0
+0.3  
40  
V
AVDD = 5V  
DVDD = 5V  
AVDD = 3.3V  
DVDD = 3.3V  
26  
mA  
mA  
mA  
mA  
22  
35  
25  
13  
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Production Data  
WM8716  
ELECTRICAL CHARACTERISTICS  
TEST CONDITIONS  
AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
DAC Circuit Specifications  
SNR (See Notes 1 and 2)  
THD (full-scale)  
105  
112  
-92  
-97  
112  
dB  
dB  
dB  
dB  
0dB FS  
-1dB FS  
(See Note 2)  
Dynamic range  
(See Note 2)  
THD @ -60dB FS  
105  
Filter Characteristics (Sharp Roll-off)  
Passband  
0.0012 dB  
-3dB  
0.4535fs  
dB  
Stopband  
0.491fs  
30/fs  
Passband ripple  
0.0012  
0.001  
dB  
dB  
s
Stopband Attenuation  
Delay time  
f > 0.5465fs  
-82  
Filter Characteristics (Slow Roll-off)  
Passband  
0.001dB  
-3dB  
0.274fs  
0.459fs  
Stopband  
Passband ripple  
dB  
dB  
s
Stopband Attenuation  
Delay time  
f > 0.732fs  
-82  
9/fs  
Internal Analogue Filter  
Bandwidth  
-3dB  
195  
kHz  
dB  
Passband edge response  
Digital Logic Levels  
20kHz  
-0.043  
Input LOW level  
Input HIGH level  
(See Note 3)  
VIL0.8  
VIH  
2.0  
V
V
Output LOW level  
Output HIGH level  
VOL  
VOH  
IOL = 2mA  
IOH = 2mA  
AVSS + 0.3V  
AVDD - 0.3V  
Analogue Output Levels  
Output level  
Into 10kohm, full scale 0dB,  
(5V supply)  
Into 10kohm, full scale 0dB,  
(3.3V supply)  
To midrail or AC coupled  
(5V supply)  
1.1  
0.72  
1
VRMS  
VRMS  
Minimum resistance load  
kohms  
ohms  
To midrail or AC coupled  
(3.3V supply)  
600  
Maximum capacitance load  
Output DC level  
5V or 3.3V  
100  
AVDD/2  
0.5  
pF  
V
Gain mismatch channel to  
channel  
2
%FSR  
Reference Levels  
Potential divider resistance  
10  
kohms  
AVDD to VMIDL/VMIDR and  
VMIDL/VMIDR to AGND  
Voltage at VMIDL/VMIDR  
POR  
AVSS/2  
2.5V  
POR threshold  
V
Notes:  
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PD Rev 4.0 May 2004  
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WM8716  
Production Data  
1. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’  
weighted over a 20Hz to 20kHz bandwidth.  
2. All performance measurements done with 20kHz low pass filter. Failure to use such a filter will result in higher THD+N  
and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter  
removes out of band noise; although it is not audible it may affect dynamic specification values.  
3. Except for Pin 12 (MODE8X) and Pin 17 (DIFFHW), where VIH = 2.6V min.  
TERMINOLOGY  
1. Signal-to-noise ratio (dB) (SNR) is a measure of the difference in level between the full-scale output and the output  
with no signal applied.  
2. Dynamic range (dB) (DNR) is a measure of the difference between the highest and lowest portions of a signal.  
Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB  
to it. (eg THD+N @ -60dB= -32dB, DR= 92dB).  
3. THD+N (dB) is a ratio of the r.m.s. values, of (Noise + Distortion)/Signal.  
4. Stop band attenuation (dB) is the degree to which the frequency spectrum is attenuated (outside audio band).  
5. Channel Separation (dB) (also known as Cross-Talk) is a measure of the amount one channel is isolated from the  
other. Normally measured by sending a full-scale signal down one channel and measuring the other.  
6. Pass-Band Ripple - Any variation of the frequency response in the pass-band region.  
LRCIN  
tBCH  
tBCL  
tLB  
BCKIN  
DIN  
tBCY  
tBL  
tDS  
tDH  
Figure 1 Audio Data Input Timing  
TEST CONDITIONS  
AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Audio Data Input Timing Information  
BCKIN pulse cycle time  
BCKIN pulse width high  
BCKIN pulse width low  
tBCY  
tBCH  
tBCL  
tBL  
100  
50  
ns  
ns  
ns  
ns  
50  
BCKIN rising edge  
to LRCIN edge  
30  
LRCIN rising edge  
tLB  
30  
ns  
to BCKIN rising edge  
DIN setup time  
DIN hold time  
tDS  
tDH  
30  
30  
ns  
ns  
tSCKIL  
SCKI  
tSCKIH  
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Production Data  
WM8716  
Figure 2 System Clock Timing Requirements  
TEST CONDITIONS  
AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
System Clock Timing Information  
SCKI System clock pulse width high  
SCKI System clock pulse width low  
tSCKIH  
tSCKIL  
13  
13  
ns  
ns  
tMLL  
tMHH  
ML/I2S (PIN 28)  
MC/DM1 (PIN 27)  
MD/DM0 (PIN 26)  
CSBIWO (PIN 23)  
tMCY  
tMCH  
tMCL  
tMLH  
tMLS  
tMDS  
tMDH  
LSB  
tCSML  
tMLCS  
Figure 3 Program Register Input Timing  
TEST CONDITIONS  
AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Program Register Input Information  
MC/DM1 Pulse cycle time  
MC/DM1 Pulse width LOW  
MC/DM1 Pulse width HIGH  
MD/DM0 Hold time  
tMCY  
tMCL  
tMCH  
tMDH  
tMDS  
tMLL  
100  
40  
40  
40  
40  
ns  
ns  
ns  
ns  
ns  
ns  
MD/DM0 Set-up time  
ML/I2S Low level time  
(See Note 3)  
40 +  
1SYSCLK  
ML/I2S High level time  
(See Note 3)  
tMHH  
40 +  
1SYSCLK  
ns  
ML/I2S Hold time  
tMLH  
tMLS  
tCSML  
tMLCS  
40  
40  
10  
10  
ns  
ns  
ns  
ns  
ML/I2S Set-up time  
CSBIWO Low to ML/I2S low time  
ML/I2S High to CSBIWO high time  
Note:  
3.  
System clock cycle.  
PIN DESCRIPTION  
PIN  
NAME  
TYPE  
DESCRIPTION  
Hardware Mode  
Normal Mode  
Software  
Mode  
Differential Mode  
8X Mode  
1
LRCIN  
Digital input  
Sample rate clock input.  
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PD Rev 4.0 May 2004  
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WM8716  
Production Data  
PIN  
NAME  
TYPE  
DESCRIPTION  
Hardware Mode  
Normal Mode  
Software  
Mode  
Differential Mode  
8X Mode  
2
DIN  
Digital input  
Audio data serial input  
DINL  
Audio data  
serial input  
3
BCKIN  
CLKO  
Digital input  
Digital output  
Analogue input  
Analogue output  
Supply  
Audio data bit clock input.  
4
Oscillator buffered output (system clock).  
Oscillator input.  
5
XTI  
6
XTO  
Oscillator output.  
7
DGND  
DVDD  
Digital ground supply.  
8
Supply  
Digital positive supply.  
9
AVDDR  
AGNDR  
VMIDR  
MODE8X  
VOUTR  
AGND  
AVDD  
Supply  
Analogue positive supply.  
Analogue ground supply.  
Mid rail right channel.  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
Supply  
Analogue output  
Digital input  
Analogue output  
Supply  
Internal pull-down, active high, 8 x fs mode.  
Right channel DAC output.  
Analogue ground supply.  
Analogue positive supply.  
Left channel DAC output.  
Supply  
VOUTL  
DIFFHW  
VMIDL  
AGNDL  
AVDDL  
ZERO  
Analogue output  
Digital input  
Analogue output  
Supply  
Internal pull-down, active high, differential mono mode  
Mid rail left channel.  
Analogue ground supply.  
Supply  
Analogue positive supply.  
Digital output  
Digital input  
Infinite zero detect – active low. Open drain type output with active pull-down.  
Reset input – active low. Internal pull-up.  
RSTB  
CSBIWO  
Digital input  
Internal pull-down  
Wordlength:  
Wordlength:  
Wordlength:  
Low for  
serial  
interface  
operation.  
Low for 16-bit data.  
Low for 16-bit data.  
Low for 20-bit data.  
High for 24-bit data.  
High for 20-bit  
(normal) or 24-bit  
I2S data.  
High for 20-bit  
(normal) or 24-bit  
I2S data.  
24  
25  
MODE  
Digital input  
Internal pull-up  
Low for hardware  
mode.  
Low for left  
mono mode. High for  
right mono mode  
DINR  
High for  
software  
mode.  
MUTEB  
Digital input  
Internal pull-up  
Low to soft mute.  
Low to soft mute.  
Low to soft mute.  
Low to soft  
mute.  
High for normal  
operation.  
High for normal  
operation.  
High for normal  
operation.  
High for  
normal  
operation.  
Z for automute.  
Z for automute.  
Z for automute.  
Z for  
automute.  
26  
27  
28  
MD/DM0  
MC/DM1  
ML/I2S  
Digital input  
Internal pull-up  
De-emphasis mode  
select bit 0.  
Low for no  
de-emphasis.  
LRP – LRCLK  
polarity select.  
Control serial  
interface  
data signal.  
High for 44.1kHz  
de-emphasis.  
Digital input  
Internal pull-up  
De-emphasis mode  
select bit 1.  
Low for normal filter  
operation.  
Unused.  
Control serial  
interface  
clock signal.  
Leave unconnected.  
High for filter slow  
roll-off.  
Digital input  
Internal pull-up  
Audio serial format:  
Low – right justified.  
High – I2S.  
Audio serial format:  
Low – right justified.  
High – I2S.  
Input data format:  
Low – right justified.  
High – left justified.  
Control serial  
interface  
load signal.  
Note: Digital input pins have Schmitt trigger input buffers except Pin 12 and Pin 17.  
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PD Rev 4.0 May 2004  
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Production Data  
WM8716  
DEVICE DESCRIPTION  
The WM8716 is a high performance 128fs oversampling rate stereo DAC employing a novel 64 level  
sigma delta DAC design which provides optimised signal-to-noise performance and clock jitter  
tolerance. It is ideally suited to high quality audio applications such as CD, DVD-audio, home theatre  
receivers and professional mixing consoles. The WM8716 supports sample rates from 8ks/s to  
192ks/s.  
The control functions of the WM8716 are either pin selected (hardware mode) or programmed via the  
serial interface (software mode). Control functions that are available include: data input word length  
and format selection (16-24 bits: I2S, left justified or right justified): de-emphasis sample rate  
selection (48kHz, 44.1kHz and 32kHz); differential output modes; a software or hardware mute and  
independently digitally controllable attenuation on both channels.  
The digital filtering may be bypassed entirely by selecting MODE8X. Data is then input directly to the  
DAC, bypassing the digital filters. Left and right channels are input separately, using the MODE pin  
as the right channel input. This mode allows the use of alternative digital filters, such as the Pacific  
Microsonics PMD100 HDCD filter.  
In addition to the normal stereo operating mode the WM8716 may also be used in dual differential  
mode with either the left or right channel (selectable) being output differentially. Two WM8716s can  
then be used in parallel to implement a stereo channel, each supporting a single channel  
differentially. This mode is available in both software and hardware modes and may also be used in  
conjunction with MODE8X.  
SYSTEM CLOCK  
Sample rates from 8ks/s up to 96ks/s are available, and automatically selected, with a system clock  
of 256fs, 384fs, 512fs or 768fs. In addition a system clock of 128fs or 192fs may be used, with  
sample rates up to 192ks/s. With a 128fs or 192fs system clock 64x oversampling mode operation is  
automatically selected and the first stage of the digital filter is bypassed.  
WM8716 has an asynchronous monitor circuit, which in the event of removal of the master system  
clock, resets the digital filters and analogue circuits, muting the output. Re-application of the system  
clock re-starts the filters from an intitialised state. Control registers are not reset under this condition.  
The WM8716 is tolerant of asynchronous bit clock jitter. The internal signal processing  
resynchronises to the external LRCIN once the phase difference between bit clock and the system  
clock exceeds half an LRCIN period. During this re-synch period the interpolating filters will either  
miss or repeat an audio sample, minimising the audible effects of the operation. Table 1 shows the  
typical system clock frequency inputs for the WM8716.  
SAMPLING  
RATE  
SYSTEM CLOCK FREQUENCY (MHZ)  
128fs  
192fs  
256fs  
384fs  
512fs  
768fs  
(LRCIN)  
32kHz  
44.1kHz  
48kHz  
4.096  
5.6448  
6.114  
12.288  
24.576  
6.144  
8.467  
8.192  
11.2896  
12.288  
24.576  
12.288  
16.9340  
18.432  
36.864  
16.384  
22.5792  
24.576  
24.576  
33.8688  
36.864  
9.216  
18.432  
36.864  
96kHz  
Unavailable Unavailable  
192kHz  
Unavailable Unavailable Unavailable Unavailable  
Table 1 System Clock Frequencies Versus Sampling Rate  
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WM8716  
Production Data  
AUDIO DATA INTERFACE  
Data may be input at a rate corresponding to the system clock having a rate of 256fs or 384fs or  
512fs or 768fs, in which case an oversampling ratio of 128x is selected. Alternatively a rate of 128fs  
or 192fs may be used, in which case the first filter stage is bypassed and an oversampling ratio of  
64x results. Finally, in MODE8X, data may be input at 8x the normal rate, in which case separate  
input pins are used to input the two stereo channels of data (unless DIFFHW mode and MODE8X  
are both selected, in which case only a mono channel is converted differentially). In MODE8X all filter  
stages are by-passed, prior to the sigma delta modulator. Data is input MSB first in all modes.  
NORMAL SAMPLE RATE  
In normal mode, the data is input serially on one pin for both left and right channels.  
Data can be “right justified” meaning that the last 16, 20 or 24 bits (depending on chosen PCM word  
length) that were clocked in prior to the transition on LRCIN are valid.  
Alternatively data can be “left justified” (20 and 24-bit PCM data only), where the bits are clocked in  
as the first 20 or 24 bits after a transition on LRCIN.  
For the three I2S modes supported (16-bit, 20-bit and 24-bit PCM data), data is clocked “left justified”  
except with one additional preceding clock cycle.  
1/fs  
LEFT  
RIGHT  
LRCIN (PIN 1)  
BCKIN (PIN 3)  
16-BIT RIGHT  
JUSTIFIED  
DIN (PIN 2)  
B2 B1 B0  
B2 B1 B0  
B2 B1 B0  
B0  
B15  
B2 B1 B0  
B2 B1 B0  
B2 B1 B0  
B15  
B2 B1 B0  
B2 B1 B0  
B2 B1 B0  
20-BIT RIGHT  
JUSTIFIED  
DIN (PIN 2)  
B19 B18 B17  
B19 B18 B17  
24-BIT RIGHT  
JUSTIFIED  
DIN (PIN 2)  
B23 B22 B21 B20 B19  
B23 B22 B21 B20 B19  
24-BIT LEFT  
JUSTIFIED  
DIN (PIN 2)  
B23 B22 B21  
B4 B3 B2 B1 B0  
B23 B22 B21  
B4 B3 B2 B1 B0  
20-BIT LEFT  
JUSTIFIED  
DIN (PIN 2)  
B0  
B19 B18 B17  
B0  
B19 B18 B17  
B0  
LEFT  
RIGHT  
LRCIN (PIN 1)  
BCKIN (PIN 3)  
16-BIT I2S  
DIN (PIN 2)  
B15  
B23  
B19  
B2 B1 B0  
B15  
B23  
B19  
B2 B1 B0  
B15  
B23  
B19  
24-BIT I2S  
DIN (PIN 2)  
B6 B5 B4 B3 B2 B1 B0  
B6 B5 B4 B3 B2 B1 B0  
20-BIT I2S  
DIN (PIN 2)  
B2 B1 B0  
B2 B1 B0  
Figure 4 Audio Data Input Format  
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WM8716  
8 X FS INPUT SAMPLE RATE  
Due to the higher speed of the interface in 8 x fs mode, audio data is input on two pins. The MODE  
pin (pin 24) is used as the second input for the right channel data and left data is input on DIN (pin 2).  
In this mode, software control of the device is not available. The data can be input in two formats, left  
or right justified, selectable by ML/I2S and two word lengths (20 or 24 bit), selectable by CSBIWO. In  
both modes the data is always clocked in MSB first.  
For left justified data the word start is marked by the falling edge of LRCIN. The data is clocked in on  
the next 20/24 BCKIN rising edges. This format is compatible with devices such as the PMD100.  
For right justified the data is justified to the rising edge of LRCIN and the data is clocked in on the  
preceding 20/24 BCKIN rising edges before the LRCIN rising edge. This format is compatible with  
devices such as the DF1704 or SM5842.  
In both modes the polarity of LRCIN can be switched using MD/DM0.  
Differential hardware mode can be used in conjunction with 8fs mode by setting the DIFFHW  
pin high. In differential 8fs mode the data is input on DIN and output differentially. MODE is unused  
and must be tied low.  
1/8fs  
LRCIN (PIN 1)  
BCKIN (PIN 3)  
LEFT AUDIO  
B23  
B23  
B22 B21 B20  
B19  
B19  
B2  
B2  
B1  
B1  
B0  
B0  
B23 B22  
B23 B22  
B21  
B21  
B20  
B20  
DATA DIN  
(PIN 2)  
RIGHT AUDIO  
DATA MODE  
(PIN 24)  
B22 B21 B20  
1/8fs  
LRCIN (PIN 1)  
BCKIN (PIN 3)  
LEFT AUDIO  
DATA DIN  
(PIN 2)  
B23  
B23  
B22  
B22  
B21 B20  
B21 B20  
B19  
B19  
B2  
B2  
B1  
B1  
B0  
B0  
RIGHT AUDIO  
DATA MODE  
(PIN 24)  
Figure 5 Audio Data Input Format (8 x fs Operation)  
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MODES OF OPERATION  
Control of the various modes of operation is either by software control over the serial interface, or  
by hard-wired pin control. Selection of software or hardware mode is via MODE pin. The following  
functions may be controlled either via the serial control interface or by hard wiring of the  
appropriate pins.  
HARDWARE CONTROL MODES  
When the MODE pin is held ‘low’ the following hardware modes of operation are available. In  
Hardware differential mode or 8X mode some of these modes/control words are altered or  
unavailable.  
DE-EMPHASIS CONTROL  
MDDM1  
MCDMO  
DE-EMPHASIS  
PIN 27  
PIN 26  
L
L
H
L
Off  
L
48kHz  
44.1kHz  
32kHz  
H
H
H
Table 2 De-Emphasis Control  
AUDIO INPUT FORMAT  
CSBIIS  
CSBIWO  
DATA FORMAT  
PIN 28  
PIN 23  
L
L
H
L
16 bit normal right justified  
20 bit normal right justified  
16 bit I2S  
L
H
H
H
24 bit I2S  
Table 3 Audio Input Format  
SOFT MUTE  
MUTEB  
FUNCTION  
PIN 25  
L
Mute On (no output)  
Automute  
Z
H
Mute Off (normal operation)  
Table 4 Soft Mute  
A logic low on the MUTEB pin will cause the attenuation to ramp to infinite attenuation at a rate of  
128/fs seconds per 0.5dB step. Setting MUTEB high will cause the attenuation to ramp back to its  
previous value.  
Leaving MUTEB undriven allows operation of the automute circuit in both hardware and software  
modes. On receiving 1024 consecutive zero value audio samples, the analogue stage output mute is  
asserted. This may be overdriven from the MUTEB pin to disable the automute function, or output as  
a weak (10kohm) output signal.  
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WM8716  
SOFTWARE CONTROL INTERFACE  
The WM8716 can be controlled using a 3-wire serial interface. MD/DM0 (pin 26) is used for the  
program data, MC/DM1 (pin 22) is used to clock in the program data and ML/I2S (pin 28) is use to  
latch in the program data. The 3-wire interface protocol is shown in Figure 6. CSB/IWO (pin 23) must  
be low when writing.  
ML/I2S (PIN 28)  
MC/DM1 (PIN 27)  
MD/DM0 (PIN 26)  
B15 B14 B13  
B2  
B1  
B0  
Figure 6 Three-Wire Serial Interface  
REGISTER MAP  
WM8716 controls the special functions using 4 program registers, which are 16-bits long. These  
registers are all loaded through input pin MD/DM0. After the 16 data bits are clocked in, ML/I2S is  
used to latch in the data to the appropriate register. Table 5 shows the complete mapping of the  
4 registers. Note that in hardware differential mode and 8X modes, software control is not available.  
The hardware differential mode (Diff[1:0]) clock loss detector disable (CDD) can only be accessed by  
writing to M2[8:5] with the pattern 1111. Register M4 is then accessible by setting A[2:0] to 110.  
B15  
B14  
B13  
B12  
B11  
B10  
B9  
B8  
B7  
AL7  
AR7  
-
B6  
AL6  
AR6  
-
B5  
AL5  
AR5  
-
B4  
AL4  
AR4  
IW1  
B3  
AL3  
AR3  
B2  
AL2  
AR2  
B1  
AL1  
AR1  
B0  
AL0  
AR0  
M0  
M1  
M2  
M3  
M4  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
A2 (0) A1(0) A0(0) LDL  
A2(0) A1(0) A0(1) LDR  
A2(0) A1(1) A0(0)  
A2(0) A1(1) A0(1) IZD  
A2(1) A1(1) A0(0)  
-
IW0 OPE DEM MUT  
SF1  
-
SF0  
CK0 REV SR0 ATC LRP  
I2S  
-
CDD DIFF1 DIFF0  
-
-
-
-
Table 5 Mapping of Program Registers  
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REGISTER  
BITS  
NAME  
AL[7:0]  
LDL  
DEFAULT  
DESCRIPTION  
0
[7:0]  
FF  
Attenuation data for left channel.  
Attenuation data load control for left channel.  
Attenuation data for right channel.  
Attenuation data load control for right channel.  
Left and right DACs soft mute control.  
De-emphasis control.  
8
[7:0]  
8
0
1
2
AR[7:0]  
LDR  
FF  
0
0
0
0
0
0
0
0
0
0
0
0
0
MUT  
DEM  
OPE  
IW[1:0]  
I2S  
1
2
Left and right DACs operation control.  
Input audio data bit select.  
Audio data format select.  
[4:3]  
0
3
1
LRP  
Polarity of LRCIN select.  
2
ATC  
Attenuator control.  
3
SR0  
Digital filter slow roll-off select.  
Output phase reverse.  
4
REV  
5
CKO  
SF[1:0]  
IZD  
CLKO frequency select.  
[7:6]  
8
Sampling rate select.  
0
Infinite zero detection circuit control.  
Differential output mode.  
4
[5:4]  
6
DIFF  
CDD  
0
0
Clock loss detector disable.  
Table 6 Register Bit Descriptions  
DAC OUTPUT ATTENUATION  
The level of attenuation for eight bit code X, is given by:  
0.5 ∗ (X - 255) dB, 1 ≤ X ≤ 255  
- ∞dB (mute),  
X = 0  
Bit 8 in register 0 (LDL) is used to control the loading of attenuation data in B[7:0]. When LDL is set  
to 0, attenuation data will be loaded into AL[7:0], but it will not affect the filter attenuation. LDR in  
register 1 has the same function for right channel attenuation. Only when LDL or LDR is set to '1' will  
the filter attenuation be updated. This permits left and right channel attenuation to be updated  
simultaneously.  
Attenuation level is controlled by AL[7:0] (left channel) or AR[7:0] (right channel). Attenuation levels  
are given in Table 4.  
X[7:0]  
00(hex)  
01(hex)  
:
ATTENUATION LEVEL  
- ∞dB (mute)  
-127.0dB  
:
:
:
FD(hex)  
FE(hex)  
FF(hex)  
-1.0dB  
-0.5dB  
0.0dB  
Table 7 Attenuation Control Level  
Bit 2 in Reg3 is used to control the attenuator (ATC). When ATC is “high”, the attenuation data  
loaded in program register 0 is used for both the left and the right channels. When ATC is low, the  
attenuation data for each register is applied separately to left and right channels.  
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WM8716  
SOFT MUTE  
MUT  
(REG2, B0)  
L
Soft Mute off (normal operation)  
Soft Mute on (no output)  
H
Table 8 Soft Mute  
Setting MUT causes the attenuation to ramp from the current value down to 00. The values held in  
the attenuation registers are unchanged. When MUT is reset the attenuation will ramp back up to the  
previous value. The ramp rate is 128/fs s/0.5dB step.  
DIGITAL DE-EMPHASIS  
DEM  
(REG2, B1)  
L
De-emphasis off  
De-emphasis on  
H
Table 9 Digital De-Emphasis  
DAC OPERATION ENABLE  
OPE  
(REG2,B2)  
L
Normal operation  
H
DAC output forced to bipolar zero,  
irrespective of input data.  
Table 10 DAC Operation Enable  
AUDIO DATA INPUT FORMAT  
I2S  
IW1  
IW0  
AUDIO INTERFACE  
(REG3, B0)  
(REG2, B4)  
(REG2, B3)  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
16-bit standard right justified  
20-bit standard right justified  
24-bit standard right justified  
24-bit left justified (MSB first)  
16-bit I2S  
24-bit I2S  
20-bit I2S  
20-bit left justified (MSB first)  
Table 11 Audio Data Input Format  
POLARITY OF LR INPUT CLOCK  
The left channel data for a particular sample instant is always input first, then the right channel data.  
LRP  
(REG3, B1)  
L
LR High – left channel  
LR Low – right channel  
LR Low – left channel  
LR High – right channel  
H
Table 12 Polarity of LR Input Clock  
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INDIVIDUAL OR COMMON ATTENUTATION CONTROL  
ATC  
(REG3, B2)  
L
Individual control  
H
Common control from Reg0  
Table 13 Individual or Common Attenuation Control  
DIGITAL FILTER ROLL-OFF SELECTION  
SRO  
(REG3, B3)  
L
Sharp  
Slow  
H
Table 14 Digital Filter Roll-Off Selection  
ANALOGUE OUTPUT POLARITY REVERSAL  
REV  
(REG3, B4)  
L
Normal  
H
Inverted  
Table 15 Analogue Output Polarity Reversal  
CLKO OUTPUT FREQUENCY  
CKO  
(REG3, B5)  
L
XTI  
H
XTI/2  
Table 16 CLKO Output Frequency  
DE-EMPHASIS SAMPLE RATE  
SF1  
SF0  
SAMPLE RATE  
(REG3, B7)  
(REG3, B6)  
0
0
1
1
0
1
0
1
No de-emphasis  
48kHz  
44.1kHz  
32kHz  
Table 17 De-Emphasis Sample Rate  
INFINITE ZERO DETECT  
IZD  
(REG3, B8)  
L
Zero detect mute off  
Zero detect mute on  
H
Table 18 Infinite Zero Detect  
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WM8716  
DIFFERENTIAL MONO MODE  
Using bits 4 and 5, the differential output mode may be selected to be one of normal stereo, reversed  
stereo, mono left or mono right, as shown in Table 19.  
DIFF[1:0]  
B[4:5])  
00  
DIFFERENTIAL OUTPUT MODE  
Stereo  
01  
Stereo reverse.  
10  
Mono left – differential outputs.  
VOUTL is left channel.  
VOUTR is the negative of left channel.  
Mono right – differential outputs.  
VOUTL is the negative right channel.  
VOUTR is right channel.  
11  
Table 19 Differential Output Modes  
Using these controls a pair of WM8716 devices may be used to build a ‘dual differential’ stereo  
implementation with higher performance and differential output.  
CLOCK LOSS DETECTOR DISABLE  
CDD (REG4, B6)  
L
Clock loss detector on  
Clock loss detector off  
R
Table 20 Clock Loss Detector Disable  
When the system clock is inactive for approximately 100µs, the clock loss detector circuit detects the  
loss of clock and the analogue circuitry is forced into a mute condition and the digital filters reset.  
Setting the CDD bit disables this behaviour.  
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WM8716  
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MUTE MODES  
The device has various mute modes.  
DIGITAL FILTER  
ANALOGUE  
ANRES  
ANMUTE  
Reg bit OPE = ‘1’  
MUTEB pin  
Unaffected  
Asserted  
Gain ramped to zero  
Asserted when  
gain = 0  
On release volume ramps  
to previous value  
AUTOMUTE  
Automute has no effect on digital  
filters  
Asserted after  
1024 zero input  
samples if IZD = 1  
(detect 1024 zero  
input samples)  
Reg bit MUT  
As MUTEB pin  
As MUTEB pin  
Asserted  
Gain = 00  
(left & right)  
Gain = -∞dB  
RAM initialise  
Gain initialised to 0dB  
Asserted  
Asserted  
Loss of system  
clock  
Not running (no clock). On clock  
restart, filters initialised, RAM  
initialised. Registers unchanged  
Asserted  
Asserted  
No LRCLK or invalid  
SCLK/LRCLK ratio  
Filters initialised, RAM initialised.  
Registers unchanged  
Asserted  
RB  
Reset – gain initialised to 0dB  
Reset  
Asserted  
Asserted  
Asserted  
Asserted  
Power-on reset  
Table 21 Mute Modes  
•
•
ANRES is the reset to the switched capacitor filter.  
ANMUTE is an analogue muting signal gating the analogue signal at the output (after the  
SC filter)  
•
•
AUTOMUTE is asserted when both the IZD register bit is asserted and the input audio data has  
been zero on both left and right channels for 1024 input samples. The first non-zero sample de-  
asserts.  
Applying a logic low to MUTEB or setting MUT in Reg2 causes the gain registers to ramp to zero.  
When a logic high is applied, the gain ramps slowly back up to the value held in the appropriate  
attenuation register (AL or AR). The ramp rate = 128/fs s/0.5dB step.  
If SOFTMUTE is set or  
MUTEB=0 then GAINL and  
GAINR are overridden to 00  
GAINL[0:7]  
Signal  
Processing  
GAINR[0:7]  
SOFTMUTE  
MUTEB  
gain ramps between  
previous and new gain  
setting  
Automute:  
Detect 1024  
zero input  
samples  
IZD  
OPE  
FREQ_INVALID  
INIT  
ANMUTE  
ZERO  
Figure 7 Mute Modes  
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WM8716  
FILTER RESPONSES  
Figure 8 Digital Filter Response (Sharp Roll-off Mode)  
Figure 9 Digital Filter Response (Sharp Roll-off Mode)  
Figure 10 Digital Filter Response (Slow Roll-off Mode)  
Figure 11 Digital Filter Response (Slow Roll-off Mode)  
0
-20  
-40  
-60  
-80  
-100  
-120  
0
0.2  
0.4  
0.6  
0.8  
1
1.2  
1.4  
1.6  
1.8  
2
Frequency (Fs)  
Figure 12 Digital Filter Response 128fs Mode (192kHz  
Sample Rate) Normal Mode – Solid, Slow Mode – Dashed  
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WM8716  
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1
0.8  
0.6  
0.4  
0.2  
0
1
0.8  
0.6  
0.4  
0.2  
0
-0.2  
-0.2  
-0.4  
-0.4  
0
10  
20  
30  
40  
50  
60  
0
10  
20  
30  
40  
50  
60  
Time (input samples)  
Time (input samples)  
Figure 13 Impulse Response (Normal Roll-off,  
no De-emphasis)  
Figure 14 Impulse Response (Slow Roll-off,  
no De-emphasis)  
0.0  
-1.0  
-2.0  
-3.0  
-4.0  
-5.0  
-6.0  
-7.0  
-8.0  
-9.0  
-10.0  
0.0  
-1.0  
-2.0  
-3.0  
-4.0  
-5.0  
-6.0  
-7.0  
-8.0  
-9.0  
-10.0  
0
2000  
4000  
6000  
8000  
10000  
12000  
14000  
16000  
0
5000  
10000  
15000  
20000  
Frequency (Fs)  
Frequency (Fs)  
Figure 15 De-emphasis frequency response (fs=32kHz)  
Figure 15 De-emphasis frequency response (fs=44.1kHz)  
0.0  
-1.0  
-2.0  
-3.0  
-4.0  
-5.0  
-6.0  
-7.0  
-8.0  
-9.0  
-10.0  
0.4  
0.3  
0.2  
0.1  
0.0  
-0.1  
-0.2  
-0.3  
-0.4  
0
2000  
4000  
6000  
8000  
10000 12000 14000 16000 18000 20000  
0
2000  
4000  
6000  
8000  
10000  
12000  
14000  
16000  
Frequency (Fs)  
Frequency (Fs)  
Figure 16 De-emphasis frequency response (fs=48kHz)  
Figure 17 De-emphasis frequency response error  
(fs=32kHz)  
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WM8716  
0.4  
0.3  
0.4  
0.3  
0.2  
0.2  
0.1  
0.1  
0.0  
0.0  
-0.1  
-0.2  
-0.3  
-0.4  
-0.1  
-0.2  
-0.3  
-0.4  
0
2000  
4000  
6000  
8000  
10000 12000 14000 16000 18000 20000  
0
2000  
4000  
6000  
8000  
10000 12000 14000 16000 18000 20000  
Frequency (Fs)  
Frequency (Fs)  
Figure 18 De-emphasis frequency response error  
(fs=44.1kHz)  
Figure 19 De-emphasis frequency response error  
(fs=48kHz)  
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APPLICATIONS INFORMATION  
RECOMMENDED EXTERNAL COMPONENTS  
DVDD  
AVDD  
8
15  
9
DVDD  
AVDD  
AVDDR  
AVDDL  
+
C1  
C2  
7
20  
DGND  
+
C3  
C4  
C5  
C6  
DGND  
14  
10  
19  
AGND  
AGNDR  
AGNDL  
AGND  
28  
27  
26  
23  
22  
ML/I2S  
MC/DM1  
MD/DM0  
CSB/IWO  
RSTB  
Software I/F or  
Hardware Control  
C7  
13  
16  
VOUTR  
VOUTL  
AC-Coupled Output  
to External LPF  
C8  
12  
17  
24  
25  
MODE8X  
WM8716  
AVDD  
R1  
DIFFHW  
MODE  
21  
ZERO  
11  
18  
MUTEB  
VMIDR  
VMIDL  
+
C
C12  
+
11  
1
2
3
LRCIN  
DIN  
C9  
C10  
Audio Serial Data I/F  
BCKIN  
AGND  
4
CLKO  
XTI Buffered Output  
5
6
XTI  
System Clock Input or  
Oscillator Input/Output  
XTO  
NOTES:  
1. AGND and DGND should be connected as close to the WM8716 as possible.  
2. C2 to C5, C9 and C11 should be positioned as close to the WM8716 as possible.  
3. Capacitor type used can have a big effect on device performance. It is  
recommended that capacitors with very low ESR are used and that ceramics  
are either NPO or COG type material to achieve best performance from the  
WM8716.  
Figure 20 External Components Diagram  
RECOMMENDED EXTERNAL COMPONENTS VALUES  
COMPONENT  
REFERENCE  
SUGGESTED  
VALUE  
DESCRIPTION  
C1 and C6  
C2 to C5  
10µF  
0.1µF  
10µF  
0.1µF  
10µF  
10kΩ  
De-coupling for DVDD and AVDD.  
De-coupling for DVDD and AVDD.  
C7 and C8  
C9 and C11  
C10 and C12  
R1  
Output AC coupling caps to remove VMID DC level from outputs.  
Reference de-coupling capacitors for VMIDR and VMIDL.  
Resistor to AVDD for open drain output operation.  
Table 22 External Components Description  
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WM8716  
RIGHT DAC  
DVDD  
+
AVDD  
8
7
15  
9
DVDD  
DGND  
AVDD  
AVDDR  
AVDDL  
20  
+
1
2
3
14  
10  
19  
LRCIN  
DIN  
LRCIN  
DIN  
AGND  
AGNDR  
AGNDL  
AUDIO  
SERIAL  
DATA  
BCKIN  
BCKIN  
5
6
4
13  
16  
21  
SCKI  
XTI  
VOUTR  
VOUTL  
ZERO  
+
-
RIGHT  
OUTPUT  
DATA  
XTO  
CLKO  
LPF  
WM8716  
DVDD  
24  
25  
22  
MODE  
MUTEB  
RSTB  
11  
18  
VMIDR  
VMIDL  
+
+
28  
27  
26  
23  
ML/I2S  
MC/DM1  
MD/DM0  
CSB/IWO  
Hardware  
Control  
12  
17  
MODE8X  
DIFFHW  
AVDD  
LEFT DAC  
DVDD  
+
AVDD  
8
7
15  
9
DVDD  
DGND  
AVDD  
AVDDR  
AVDDL  
20  
+
1
2
3
14  
10  
19  
LRCIN  
DIN  
AGND  
AGNDR  
AGNDL  
BCKIN  
5
6
4
13  
16  
21  
XTI  
VOUTR  
VOUTL  
ZERO  
+
-
LEFT  
OUTPUT  
DATA  
XTO  
CLKO  
LPF  
WM8716  
DVDD  
24  
25  
22  
MODE  
MUTEB  
RSTB  
11  
18  
VMIDR  
VMIDL  
+
+
28  
27  
26  
23  
ML/I2S  
MC/DM1  
MD/DM0  
CSB/IWO  
12  
17  
MODE8X  
DIFFHW  
AVDD  
NOTE:  
1. MODE selects left/right data. High for right, Low for left.  
Figure 21 Example of 2 WM8716 Stereo DACs Configured in Hardware Differential Mode to Provide an Optimum  
Performance Stereo Output  
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PD Rev 4.0 May 2004  
23  
WM8716  
Production Data  
+VDD  
MODE8X  
XTI  
SCKI  
PMD-100  
XTI  
Serial Interface Data  
WCKO  
BCKO  
DOL  
LRCIN  
BCKIN  
DIN  
LRCIN  
BCKIN  
DIN  
LRCI  
BCKI  
DIN  
VOUTL  
VOUTR  
DOR  
MODE  
PROG  
WM8716  
+VDD  
(STAND ALONE  
MODE)  
ML/I2S  
CSB/IWO  
MD/DM0  
MUTEB  
NOTES:  
1. ML/I2S selects left or right justified inputs.  
2. MD/DM0 selects LRCLK polarity.  
3. CSBIWO selects 20 or 24-bit data.  
Figure 22 Example of WM8716 in MODE8X Operation  
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PD Rev 4.0 May 2004  
24  
Production Data  
WM8716  
PACKAGE DIMENSIONS  
DS: 28 PIN SSOP (10.2 x 5.3 x 1.75 mm)  
DM007.D  
b
e
28  
15  
E1  
E
GAUGE  
PLANE  
Θ
14  
1
D
0.25  
L
c
A1  
L1  
A A2  
-C-  
0.10 C  
SEATING PLANE  
Dimensions  
(mm)  
NOM  
-----  
Symbols  
MIN  
-----  
0.05  
1.65  
0.22  
0.09  
9.90  
MAX  
A
A1  
A2  
b
c
D
e
E
E1  
L
2.0  
0.25  
1.85  
0.38  
0.25  
10.50  
-----  
1.75  
0.30  
-----  
10.20  
0.65 BSC  
7.80  
7.40  
5.00  
0.55  
8.20  
5.60  
0.95  
5.30  
0.75  
L1  
θ
0.125 REF  
0o  
4o  
8o  
JEDEC.95, MO-150  
REF:  
NOTES:  
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.  
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.  
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM.  
D. MEETS JEDEC.95 MO-150, VARIATION = AH. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.  
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PD Rev 4.0 May 2004  
25  
WM8716  
Production Data  
IMPORTANT NOTICE  
Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or  
service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing  
orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale  
supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation  
of liability.  
WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM’s  
standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support  
this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by  
government requirements.  
In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used  
by the customer to minimise inherent or procedural hazards. Wolfson products are not authorised for use as critical  
components in life support devices or systems without the express written approval of an officer of the company. Life  
support devices or systems are devices or systems that are intended for surgical implant into the body, or support or  
sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be  
reasonably expected to result in a significant injury to the user. A critical component is any component of a life support  
device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or  
system, or to affect its safety or effectiveness.  
WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that  
any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual  
property right of WM covering or relating to any combination, machine, or process in which such products or services might  
be or are used. WM’s publication of information regarding any third party’s products or services does not constitute WM’s  
approval, license, warranty or endorsement thereof.  
Reproduction of information from the WM web site or datasheets is permissible only if reproduction is without alteration and  
is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this  
information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive  
business practice, and WM is not responsible nor liable for any such use.  
Resale of WM’s products or services with statements different from or beyond the parameters stated by WM for that  
product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and  
deceptive business practice, and WM is not responsible nor liable for any such use.  
ADDRESS:  
Wolfson Microelectronics plc  
Westfield House  
26 Westfield Road  
Edinburgh  
EH11 2QW  
Tel :: +44 (0)131 272 7000  
Fax :: +44 (0)131 272 7001  
Email :: sales@wolfsonmicro.com  
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PD Rev 4.0 May 2004  
26  
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