Philips Semiconductors
Objective specification
XA 16-bit microcontroller
32K/1K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7V–5.5V),
I C, 2 UARTs, 16MB address range
XA-S3
2
I2CON
Address:42Ch
MSB
CR2
LSB
CR0
Bit Addressable
Reset Value: 00h
ENA
STA
STO
SI
AA
CR1
BIT
SYMBOL
CR2
ENA
FUNCTION
2
I2CON.7
I2CON.6
I2CON.5
I C Rate Control, with CR1 and CR0. See text and table.
2
2
Enable I C port. When ENA = 1, the I C port is enabled.
2
STA
Start flag. Setting STA to 1 causes the I C interface to attempt to gain mastership of the bus by
generating a Start condition.
Stop flag. Setting STO to 1 causes the I C interface to attempt to generate a Stop condition.
Serial Interrupt. SI is set by the I C hardware when a new I C state is entered, indicating that
software needs to respond. SI causes an I C interrupt if enabled and of sufficient priority.
2
I2CON.4
I2CON.3
STO
SI
2
2
2
2
I2CON.2
AA
Assert Acknowledge. Setting AA to 1 causes the I C hardware to automatically generate
acknowledge pulses for various conditions (see text).
2
I2CON.1
I2CON.0
CR1
CR0
I C Rate Control, with CR2 and CR0. See text and table.
I C Rate Control, with CR2 and CR1. See text and table.
2
SU00941
2
Figure 5. I C Control Register (I2CON)
2
2
If STA is set while the I C interface is already in a master mode and
one or more bytes are transmitted or received, the hardware
transmits a repeated START condition. STA may be set at any time.
I C Interface
2
The I C interface on the XA-S3 is identical to the standard byte-style
2
I C interface found on devices such as the 8xC552 except for the
2
2
2
STA may also be set when the I C interface is an addressed slave.
rate selection. The I C interface conforms to the 100 kHz I C
specification, but may be used at rates up to 400 kHz
(non-conforming).
STA = 0: When the STA bit is reset, no START condition or
repeated START condition will be generated.
2
Important: Before the I C interface may be used, the port pins
P5.6 and 5.7, which correspond to the I C functions SCL and SDA
respectively, must be set to the open drain mode.
STO, the STOP flag
STO = 1: When the STO bit is set while the I C interface is in a
master mode, a STOP condition is transmitted to the I C bus. When
2
2
2
2
The processor interfaces to the I C logic via the following four
special function registers: I2CON (I C control register), I2STA (I C
the STOP condition is detected on the bus, the hardware clears the
STO flag. In a slave mode, the STO flag may be set to recover from
an error condition. In this case, no STOP condition is transmitted to
2
2
2
2
status register), I2DAT (I C data register), and I2ADR (I C slave
2
2
2
address register). The I C control logic interfaces to the external I C
bus via two port 5 pins: P5.6/SCL (serial clock line) and P5.7/SDA
(serial data line).
the I C bus. However, the hardware behaves as if a STOP condition
has been received and switches to the defined “not addressed”
slave receiver mode. The STO flag is automatically cleared by
hardware.
The Control Register, I2CON
This register is shown in Figure 5. Two bits are affected by the I C
2
If the STA and STO bits are both set, then a STOP condition is
2
transmitted to the I C bus if the interface is in a master mode (in a
hardware: the SI bit is set when a serial interrupt is requested, and
the STO bit is cleared when a STOP condition is present on the I C
bus. The STO bit is also cleared when ENA = “0”.
2
slave mode, the hardware generates an internal STOP condition
which is not transmitted). The I C interface then transmits a START
2
condition.
2
ENA, the I C Enable Bit
STO = 0: When the STO bit is reset, no STOP condition will be
generated.
ENA = 0: When ENA is “0”, the SDA and SCL outputs are not
driven. SDA and SCL input signals are ignored, SIO1 is in the “not
addressed” slave state, and the STO bit in I2CON is forced to “0”.
No other bits are affected. P5.6 and P5.7 may be used as open
drain I/O ports.
SI, the Serial Interrupt flag
SI = 1: When the SI flag is set, and the EA (interrupt system
2
2
enable) and EI2 (I C interrupt enable) bits are also set, an I C
interrupt is requested. SI is set by hardware when one of 25 of the
ENA = 1: When ENA is “1”, SIO1 is enabled. The P5.6 and P5.7
port latches must be set to logic 1.
2
26 possible I C interface states is entered. The only state that does
not cause SI to be set is state F8H, which indicates that no relevant
state information is available.
2
ENA should not be used to temporarily release the I C-bus since,
2
when ENA is reset, the I C-bus status is lost. The AA flag should be
While SI is set, the low period of the serial clock on the SCL line is
stretched, and the serial transfer is suspended. A high level on the
SCL line is unaffected by the serial interrupt flag. SI must be reset
by software.
used instead (see description of the AA flag in the following text).
In the following text, it is assumed the ENA = “1”.
STA, the START flag
STA = 1: When the STA bit is set to enter a master mode, the I C
hardware checks the status of the I C bus and generates a START
condition if the bus is free. If the bus is not free, the I C interface
2
SI = 0: When the SI flag is reset, no serial interrupt is requested,
and there is no stretching of the serial clock on the SCL line.
2
2
waits for a STOP condition (which will free the bus) and generates a
START condition after a delay of a half clock period of the internal
serial clock generator.
17
1998 Oct 06
