5P30001
LOW SKEW 1 TO 4 CLOCK BUFFER
FANOUT BUFFER
Pin Assignment
OE
Q3
1
8
VDD
Q0
Q1
Q2
4
5
GND
ICLK
8-pin DFN
Pin Descriptions
Pin
Pin
Pin
Pin Description
Number Name Type
1
2
3
4
5
6
7
8
VDD
Q0
Power Connect to +1.2 V or +2.5 V
Output Clock Output 0.
Q1
Output Clock Output 1.
GND
ICLK
Q2
Power Connect to ground.
Input
Clock Input. 3.3 V tolerant input.
Output Clock Output 2.
Output Clock Output 3.
Q3
OE
Input
Output Enable. Tri-states outputs when low. Connect to VDD for normal operation.
External Components
A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01 µF
should be connected between VDD on pin 1 and GND on pin 4, as close to the device as possible. A 33 Ω series
terminating resistor may be used on each clock output if the trace is longer than 1 inch.
To achieve the low output skew that the 5P30001 is capable of, careful attention must be paid to board layout.
Essentially, all 4 outputs must have identical terminations, identical loads and identical trace geometries. If they do
not, the output skew will be degraded. For example, using a 30Ωseries termination on one output (with 33Ωon the
others) will cause at least 15ps of skew.
IDT™ / ICS™ LOW SKEW 1 TO 4 CLOCK BUFFER
2
5P30001
REV A 083006