5P35021_1,PDF,5P35021_1 PDF资料,Datasheet,下载5P35021

VersaClock^®Programmable Clock Generator

5P35021

DATASHEET

Description

Features

The 5P35021 is the latest VersaClock programmable clock

generator and is designed for low-power, consumer, and

high-performance PCI Express applications. The 5P35021

device is a 3 PLLs architecture design; each PLL is

individually programmable and allows up to 3 unique

frequency outputs.

• Configurable OE pin function as OE, PD#, PPS or DFC

control function

• Configurable PLL bandwidth/minimizes jitter peaking

• PPS: Proactive Power Saving features save power during

the end device power down mode

• PPB: Performance- Power Balancing feature allow user to

minimum power consumption base on required

performance

The 5P35021 has built-in unique features such as Proactive

Power Saving (PPS), Performance-Power Balancing (PPB),

Overshot Reduction Technology (ORT) and extreme low

power DCO. An internal OTP memory allows the user to store

the configuration in the device. After power up, the user can

• DFC: Dynamic Frequency Control feature allows user to

program up to 4 difference frequencies and switch

dynamically

2

• Spread spectrum clock support to lower system EMI

• Store user configuration into OTP memory

change the device register settings through the I C interface

2

when I C mode is selected. It also has programmable VCO

2

and PLL source selection to allow the user to do

power-performance optimization based on the application

requirements.

• I C interface

Key Specifications

• PCIe clocks phase jitter: PCIe Gen3

• Differential clocks < 3 ps rms jitter integer range 12kHz–

20MHz

The device provides one single-ended output and two pairs of

differential outputs that support LVCMOS, LVPECL, LVDS and

LPHCSL. The low power 32.768kHz clock is supported with

only less than 2µA current consumption for system RTC

reference clock.

• < 2µA DCO to generate 32.768kHz clock

Output Features

• 2 DIFF outputs with configurable LPHSCL, LVDS, LVPECL,

LVCMOS output pairs. 1MHz–500MHz (160MHz/ with

LVCMOS mode)

Typical Applications

• PCIe Gen1/2/3 clock generator

• Consumer application crystal replacements

• SmartDevice, Handheld, Computing and Consumer

applications

• 1 LVCMOS output: 1MHz–160MHz

• Maximum 5 LVCMOS outputs as 1 × SE + 2 × DIFF_T/C as

LVCMOS

• Low Power 32.768kHz clock supported on SE1

Pin Assignment

19

18

17

20

16

1

15

14

13

12

11

DIFF1

DIFF1B

VDDDIFF1

OE1

VDDA

2

SDA_DFCO

3

5P35021

SEL_DFC/SCL_DFC1

4

CLKIN/X2

5

SE1

CLKINB/X1

6

7

8

9

10

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5P35021 DATASHEET

Functional Block Diagram

DIV1/REF

DIV3

VDDDIFF2

OSC

DIFF2

DIFF2B

MUX

DIV1

DIV2

MUX

CLKINB/X1

VDDDIFF1

PLL1

PLL2

DIV1/REF

DIV3

CLKIN/X2

DIFF1

DIFF1B

Power

VBAT

DIV3

DIV4

MUX

Monitor

VDD33

POR

VDDA

MUX

DIV5

PLL3

DIV4/REF

DIV5

OE1

SE1

Calibration

VSS

MUX

32K

VDDSE1

32.768K

DCO

SCL_DFC1

I2C Engine

SDA_DFC0

Overshoot Reduction

(ORT)

Dynamic Frequency Control Logic (DFC)

OTP memory (1 configuration )

Proactive Power Saving Logic (PPS)

Timer

Power Group

Power supply table

SE

DIFF

DIV

MUX

PLL

PLL2

PLL3

PLL1

DCO

REF

Xtal

SE1

VDDSE1

VDDDIFF1

VDDDIFF2

VDD33

DIFF1

DIFF2

DIV3/4 MUXPLL2

DIV1

DIV5

MUXPLL1

DCO

REF

Xtal

VBAT

DIV2

VDDA

* VDDSEx for non-32kHz outputs should be OFF when VDDA/VDD3 turn OFF, VBAT mode only support

32.768kHz outputs from SE1-3.

* VBAT power ramp up should be same or earlier than other VDD power rail.

Output Source Table

Outputs:

Source:

SE1

DIFF1

DIFF2

Xtal REF

32.768kHz

PLL1

Xtal REF

32.768kHz

Xtal REF

PLL1

PLL2

PLL3

PLL1

PLL2

PLL3

PLL2

PLL3

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5P35021 DATASHEET

Output Source Selection Register Setting Table

SE1

B36<4>

B36<3>

B31<1>

B29<3>

From 32K

0

1

0

1

0

1

0

1

From PLL3 + Divider 5

From PLL2 + Divider 4

From REF + Divider 4

DIFF1

B34<7>

B0<3>

From PLL1 + Divider 1

From PLL2 + Divider 3

From REF + Divider 1

0

1

0

1

DIFF2

B35<7>

B0<3>

From PLL1 + Divider 1

From PLL2 + Divider 3

From REF + Divider 1

0

1

0

1

Glossary of Features

Term

Function Description

Apply to

Dynamic Frequency Control, from selected PLL to support four VCO frequencies,

means two different output frequencies by assign H/W pin state changes.

PLL2

DFC

Overshoot Reduction, when the DFC dynamic frequency change is functional, the

VCO change frequency smoothly to target frequency without overshoot or under

shoot.

PLL2

OE1

ORT

Output Enable function, each output can be controlled by assigned OE pin, the

dedicated OE pin can be OTP programmable as Global Power Down function (PD#)

or Output enable (OE) or proactive power saving function (PPS) or RESET pin

function.

OE

Spread spectrum clock.

PLL1/PLL2

LVCMOS

SS

LVCMOS outputs with slew rate control - slow and fast.

Slew Rate

Proactive Power Saving, utilize OE pin as monitor pin for end device X2 clock status,

details see PPS function .description

SE1

PPS

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5P35021 DATASHEET

Pin Descriptions

Number

Name

Type

Power

I/O

Description

1

2

VDDA

SDA_DFC0

VDD 3.3V.

I2C DATA pin, can be setup become DFC0 by OTP programming.

I2C CLK pin,

SEL_DFC is a latch input pin during the power up

High on power on: I2C mode as SCLK function,

Low on power on: SCL and SDA as DFC function pins.

3

SEL_DFC/SCL_DFC1

Input

4

5

CLKIN/X2

CLKINB/X1

I/O

Input

Crystal oscillator interface output or differential clock input pin (CLKIN).

Crystal oscillator interface input or differential clock input pin (CLKINB).

6

VBAT

Power

Power supply pin for 32.768kHz DCO, usually connect to coin cell battery, 2.5-3.3V.

7

8

9

10

11

VSS

VDD33

VSSSE1

VDDSE1

SE1

Power

Output

Connect to ground.

VDD 3.3V.

Connect to ground.

Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for SE1.

Output Clock SE1.

OE1’s function selected from OTP preprogram register bits.

OE1 pull-up to 6.5V when burn OTP registers.

Refer to OE function table for details.

12

OE1

Input

13

14

VDDDIFF1

DIFF1B

Power

Output

Output power supply. Connect to 2.5 to 3.3V. Sets output voltage levels for DIFF1.

Differential clock output 1_Complement, can be OTP pre-program to

LVCMOS/LPHCSL/LVDS/LVPECL output type.

Differential clock output 1_True, can be OTP pre-program to

LVCMOS/LPHCSL/LVDS/LVPECL output type.

15

DIFF1

Output

16

17

VSSDIFF1

VDDDIFF2

Power

Connect to ground.

Output power supply. Connect to 2.5 to 3.3V. Sets output voltage levels for DIFF2.

Differential clock output 2_Complement, can be OTP pre-program to

LVCMOS/LPHCSL/LVDS/LVPECL output type.

18

19

DIFF2B

DIFF2

Output

Differential clock output 2_True, can be OTP pre-program to

LVCMOS/LPHCSL/LVDS/LVPECL output type.

20

21

VSSDIFF2

EPAD

Power

Connect to ground.

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Device Feature and Function

DFC–Dynamic Frequency Control

• OTP program (Only) setup 4 different feedback fractional divider (4 VCO frequencies) that apply to PLL2

• ORT (overshoot reduction) function will be applied automatically during the VCO frequency change

• Smooth frequency incremental or decremental from current VCO to targeted VCO base on DFC hardware pins selection

DFC Block Diagram

M divider

PLL2

OUT DIV

Selector

N divider

00

01

10

11

N divider

DFC1:0

OTP/I2C

DFC Function Priority Table

DFC_EN

bit(W32[4])

0

OE1_fun_sel

(W30[6:5])

x

*OE3_fun_sel

(W30[3:2])

SCL_DFC1

DFC[1:0]

0

Notes

x

DFC disable

One pin DFC -

OE1

1

11 (DFC)

00-10 (DFC)

[0,OE1]

Two pin DFC -

OE3,OE1

1

11 (DFC)

00-10

11 (DFC)

11

x

0

[OE3,OE1]

Not permit

[SCL_DFC1,

SDA_DFC0]

Not supported

I2C pin as DFC

control pins mode

I2C control DFC

mode

00-10

1

00-10

1

W30[1:0]

* 5P35021 has only OE1 pin for DFC function hardware pin selection. For OE1/OE3 two pins DFC control, use 5P35023 24-

QFN package device.

DFC Function Programming

• Register B63b3:2 select DFC00–DFC11 configuration.

• Byte16–19 are the register for PLL2 VCO setting, base on B63b3:2 configuration selection, the data write to B16–19 will be

store in selected configuration OTP memory.

• Refer to DFC function priority table, select proper control pin(s) to activate DFC function.

2

• Note the DFC function can also be controlled by I C access.

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5P35021 DATASHEET

PPS–Proactive Power Saving Function

PPS Proactive Power Saving is an IDT patented unique design for the clock generator that proactively detects end device power

down state and then switches output clocks between the normal operation clock frequency and the low power mode 32kHz clock

that only consume < 2µA current. The system could save power when the device goes into power down or sleep mode. The PPS

function diagram is shown below.

PPS Function Block Diagram

PPS

Control

Logic

Power

Down

I2C

&

Logic

Control

Low

Power

DCO

Xout

Xin

Xtal

Oscillator

Logic

MHz

/kHz

Xtal

Oscillator

PLL

Switching

PPS Assertion/Deassertion Timing Chart

3rd cycle

2nd cycle

1st cycle

PPS assertion

MHz clock

2nd cycle

32K clocks

1st cycle

PPS deassertion

32K clocks

MHz clock

PPS Function Programming

• Refer to OE_pin_function_table to have proper PPS function selected for OE pin(s), please note that register default is set to

Output enable (OE).

• Have proper setup to Byte 30 and 32 for OE1~OE3 function selection, for PPS function, select 10 to control register bits.

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Timer Function Description

1. The timer function can be used together with the DFC (Dynamic Frequency Control) function or with another PLL frequency

programming.

2. The timer provides 4 different delay times by two bits selection: 0.5 seconds, 1 seconds, 2 seconds, 4 seconds.

3. The timeout flag will be set when timer times out, and the flag can be cleared by writing 0 to timer enable bit.

4. When timer times out, RESET pin (available in 5P35023) can generate a 250ms pulse signal if RESET control bit is enabled.

5. When timer times out, DFC stage will switch back to DFC00 setting if DFC function is enabled and DFC function will be

disabled after RESET.

Select delay time 0.5 ~ 4.0 seconds and enable Timer

Program New VCO frequency or enable DFC

System functional check

Disable Timer

Timer continue if system is not able to stop timer

Timer out Flag set and generate RESET pulse

OE Pin Function

OE pins in the 5P35021 have multiple functions. The OE pins can be configured as output enable control (OE) or chip power

down control (PD#) or Proactive Power Saving function (PPS). Furthermore, the OE pins can be configured as single or two pin

dynamic Frequency control (DFC), or the RESET out function that is associated with the Timer function.

OE Pin Function Table

Function

OE2 (Not available in

5P35021)

OE3 (Not available in

5P35021)

OE1

SE1 (Default)

SE2 (Default)

SE3 (Default)

SE Output Enable/Disable

DIFF Output Enable/Disable

Global Power Down (PD#)

Proactive Power Saving Input

DOC Control (Only PLL2)

RESET OUT

-

PD#

DIFF1/DIFF2

-

SE3_PPS

DFC1

-

SE1_PPS

DFC0

-

SE2_PPS

-

RESET OUT

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5P35021 DATASHEET

OE Pin Function Summary (* Note: OE2, OE3 and SE2, SE3 pins are only available in 5P35023)

OE1: SE1

* OE2: SE2

* OE2: SE3

OE1 only control SE1 enable/disable, other outputs are not affected by this pin status

OE2 only control SE2 enable/disable, other outputs are not affected by this pin status

OE3 only control SE3 enable/disable, other outputs are not affected by this pin status

OE2 control Differential outputs 1 and 2 only, other SE outputs are not affected by this pin status

OE1 control chip global power down (PD#) except 32.768KHz on OE1 (when 32K is enabled),

Config OE1 as SE1_PPS (Proactive Power Saving) function pin

Config OE2 as SE2_PPS (Proactive Power Saving) function pin

Config OE3 as SE3_PPS (Proactive Power Saving) function pin

Config OE1 as DFC0 control pin0

* OE2: DIFF1/DIFF2

OE1: PD#

OE1: SE1_PPS

* OE1: SE2_PPS

* OE1: SE3_PPS

OE1:DFC0

* OE3/DFC1

Config OE3 as DFC1 control pin1

PD# Priority Table

SE1, DIFF1/DIFF2

PD#

I2C_OE_EN_bit

Output

Notes

SE1_PPS

0

1

x

0

1

x

0

1

stop

32kHz free run

stop

running

Reference Input and Selection

The 5P35021 accepts crystal input or LVCMOS/Differential clocks input by external AC coupling. See below reference circuit for

details.

Crystal Input (X1/X2)

The crystal oscillators should be fundamental mode quartz crystals; overtone crystals are not suitable. Crystal frequency should

be specified for parallel resonance with 40MHz maximum.

A crystal manufacturer will calibrate its crystals to the nominal frequency with a certain load capacitance value. When the

oscillator load capacitance matches the crystal load capacitance, the oscillation frequency will be accurate as 0 PPM. When the

oscillator load capacitance is lower than the crystal load capacitance, the oscillation frequency will be higher than nominal. In

order to get an accurate oscillation frequency, the matching the oscillator load capacitance with the crystal load capacitance is

required.

To set the oscillator load capacitance, 5P35021 has built-in two programmable tuning capacitors inside the chip, one at XIN and

one at XOUT. They can be adjusted independently. The value of each capacitor is composed of a fixed capacitance amount plus

a variable capacitance amount set with the XTAL[7:0] register. Adjustment of the crystal tuning capacitors allows for maximum

flexibility to accommodate crystals from various manufacturers. The range of tuning capacitor values available are in accordance

with the following table.

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5P35021 DATASHEET

Programmable Tuning Caps Table

Parameter

Bits

Range

Min (pF)

Max (pF)

Xtal [7:0]

4*2

+1/+2/+4/+8 pF

0

15pF

XTAL[4:0] = (XTAL CL - 7pF) × 2 (Eq.1)

Equation 1 and the table of XTAL[7:0] tuning capacitor characteristics show that the parallel tuning capacitance can be set

between 4.5pF to 12.5pF with a resolution of 0.25pF.

For a crystal C = 8pF, where C is the parallel capacity specified by the crystal vendor that sets the crystal frequency to the

L

nominal value. Under the assumptions that the stray capacity between the crystal leads on the circuit board is zero and that no

external tuning caps are placed on the crystal leads, then the internal parallel tuning capacity is equal to the load capacity

presented to the crystal by the device.

The internal load capacitors are true parallel-plate capacitors for ultra-linear performance. Parallel-plate capacitors were chosen

to reduce the frequency shift that occurs when non-linear load capacitance interacts with load, bias, supply, and temperature

changes. External non-linear crystal load capacitors should not be used for applications that are sensitive to absolute frequency

requirements.

Spread Spectrum

The 5P35021 supports spread spectrum clocks from PLL1 and PLL2; the PLL1 built-in with analog spread spectrum and PLL2

has digital spread spectrum.

Analog Spread Spectrum

Please refer to programming guide.

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5P35021 DATASHEET

Digital Spread Spectrum

Fvco

N 

2*Fout

Fpfd

period 

2*Fss

N *SSamout

step 

period

Down spread or Spread off

N = Fvco/Fpfd

Center Spread

N = Nssoff + N*SSamount/2

N: include integer and fraction

Fvco: vco’s frequency

Fpfd: PLL’s pfd frequency

Fss: spread modulation rate

SSamout: spread percentage

The black line is for the down spread, N will decrease to make the center frequency is lower than spread off.

The blue line is for the center spread, there is a offset put on divider ratio to make the center frequency keep same as spread off.

Example: 0.5% down spread at 32kHz modulation rate.

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5P35021 DATASHEET

VBAT

The 5P35021 supports low-power operation 32.768kHz RTC clock with only coin cell battery supply. The coin cell battery power

capacitance is usually 170mAhr or higher, with less than 2µA* low-power DCO operation mode will support application up to few

years clock source for date/time keeping circuit (RTC).

When there is main power exist like V

and V

, the 5P35021 will switch DCO power source to main power to save battery

DDA

DD33

power. V

should be powered earlier or at same time with other V power up.

BAT

DD

VBAT Switching Threshold

VDD33

>2.5V

<2.3V

VBAT DCO power source

--

VDD33

VBAT

*VBAT needs to be 3.0V~3.3V

VBAT

Switch to VDD33

(VDD33 raise up to 2.5V )

Switch to VBAT

(VDD33 falling down to 2.3V)

VDD33

ORT–VCO Overshoot Reduction Technology

The 5P35021 supports innovate the VCO overshoot reduction technology (ORT) to prevent an output clock frequency spike

when the device is changing frequency on the fly or doing DFC (Dynamic Frequency Control) function. The VCO frequency

changes are under control instead of free-run to targeted frequency.

PLL Features and Descriptions

Output divider 1 table

Output Divider bits<3:2>

Output Divider bits<1:0>

OO

O1

1O

11

OO

O1

1O

11

1

4

5

6

2

8

4

8

16

20

24

32

40

48

10

12

Output 2,4,5 divider table

Output Divider bits<3:2>

Output Divider bits<1:0>

OO

O1

1O

11

OO

O1

1O

11

1

3

2

6

4

5

12

20

40

15

25

50

5

10

20

10

Output 3 divider table

Output Divider bits<3:2>

Output Divider bits<1:0>

OO

O1

1O

11

OO

O1

1O

11

1

3

2

6

4

8

12

20

40

24

40

80

5

10

20

10

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5P35021 DATASHEET

Output Clock Test Conditions

LVCMOS output test conditions

33 ohm

2 inches

2pF

LVCMOS

LPHCSL output test conditions

33 ohm

5 inches

33 ohm

2pF

LPHCSL

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5P35021 DATASHEET

Absolute Maximum Ratings

Stresses above the ratings listed below can cause permanent damage to the 5P35021. These ratings, which are standard values

for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions

above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating

conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended

operating temperature range.

Item

Rating

Supply Voltage, VDDA, VDD33, VDDSE,VDDDIFF 3.465V

Supply Voltage, VBAT

Inputs

3.465V

XIN/CLKIN

0V to 3.3V voltage swing for both LVCMOS or DIFF CLK

Other inputs

-0.5V to VDD33/VDDSEx

-0.5V to VDDSEx/VDDDIFF+ 0.5V

10mA

Outputs, VDDSEx (LVCMOS)

Outputs, IO (SDA)

Package Thermal Impedance, ΘJA

Package Thermal Impedance, ΘJC

Storage Temperature, TSTG

ESD Human Body Model,

ESD Charge Device Model,

Junction Temperature

42°C/W (0 mps)

41.8°C/W (0 mps)

-65°C to 150°C

2500V

1000V

125°C

Recommended Operating Conditions

Symbol

Parameter

Min

1.71

Typ

1.8

Max

1.89

Unit

V

Power supply voltage for supporting 1.8V outputs

Power supply voltage for supporting 2.5V outputs

Power supply voltage for supporting 3.3V outputs

VDDSEx

2.375

3.135

2.5

2.625

3.465

V

3.3

V

VDD33

VDDA

VBAT

3.3*

V

Power supply voltage for core logic functions.

Analog power supply voltage. Use filtered analog power supply if

available.

2.375

3.465

V

2.8*

-40

3*

5

3.465

85

V

Battery power supply voltage.

Operating temperature, ambient

°C

pF

CLOAD_OUT

FIN

Maximum load capacitance (3.3V LVCMOS only)

External reference crystal

8

12

1

40

38

External reference crystal with DCO used

External single-ended reference clock CLKINB

MHz

ms

125

8

External differential reference clock CLKIN, CLKINB

Power up time for all VDDs to reach minimum specified voltage

(power ramps must be monotonic),

tPU

0.05

3

* Power-up sequence conditions.

* VDDSEx for non-32kHz outputs should be OFF when VDDA/VDD3 turn OFF, VBAT mode only support 32.768kHz outputs from SE1-3.

* VBAT power ramp up should be same or earlier than other VDD power rail.

* When use single-ended clock to CLKINB pin within differential clocking mode, CLKIN pin needs to be grounded and minimum input

frequency should be higher than 8MHz.

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5P35021 DATASHEET

Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance

(TA = +25 °C)

Symbol

CIN

Parameter

Min

Typ

Max

Unit

Input Capacitance (CLKIN, CLKINB, OE, SDA, SCL,

DFC1:0)

3

200

22

7

pF

Pull-down Resistor

OE

kΩ

LVCMOS Output Driver Impedance (VDDSE = 1.8V)

LVCMOS Output Driver Impedance (VDDSE = 2.5V)

LVCMOS Output Driver Impedance (VDDSE = 3.3V)

Programmable input capacitance at X1 or X2

ROUT

X1, X2

Ω

0

15

pF

Crystal Characteristics

Parameter

Test Conditions

Min

Typ

Max

Units

Mode of Oscillation

Fundamental

Frequency

8

12

40

38

100

7

MHz

Ω

Frequency when 32.768K DCO is used

Equivalent Series Resistance (ESR)

Shunt Capacitance

10

2

pF

Load Capacitance (CL)

Maximum Crystal Drive Level (CL=8pF)

6

8

10

100

pF

µW

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5P35021 DATASHEET

DC Electrical Characteristics

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

VDD=VDDSE=VDD33=3.3V, Xtal=25MHz, PLL2/3 OFF,

No Output - PLLs disabled

Iddcore

Core Supply Current

5

mA

VDD=VDDSE=VDD33=3.3V, Xtal=25MHz, PLL2/3 OFF,

No Output - PLL1= 600MHz

Idd_PLL1³

Idd_PLL2³

Idd_PLL3³

PLL1 Supply Current

PLL2 Supply Current

PLL3 Supply Current

13

11

4

VDD=VDDSE=VDD33=2.5V, Xtal=25MHz, PLL2/3 OFF,

No Output - PLL1= 600MHz

VDD=VDDSE=VDD33=3.3V, Xtal=25MHz, PLL1/3 OFF,

No Output - PLL2=1GHz

VDD=VDDSE=VDD33=2.5V, Xtal=25MHz, PLL1/3 OFF,

No Output - PLL2=1GHz

VDD=VDDSE=VDD33=3.3V, Xtal=25MHz, PLL1/2 OFF,

No Output - PLL3=480MHz

LVPECL, 500MHz, 3.3V VDDDIFF (DIFF1,2)

LVPECL, 156.25MHz, 2.5V VDDDIFF (DIFF1,2)

LVDS, 500MHz, 3.3V VDDDIFF (DIFF1,2)

LVDS, 250MHz, 2.5V VDDDIFF (DIFF1,2)

39

33

13

8

mA

LPHCSL, 125MHz, 3.3V VDDDIFF, 2 pF load (DIFF1,2)

7

8

mA

LPHCSL, 100MHz, 2.5V VDDDIFF, 2 pF load (DIFF1,2)

Iddox

Output Buffer Supply Current

1,2

1

mA

LVCMOS, 8MHz, 3.3V, VDDSE

(SE1)

LVCMOS, 8MHz, 2.5V, VDDSE ^1,2(SE1)

LVCMOS, 8MHz, 1.8V, VDDSE ^1,2(SE1)

LVCMOS, 160MHz, 3.3V VDDSEx1 (SE1)

LVCMOS, 160MHz, 2.5V VDDSEx1,2 (SE1)

LVCMOS, 160MHz, 1.8V VDDSEx1,2 (SE1)

1

9.5

5.0

6.0

PD asserted with VDDA, VDD33 and VDDSE ON, I2C

programming, 32K running

Iddpd

Power Down Current

3.5

mA

Iddsuspend -

VDD33

Iddsuspend-VBAT

Only VBAT=3.3V and VDDSEn is powered

1.1

3.4

2.5

1.8

µA

Iddsuspend -

SEn 3.3V

Iddsuspend - VDDSEn 3.3V

Iddsuspend - VDDSEn 2.5V

Iddsuspend - VDDSEn 1.8V

Only VBAT=3.3V and VDDSEn is powered with 3.3V

Only VBAT =3.3Vand VDDSEn is powered with 2.5V

Only VBAT=3.3V and VDDSEn is powered with 1.8V

Iddsuspend -

SEn 2.5V

Iddsuspend -

SEn 1.8V

1. Single CMOS driver active.

2. SE1-3 current measured with 2 inches transmission line and 2 pF load, DIFF clock current measured with 5 inches transmission line with 2 pF loads.

3. Iddcore = IddA+ IddD, no loads.

NOVEMBER 30, 2017

15

VERSACLOCK^®PROGRAMMABLE CLOCK GENERATOR

5P35021 DATASHEET

Power Consumption of 32.768kHz Output Only Operation

Unless stated otherwise, supply voltage VDDSE = 1.8V–3.3V ±5%, T = -40°C to +85°C

A

Symbol

Parameter

Test Conditions

Min

Typ

1.1

0.4

1.0

2.3

0.6

1.5

3.1

0.8

1.9

4.2

Max

Unit

uA

I_VBAT

Vbat=3.3V power input current

VDDSEx=1.8V current

VDDSEx=2.5V current

VDDSEx=3.3V current

0.5 inch, no load, one output

2.0 inch, no load, one output

5.0 inch, no load, one output

0.5 inch, no load, one output

2.0 inch, no load, one output

5.0 inch, no load, one output

0.5 inch, no load, one output

2.0 inch, no load, one output

5.0 inch, no load, one output

I_VDDSEx

Electrical Characteristics – Input Parameters ^1,2

Unless stated otherwise, supply voltage VDDD33 = 3.3V ±5%, T = -40°C to +85°C

A

Symbol

VIH

Parameter

Test Conditions

Single-ended input

Differential Input

Min

Typ

Max

Unit

Input High Voltage - CLKIN

Input Low Voltage - CLKIN

Input Amplitude - CLKIN

Input Slew Rate - CLKIN

Input Common Mode Voltage

Input Leakage Low Current for OE1

2.4

GND - 0.3

325

3.345

0.8

3300

8

V

VIL

VSWING

mV

V/ns

mV

µA

%

dv/dt

VCM

IIL

Differential Input

0.4

Differential Input

200mV

-150

2500

5

VIN = GND @ OE1 pin

IIL

Input Leakage Low Current for OE2/3 VIN = GND

Input Leakage High Current for OE1/2/3 VIN = 3.465

5

IIH

20

dTIN

Input Duty Cycle

Measurement from differential waveform

45

55

1. Guaranteed by design and characterization, not 100% tested in production.

2. Slew rate measured through ±75mV window centered around differential zero.

DC Electrical Characteristics for 3.3V LVCMOS

Unless stated otherwise, VDDSE = 3.3V ±5%, T = -40°C to +85°C

A

Symbol

VOH

VOL

IOZDD

VIH

Parameter

Test Conditions

Min

Typ

Max

VDDSE

0.4

Unit

V

IOH = -15mA

Output HIGH Voltage

Output LOW Voltage

Output Leakage Current

Input HIGH Voltage

Input LOW Voltage

Input HIGH Voltage

Input LOW Voltage

2.4

IOL = 15mA

V

Tri-state outputs, VDDSE = 3.465V

3

µA

V

Single-ended inputs - CLKSEL, OE, SDA, SCL

Single-ended input - XIN/CLKIN

2

VDDSE + 0.3

0.8

VIL

GND - 0.3

2.4

V

VIH

VDD33

0.8

V

Single-ended input - XIN/CLKIN

VIL

GND - 0.3

V

DC Electrical Characteristics for 2.5V LVCMOS

Unless stated otherwise, VDDSE = 2.5V ±5%, T = -40°C to +85°C

A

Symbol

VOH

VOL

Parameter

Test Conditions

Min

Typ

Max

Unit

V

IOH = -12mA

Output HIGH Voltage

Output LOW Voltage

Output Leakage Current

Input HIGH Voltage

Input LOW Voltage

0.7xVDDSE

VDDSE

IOL = 12mA

0.4

V

Tri-state outputs, VDDSE = 2.625V

IOZDD

VIH

3

VDDSE + 0.3

0.8

µA

V

Single-ended inputs - CLKSEL, OE, SDA, SCL

1.7

VIL

GND - 0.3

V

VERSACLOCK^®PROGRAMMABLE CLOCK GENERATOR

16

NOVEMBER 30, 2017

5P35021 DATASHEET

DC Electrical Characteristics for 1.8V LVCMOS

Unless stated otherwise, VDDSE = 1.8V ±5%, T = -40°C to +85°C

A

Symbol

VOH

VOL

Parameter

Test Conditions

Min

Typ

Max

VDDSE

Unit

IOH = -8mA

Output HIGH Voltage

Output LOW Voltage

Output Leakage Current

Input HIGH Voltage

Input LOW Voltage

0.7 xVDDSE

V

IOL = 8mA

0.25 x VDDSE

3

Tri-state outputs, VDDSE = 1.89V

Single-ended inputs - OE, SDA, SCL

IOZDD

VIH

µA

V

0.65 * VDDSE

GND - 0.3

VDDSE + 0.3

0.35 * VDDSE

VIL

V

Electrical Characteristics–DIF 0.7V LPHCSL Differential Outputs

Unless stated otherwise, VDDDIFF = 3.3 V ±5%or 2.5V ±5%, T = -40° to +85°C

A

Symbol

Parameter

Notes

Min

Typ

Max

Units

dV/dt

Slew Rate

1,2,3,8

1

2.5

4

V/ns

1,2,3,8, at <=

200MHz

∆dV/dt

Slew Rate Mismatch

20

%

VHIGH

VLOW

Voltage High

1,6,7,8

660

800

0

1150

150

mV

ps

Voltage Low

1,6

1

-150

VMAX

Maximum Voltage

Minimum Voltage

Voltage Swing

1150

VMIN

1

-300

300

250

VSWING

VCROSS

1,2,6

1,4,6

1,5

1,2

Crossing Voltage Value

360

550

140

VCROSS Crossing Voltage variation

Δ

Jitter-Cy/Cy Cycle to Cycle Jitter

Jitter-STJ Jitter - Period Jitter

10

70

ps

Duty Cycle Duty Cycle

Measured

Frequency

45

55

%

LVHCSL at Differential Output

1,2

500

MHz

* differential clock amplitude setting 00.

Note 1: Guaranteed by design and characterization. Not 100% tested in production.

Note 2: Measured from differential waveform.

Note 3: Slew rate is measured through the VSWING voltage range centered around differential 0V. This results in a +/-150mV window around

differential 0V.

Note 4: VCROSS is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising

edge (i.e. Clock rising and Clock# falling).

Note 5: the total variation of all VCROSS measurements in anyparticular system. Note that this is a subset of VCROSS min/max (VCROSS

absolute) allowed. The intent is to limit VCROSS induced modulation by setting VCROSS to be smaller than VCROSS absolute.

Δ

Note 6: Measured from single-ended waveform.

Note 7. Measured with scope averaging off, using statistics function. Variation is difference between min. and max.

Note 8. Scope average ON.

NOVEMBER 30, 2017

17

VERSACLOCK^®PROGRAMMABLE CLOCK GENERATOR

5P35021 DATASHEET

DC Electrical Characteristics for LVDS

Unless stated otherwise, VDDDIFF = 3.3 V ±5%or 2.5V ±5%, T = -40° to +85°C

A

Symbol

VOT (+)

VOT (-)

Parameter

Min

247

Typ

Max

454

Unit

mV

V

Notes

Differential Output Voltage for the TRUE binary state

Differential Output Voltage for the FALSE binary state

Change in VOT between Complimentary Output States

Output Common Mode Voltage (Offset Voltage)

-247

-454

50

VOT

Δ

VOS

1.125

1.25

9

1.375

VOS

Δ

Change in VOS between Complimentary Output States

Outputs Short Circuit Current, VOUT+ or VOUT- = 0V or

VDDDIFF

50

mV

IOS

24

mA

Differential Outputs Short Circuit Current, VOUT+ =

VOUT-

IOSD

6

12

mA

ps

%

Jitter-Cy/Cy Cycle to Cycle Jitter

Jitter-STJ Jitter - ST

1,2

20

100

Duty Cycle Duty Cycle

Measured

45

55

LVDS at Differential Output

1,2

500

MHz

Frequency

* differential clock amplitude setting 01.

DC Electrical Characteristics for LVPECL

Unless stated otherwise, VDDDIFF = 3.3 V ±5%or 2.5V ±5%, T = -40° to +85°C

A

Symbol

Parameter

Min

Typ

Max

Unit

Notes

Output Voltage HIGH, terminated through 50Ω tied to

VDDDIFF-2 V

VOH

VDDDIFF - 1.19

VDDDIFF - 0.69

V

Output Voltage LOW, terminated through 50Ω tied to

VDDDIFF-2 V

VOL

VDDDIFF - 1.94

0.55

VDDDIFF - 1.4

0.993

V

VSWING

Peak-to-Peak Output Voltage Swing

Jitter-Cy/Cy Cycle to Cycle Litter

Jitter-STJ Jitter - ST

1,2

20

ps

1,2

100

ps

%

Duty Cycle Duty Cycle

45

55

Measured

Frequency

LVPECL at Differential Output

1,2

500

MHz

* differential clock amplitude setting 01.

VERSACLOCK^®PROGRAMMABLE CLOCK GENERATOR

18

NOVEMBER 30, 2017

5P35021 DATASHEET

AC Electrical Characteristics

Unless stated otherwise, VDDSE = 3.3 V ±5%or 2.5V ±5% or 1.8V ±5%, T = -40° to +85°C (spread spectrum OFF)

A

Symbol Parameter

Test Conditions

Input frequency limit (XIN)

Min.

8

12

8

1

300

400

300

45

Typ.

Max.

40

38

Units

MHz

%

Input frequency limit (XIN) when enable DCO

Input frequency limit (Differential CLKIN)

Input frequency limit (LVCMOS to X1)

Single ended clock output limit (LVCMOS)

Differential clock output limit (LPHCSL)

Differential clock output limit (LVDS)

Differential clock output limit (LVPECL)

fIN 1

Input Frequency

125

160

500

600

1200

800

55

< 125

< 333

fOUT

Output Frequency

fVCO1

fVCO2

fVCO3

t2

VCO frequency range of PLL1 VCO operating frequency range

VCO frequency range of PLL2 VCO operating frequency range

VCO frequency range of PLL3 VCO operating frequency range

Input Duty Cycle

Duty Cycle

LVCMOS and Differential clock < 333MHz ,

Crossing point measurements

LVCMOS and Differential clock > 333MHz ,

Crossing point measurements

Reference clock output or SE1-3 fan out clock

Single-ended LVCMOS output clock rise and fall

time, 20% to 80% of VDDSE1.8V-3.3V

Single-ended LVCMOS output clock rise and fall

time, 20% to 80% of VDDSE1.8V-3.3V

LVDS, 20% to 80%

t3

Output Duty Cycle

45

55

%

t3

Output Duty Cycle

Output Duty Cycle_REF

Rise/Fall, SLEW[0] = 1

40

60

%

1.0

t4

t5

ns

ps

Rise/Fall, SLEW[0] = 0

1.1

300

Rise Times

Fall Times

Rise Times

Fall Times

LVDS, 80% to 20%

LVPECL, 20% to 80%

LVPECL, 80% to 20%

Cycle-to-Cycle jitter (Peak-to-Peak), multiple

output frequencies switching, differential outputs

(1.8V to 3.3V nominal output voltage)

SE1 = 25MHz

50

ps

*SE2 = 100MHz

*SE3 = 100MHz

DIFF1/2 = 100MHz

t6

Clock Jitter

RMS Phase Jitter (12kHz to 20MHz integration

range) differential output, VDDSE = 3.465V,

25MHz crystal,

SE1 = 25MHz

*SE2 = 100MHz

*SE3 = 100MHz

DIFF1/2 = 100MHz

Skew between the same frequencies, with outputs

using the same driver format

PLL lock time from power-up

32.768kHz clock low power power-up time

PLL lock time from shutdown mode

1.1

75

ps

t7

Output Skew

t8 2

t9

t9 3

Lock Time

20

100

2

ms

10

0.1

1. Practical lower frequency is determined by loop filter settings.

2. Includes loading the configuration bits from EPROM to PLL registers. It does not include EPROM programming/write time.

3. Actual PLL lock time depends on the loop configuration.

4. * SE2/SE3 are not available in 5P35021, only available in 5P35023 QFN24 device.

5. t4 Rise/Fall time measurements are based on 5pF load.

6. t5 Rise/Fall time measurements are based on 2pF load.

NOVEMBER 30, 2017

19

VERSACLOCK^®PROGRAMMABLE CLOCK GENERATOR

5P35021 DATASHEET

PCI Express Jitter Specifications

Unless stated otherwise, VDDDIFF = 3.3 V ±5% or 2.5V ±5%, T = -40° to +85°C

A

PCIe Industry

Specification

Symbol

Parameter

Phase Jitter

Peak-to-Peak

Conditions

Min

Typ

Max

Units Notes

ƒ = 100MHz/125MHz, 25MHz Crystal Input

Evaluation Band: 0Hz - Nyquist (clock frequency/2)

ƒ = 100MHz/125MHz, 25MHz Crystal Input

High Band: 1.5MHz - Nyquist (clock frequency/2)

ƒ = 100MHz/125MHz, 25MHz Crystal Input

Low Band: 10kHz - 1.5MHz

tJ (PCIe Gen1)

30

86

3.10

3.0

ps

1,4

2,4

3,4

tREFCLK_HF_RMS Phase Jitter

(PCIe Gen2) RMS

tREFCLK_LF_RMS Phase Jitter

(PCIe Gen2)

tREFCLK_RMS

(PCIe Gen3)

2.56

0.27

0.8

RMS

ƒ = 100MHz/125MHz, 25MHz Crystal Input

Evaluation Band: 0Hz - Nyquist (clock frequency/2)

Phase Jitter

RMS

1.0

Note: Electrical parameters are guaranteed over the specified ambient operating temperature range, w hich is established w hen the device is mounted in a test socket w ith maintained

transverse airflow greater than 500 lfpm. The device w ill meet specifications after thermal equilibrium has been reached under these conditions.

1. Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1.

2. RMS jitter after applying the tw o evaluation bands to the tw o transfer functions defined in the Common Clock Architecture and reporting the w orst case results for each evaluation band.

Maximum limit for PCI Express Generation 2 is 3.1ps RMS for tREFCLK_HF_RMS (High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band).

3. RMS jitter after applying systemtransfer function for the common clock architecture. This specification is based on the

PCI_Express_Base_r3.0 10 Nov, 2010 specification, and is subject to change pending the final release version of the specification.

4. This parameter is guaranteed by characterization. Not tested in production.

Spread Spectrum Generation Specifications

Symbol

Parameter

Description

Min

Typ

Max

Unit

MHz

kHz

fOUT

Output Frequency Output Frequency Range

1

350

fMOD*

Mod Frequency

Spread Value

Modulation Frequency

30 to 63

-0.5% to -2%

+/-15%

fSPREAD

Amount of Spread Value (programmable) - Down Spread

%fOUT

%

%tolerance*1 Spread % value

Variation of spread range

* input frequency dependent, see programming guide

*1 design target

VERSACLOCK^®PROGRAMMABLE CLOCK GENERATOR

20

NOVEMBER 30, 2017

5P35021 DATASHEET

I2C Bus DC Characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIH

VIL

Input HIGH Level

Input LOW Level

0.7xVDD33

V

0.3xVDD33

VHYS

IIN

VOL

Hysteresis of Inputs

Input Leakage Current

Output LOW Voltage

0.05xVDD33

V

µA

V

±1

0.4

IOL = 3 mA

I2C Bus AC Characteristics

Symbol

FSCLK

tBUF

Parameter

Serial Clock Frequency (SCL)

Bus free time between STOP and START

Min

Typ

100

Max

400

Unit

kHz

µs

1.3

0.6

100

0

tSU:START Setup Time, START

tHD:START Hold Time, START

tSU:DATA Setup Time, data input (SDA)

tHD:DATA Hold Time, data input (SDA) 1

ns

µs

tOVD

CB

tR

tF

tHIGH

tLOW

Output data valid from clock

0.9

400

300

µs

pF

ns

µs

Capacitive Load for Each Bus Line

Rise Time, data and clock (SDA, SCL)

Fall Time, data and clock (SDA, SCL)

HIGH Time, clock (SCL)

20 + 0.1xCB

0.6

1.3

0.6

LOW Time, clock (SCL)

µs

tSU:STOP Setup Time, STOP

Note 1: A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(MIN) of the SCL

signal) to bridge the undefined region of the falling edge of SCL.

NOVEMBER 30, 2017

21

VERSACLOCK^®PROGRAMMABLE CLOCK GENERATOR

5P35021 DATASHEET

General I²C Mode Operations

2

The device acts as a slave device on the I C bus using one of the four I C addresses (0xD0, 0xD2, 0xD4, or 0xD6) to allow

multiple devices to be used in the system. The interface accepts byte-oriented block write and block read operations. Two

address bytes specify the register address of the byte position of the first register to write or read. Data bytes (registers) are

accessed in sequential order from the lowest to the highest byte (most significant bit first). Read and write block transfers can

be stopped after any complete byte transfer. During a write operation, data will not be moved into the registers until the STOP

bit is received, at which point, all data received in the block write will be written simultaneously.

2

For full electrical I C compliance, it is recommended to use external pull-up resistors for SDATA and SCLK. The internal

pull-down resistors have a size of 100k typical.

2

I C Slave Read and Write Cycle Sequencing

Current Read

S

Dev Addr + R

A

Data 0

A

Data 1

A

Data n

Data 0

A

Abar

P

Sequential Read

S

Dev Addr + W

Reg start Addr

A

Sr

Dev Addr + R

A

Data1

A

Data n

Abar

P

Sequential Write

S

Dev Addr + W

Data 0

A

Data 1

A

Data n

A

P

Reg start Addr

S = start

from master to slave

from slave to master

Sr = repeated start

A = acknowledge

Abar = none acknowledge

P = stop

VERSACLOCK^®PROGRAMMABLE CLOCK GENERATOR

22

NOVEMBER 30, 2017

5P35021 DATASHEET

Byte0:

General Control

Byte 00h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Name

Control Function

OTP memory programming indication

I2C address select bit 1

Type

0

1

PWD

OTP_Burned

I2C_addr[1]

I2C_addr[0]

PLL1_SSEN

DIV1_src_sel

PLL3_refin_sel

EN_CLKIN

R/W OTP memory non-programmed

OTP memory programmed

0

R/W

00: D0

10: D4

/

01: D2

11: D6

enable

Xtal

I2C address select bit 0

PLL1 Spread Spectrum enable

Divider 1 source clock select

PLL3 source selection

disable

PLL1

Xtal

disable

read/write

Seed (DIV2)

enable

enable CLKIN

Bit 0

OTP_protect

OTP memory protection

write locked

Byte1:

Dash Code ID (optional)

Byte 01h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Name

Control Function

Dash code ID

Type

R/W

0

-

1

-

PWD

DashCode ID[7]

DashCode ID[6]

DashCode ID[5]

DashCode ID[4]

DashCode ID[3]

DashCode ID[2]

DashCode ID[1]

DashCode ID[0]

0

Bit 0

Byte2:

Crystal Cap setting

Byte 02h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Name

Control Function

Type

R/W

0

1

PWD

Xtal_Cap[7]

Xtal_Cap[6]

Xtal_Cap[5]

Xtal_Cap[4]

Xtal_Cap[3]

Xtal_Cap[2]

Xtal_Cap[1]

Xtal_Cap[0]

Xtal cap load trimming bits

0

1

0

1

x1 x2

x4 x8

total 15pf

Bit 0

Byte3:

PLL3 M Divider

Byte 03h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Name

Control Function

PLL3 source clock divider

PLL3 reference integer divider

Type

R/W

0

1

PWD

PLL3_MDIV1

PLL3_MDIV2

PLL3 M_DIV[5]

PLL3 M_DIV[4]

PLL3 M_DIV[3]

PLL3 M_DIV[2]

PLL3 M_DIV[1]

PLL3 M_DIV[0]

disable M DIV1

disable M DIV2

bypadd divider (/1)

bypadd divider (/2)

0

1

0

1

3~64

default 25

-

Bit 0

Byte4:

PLL3 N Divider

Byte 04h

Bit 7

Bit 6

Name

Control Function

Type

R/W

0

1

PWD

PLL3 N_DIV[7]

PLL3 N_DIV[6]

PLL3 N_DIV[5]

PLL3 N_DIV[4]

PLL3 N_DIV[3]

PLL3 N_DIV[2]

PLL3 N_DIV[1]

PLL3 N_DIV[0]

PLL3 VCO feedback integer divider bit7

PLL3 VCO feedback integer divider bit6

PLL3 VCO feedback integer divider bit5

PLL3 VCO feedback integer divider bit4

PLL3 VCO feedback integer divider bit3

PLL3 VCO feedback integer divider bit2

PLL3 VCO feedback integer divider bit1

PLL3 VCO feedback integer divider bit0

1

0

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

12~2048, default VCO setting is 480MHz

Bit 0

NOVEMBER 30, 2017

23

VERSACLOCK^®PROGRAMMABLE CLOCK GENERATOR

5P35021 DATASHEET

Byte5:

PLL3 Loop filter setting and N Divider10:8

Byte 05h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Name

Control Function

Type

R/W

0

1

PWD

PLL3_R100K

PLL3_R50K

PLL3_R25K

PLL3_R12.5K

PLL3_R6K

PLL3 N_DIV[10]

PLL3 N_DIV[9]

PLL3 N_DIV[8]

PLL3 Loop filter resister 100Kohm

PLL3 Loop filter resister 50Kohm

PLL3 Loop filter resister 25Kohm

PLL3 Loop filter resister 12.5Kohm

PLL3 Loop filter resister 6Kohm

PLL3 VCO feedback integer divider bit10

PLL3 VCO feedback integer divider bit9

PLL3 VCO feedback integer divider bit8

bypass

plus 100Kohm

plus 50Kohm

plus 25Kohm

plus 12.5Kohm

only 6Kohm applied

0

1

0

1

12~2048, default VCO setting is 480MHz

Bit 0

Byte6:

PLL3 charge pump control

Byte 06h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Name

Control Function

Output divider 3 source clock selection

PLL3 charge pump control

PLL3 SiRef current selection

Type

R/W

0

PLL2

1

PLL3

x8

x4

x2

x1

/24

/3

PWD

OUTDIV 3 Source

PLL3_CP_8X

PLL3_CP_4X

PLL3_CP_2X

PLL3_CP_1X

PLL3_CP_/24

PLL3_CP_/3

PLL3_SIREF

0

1

0

1

0

-

Bit 0

10uA

20uA

Notes:

Formula : (iRef (10uA) * (1+SIREF) *(1*1X+2*2X+4*4X+8*8X+16*16X))/((24*/24)+(3*/3))

Byte7:

PLL1 Control and OUTDIV5 divider

Byte 07h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Name

PLL1_MDIV_Doubler

PLL1_SIREF

PLL1_EN_CH2

PLL1_EN_3rdpole

OUTDIV5[3]

Control Function

PLL1 reference clock doubler

PLL1 SiRef current selection

PLL1 output Channel 2 control

PLL1 3rd Pole control

Output divider5 control bit 3

Output divider5 control bit 2

Output divider5 control bit 1

Output divider5 control bit 0

Type

R/W

0

1

PWD

disable

10.8uA

disable

enable

21.6uA

enable

0

1

0

1

-

OUTDIV5[2]

OUTDIV5[1]

Bit 0

OUTDIV5[0]

Byte8:

PLL1 M Divider

Byte 08h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Name

Control Function

Type

R/W

0

1

PWD

PLL1_MDIV1

PLL1_MDIV2

PLL1 M_DIV[5]

PLL1 M_DIV[4]

PLL1 M_DIV[3]

PLL1 M_DIV[2]

PLL1 M_DIV[1]

PLL1 M_DIV[0]

PLL3 VCO referenceclock divider 1

PLL3 VCO referenceclock divider 2

PLL1 reference clock divider control bit 5

PLL1 reference clock divider control bit 4

PLL1 reference clock divider control bit 3

PLL1 reference clock divider control bit 2

PLL1 reference clock divider control bit 1

PLL1 reference clock divider control bit 0

disable M DIV1

disable M DIV2

bypass divider (/1)

bypass divider (/2)

0

1

0

1

3~64, default is 25

Bit 0

Byte9:

PLL1 VCO N divider

Byte 09h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Name

Control Function

Type

R/W

0

1

PWD

PLL1 N_DIV[7]

PLL1 N_DIV[6]

PLL1 N_DIV[5]

PLL1 N_DIV[4]

PLL1 N_DIV[3]

PLL1 N_DIV[2]

PLL1 N_DIV[1]

PLL1 N_DIV[0]

PLL1 VCO feedback divider control bit 7

PLL1 VCO feedback divider control bit 6

PLL1 VCO feedback divider control bit 5

PLL1 VCO feedback divider control bit 4

PLL1 VCO feedback divider control bit 3

PLL1 VCO feedback divider control bit 2

PLL1 VCO feedback divider control bit 1

PLL1 VCO feedback divider control bit 0

0

1

0

1

0

12~2048, default is 600

Bit 0

VERSACLOCK^®PROGRAMMABLE CLOCK GENERATOR

24

NOVEMBER 30, 2017

5P35021 DATASHEET

Byte10:

PLL loop filter and N divider

Byte 0Ah

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Name

PLL1_R100K

PLL1_R50K

Control Function

Type

R/W

0

1

PWD

PLL1 Loop filter resister 100Kohm

PLL1 Loop filter resister 50Kohm

PLL1 Loop filter resister 25Kohm

PLL1 Loop filter resister 12.5Kohm

PLL1 Loop filter resister 1Kohm

PLL1 VCO feedback integer divider bit10

PLL1 VCO feedback integer divider bit9

PLL1 VCO feedback integer divider bit8

bypass

plus 100Kohm

plus 50Kohm

plus 25Kohm

1

0

1

0

1

0

PLL1_R25K

PLL1_R12.5K

PLL1_R1.0K

PLL1 N_DIV[10]

PLL1 N_DIV[9]

PLL1 N_DIV[8]

plus 12.5Kohm

only 1.0Kohm applied

'12~2048, default is 600

Bit 0

Byte11:

PLL1 charge pump

Byte 0Bh

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Name

Control Function

Type

R/W

0

-

1

PWD

PLL1_CP_32X

PLL1_CP_16X

PLL1_CP_8X

PLL1_CP_4X

PLL1_CP_2X

PLL1_CP_1X

PLL1_CP_/24

PLL1_CP_/3

PLL1 charge pump control

x32

x16

x8

x4

x2

x1

/24

/3

0

1

0

Bit 0

Byte12:

PLL1 spread spectrum control

Name

Byte 0Ch

Control Function

Type

0

1

PWD

Bit 7

PLL1_SS_REFDIV23

PLL1 Spread Spectrum control- Ref divider 23 R/W

-

0

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PLL1_SS_REFDIV[6]

PLL1_SS_REFDIV[5]

PLL1_SS_REFDIV[4]

PLL1_SS_REFDIV[3]

PLL1_SS_REFDIV[2]

PLL1_SS_REFDIV[1]

PLL1_SS_REFDIV[0]

PLL1 Spread Spectrum control- Ref divider 6 R/W

PLL1 Spread Spectrum control- Ref divider 5 R/W

PLL1 Spread Spectrum control- Ref divider 4 R/W

PLL1 Spread Spectrum control- Ref divider 3 R/W

PLL1 Spread Spectrum control- Ref divider 2 R/W

PLL1 Spread Spectrum control- Ref divider 1 R/W

PLL1 Spread Spectrum control- Ref divider 0 R/W

-

0

Byte13:

PLL1 spread spectrum control

Name

Byte 0Dh

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Control Function

Type

R/W

0

-

1

-

PWD

PLL1_SS_FBDIV[7]

PLL1_SS_FBDIV[6]

PLL1_SS_FBDIV[5]

PLL1_SS_FBDIV[4]

PLL1_SS_FBDIV[3]

PLL1_SS_FBDIV[2]

PLL1_SS_FBDIV[1]

PLL1_SS_FBDIV[0]

PLL1 Spread Spectrum - feedback divider 7

PLL1 Spread Spectrum - feedback divider 6

PLL1 Spread Spectrum - feedback divider 5

PLL1 Spread Spectrum - feedback divider 4

PLL1 Spread Spectrum - feedback divider 3

PLL1 Spread Spectrum - feedback divider 2

PLL1 Spread Spectrum - feedback divider 1

PLL1 Spread Spectrum - feedback divider 0

0

Bit 0

Byte14:

PLL1 Spread spectrum control

Name

Byte 0Eh

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Control Function

Type

0

-

1

-

PWD

PLL1_SS_FBDIV[15]

PLL1_SS_FBDIV[14]

PLL1_SS_FBDIV[13]

PLL1_SS_FBDIV[12]

PLL1_SS_FBDIV[11]

PLL1_SS_FBDIV[10]

PLL1_SS_FBDIV[09]

PLL1_SS_FBDIV[08]

PLL1 Spread Spectrum - feedback divider 15 R/W

PLL1 Spread Spectrum - feedback divider 14 R/W

PLL1 Spread Spectrum - feedback divider 13 R/W

PLL1 Spread Spectrum - feedback divider 12 R/W

PLL1 Spread Spectrum - feedback divider 11 R/W

PLL1 Spread Spectrum - feedback divider 10 R/W

0

PLL1 Spread Spectrum - feedback divider 9

PLL1 Spread Spectrum - feedback divider 8

R/W

Bit 0

NOVEMBER 30, 2017

25

VERSACLOCK^®PROGRAMMABLE CLOCK GENERATOR

5P35021 DATASHEET

Byte15:

Output divider1 control

Byte 0Fh

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Name

Control Function

Type

R/W

0

-

1

-

PWD

OUTDIV1[3]

OUTDIV1[2]

OUTDIV1[1]

OUTDIV1[0]

OUTDIV2[3]

OUTDIV2[2]

OUTDIV2[1]

OUTDIV2[0]

Output divider1 control bit 3

Output divider1 control bit 2

Output divider1 control bit 1

Output divider1 control bit 0

Output divider2 control bit 3

Output divider2 control bit 2

Output divider2 control bit 1

Output divider2 control bit 0

0

1

0

1

Bit 0

Byte16:

PLL2 integer feedback divider

Byte 10h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Name

reserved

Control Function

Type

R/W

0

-

1

-

PWD

-

0

reserved

-

PLL2_FB_INT[10]

PLL2_FB_INT[9]

PLL2_FB_INT[8]

PLL2 feedback integer divider 10

PLL2 feedback integer divider 9

PLL2 feedback integer divider 8

Bit 0

Byte17:

PLL2 integer feedback divider

Byte 11h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Name

Control Function

Type

R/W

0

-

1

-

PWD

PLL2_FB_INT_DIV[7]

PLL2_FB_INT_DIV[6]

PLL2_FB_INT_DIV[5]

PLL2_FB_INT_DIV[4]

PLL2_FB_INT_DIV[3]

PLL2_FB_INT_DIV[2]

PLL2_FB_INT_DIV[1]

PLL2_FB_INT_DIV[0]

PLL2 feedback integer divider 7

PLL2 feedback integer divider 6

PLL2 feedback integer divider 5

PLL2 feedback integer divider 4

PLL2 feedback integer divider 3

PLL2 feedback integer divider 2

PLL2 feedback integer divider 1

PLL2 feedback integer divider 0

0

1

0

1

0

Bit 0

Byte18:

PLL2 fractional feedback divider

Byte 12h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Control Function

Type

R/W

0

-

1

-

PWD

PLL2_FB_FRC_DIV[7]

PLL2_FB_FRC_DIV[6]

PLL2_FB_FRC_DIV[5]

PLL2_FB_FRC_DIV[4]

PLL2_FB_FRC_DIV[3]

PLL2_FB_FRC_DIV[2]

PLL2_FB_FRC_DIV[1]

PLL2_FB_FRC_DIV[0]

PLL2 feedback fractional divider 7

PLL2 feedback fractional divider 6

PLL2 feedback fractional divider 5

PLL2 feedback fractional divider 4

PLL2 feedback fractional divider 3

PLL2 feedback fractional divider 2

PLL2 feedback fractional divider 1

PLL2 feedback fractional divider 0

0

Byte19:

PLL2 fractional feedback divider

Name

Byte 13h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Control Function

Type

R/W

0

-

1

-

PWD

PLL2_FB_FRC_DIV[15]

PLL2_FB_FRC_DIV[14]

PLL2_FB_FRC_DIV[13]

PLL2_FB_FRC_DIV[12]

PLL2_FB_FRC_DIV[11]

PLL2_FB_FRC_DIV[10]

PLL2_FB_FRC_DIV[9]

PLL2_FB_FRC_DIV[8]

PLL2 feedback fractional divider 15

PLL2 feedback fractional divider 14

PLL2 feedback fractional divider 13

PLL2 feedback fractional divider 12

PLL2 feedback fractional divider 11

PLL2 feedback fractional divider 10

PLL2 feedback fractional divider 9

PLL2 feedback fractional divider 8

0

Bit 0

VERSACLOCK^®PROGRAMMABLE CLOCK GENERATOR

26

NOVEMBER 30, 2017

5P35021 DATASHEET

Byte20:

PLL2 spread spectrum control

Byte 14h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Control Function

Type

R/W

0

-

1

-

PWD

PLL2_STEP[7]

PLL2_STEP[6]

PLL2_STEP[5]

PLL2_STEP[4]

PLL2_STEP[3]

PLL2_STEP[2]

PLL2_STEP[1]

PLL2_STEP[0]

PLL2 spread step size control bit 7

PLL2 spread step size control bit 6

PLL2 spread step size control bit 5

PLL2 spread step size control bit 4

PLL2 spread step size control bit 3

PLL2 spread step size control bit 2

PLL2 spread step size control bit 1

PLL2 spread step size control bit 0

0

Byte21:

PLL2 spread spectrum control

Byte 15h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Name

Control Function

Type

R/W

0

-

1

-

PWD

PLL2_STEP[15]

PLL2_STEP[14]

PLL2_STEP[13]

PLL2_STEP[12]

PLL2_STEP[11]

PLL2_STEP[10]

PLL2_STEP[9]

PLL2_STEP[8]

PLL2 spread step size control bit 15

PLL2 spread step size control bit 14

PLL2 spread step size control bit 13

PLL2 spread step size control bit 12

PLL2 spread step size control bit 11

PLL2 spread step size control bit 10

PLL2 spread step size control bit 9

PLL2 spread step size control bit 8

0

Bit 0

Byte22:

PLL2 spread spectrum control

Name

Byte 16h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Control Function

Type

R/W

0

-

1

-

PWD

PLL2_STEP_DELTA[7]

PLL2_STEP_DELTA[6]

PLL2_STEP_DELTA[5]

PLL2_STEP_DELTA[4]

PLL2_STEP_DELTA[3]

PLL2_STEP_DELTA[2]

PLL2_STEP_DELTA[1]

PLL2_STEP_DELTA[0]

PLL2 spread step size control delta bit 7

PLL2 spread step size control delta bit 6

PLL2 spread step size control delta bit 5

PLL2 spread step size control delta bit 4

PLL2 spread step size control delta bit 3

PLL2 spread step size control delta bit 2

PLL2 spread step size control delta bit 1

PLL2 spared step size control delta bit 0

0

Bit 0

Byte23:

PLL2 period control

Byte 17h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Name

Control Function

Type

R/W

0

-

1

-

PWD

PLL2_PERIOD[7]

PLL2_PERIOD[6]

PLL2_PERIOD[5]

PLL2_PERIOD[4]

PLL2_PERIOD[3]

PLL2_PERIOD[2]

PLL2_PERIOD[1]

PLL2_PERIOD[0]

PLL2 period control bit 7

PLL2 period control bit 6

PLL2 period control bit 5

PLL2 period control bit 4

PLL2 period control bit 3

PLL2 period control bit 2

PLL2 period control bit 1

PLL2 period control bit 0

0

Bit 0

Byte24:

PLL2 control register

Byte 18h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Control Function

PLL2 period control bit 9

PLL2 period control bit 8

Type

R/W

0

-

1

-

PWD

PLL2_PERIOD[9]

PLL2_PERIOD[8]

PLL2_SSEN

PLL2_R100K

PLL2_R50K

PLL2_R25K

PLL2_R12.5K

PLL2_R6K

0

PLL2 spread spectrum enable

PLL2 Loop filter resister 100Kohm

PLL2 Loop filter resister 50Kohm

PLL2 Loop filter resister 25Kohm

PLL2 Loop filter resister 12.5Kohm

PLL2 Loop filter resister 6Kohm

disable

bypass

enable

plus 100Kohm

plus 50Kohm

plus 25Kohm

plus 12.5Kohm

only 6Kohm applied

NOVEMBER 30, 2017

27

VERSACLOCK^®PROGRAMMABLE CLOCK GENERATOR

5P35021 DATASHEET

Byte25:

PLL2 charge pump control

Byte 19h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Name

Control Function

Type

R/W

0

-

1

x16

x8

x4

x2

x1

/24

/3

PWD

PLL2_CP_16X

PLL2_CP_8X

PLL2_CP_4X

PLL2_CP_2X

PLL2_CP_1X

PLL2_CP_/24

PLL2_CP_/3

PLL2_SIREF

PLL2 charge pump control

PLL2 SiRef current selection

0

1

0

1

0

Bit 0

10uA

20uA

Byte26:

PLL2 M divider setting

Byte 1Ah

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Name

PLL2_MDIV_Doubler

PLL2_MDIV1

Control Function

PLL2 reference divider - doubler

PLL2 reference divider 1

Type

R/W

0

1

PWD

disable

disable M DIV1

disable M DIV2

enable

bypadd divider (/1)

bypadd divider (/2)

0

1

0

PLL2_MDIV2

PLL2 reference divider 2

PLL2_MDIV[4]

PLL2_MDIV[3]

PLL2_MDIV[2]

PLL2_MDIV[1]

PLL2_MDIV[0]

PLL2 reference divider control bit 4

PLL2 reference divider control bit 3

PLL2 reference divider control bit 2

PLL2 reference divider control bit 1

PLL2 reference divider control bit 0

3~64, default is 25

Bit 0

Byte27:

Output divider 4

Byte 1Bh

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Name

Control Function

Type

R/W

0

-

1

-

PWD

OUTDIV3[3]

OUTDIV3[2]

OUTDIV3[1]

OUTDIV3[0]

OUTDIV4[3]

OUTDIV4[2]

OUTDIV4[1]

OUTDIV4[0]

Out divider 3 control bit 7

Out divider 3 control bit 6

Out divider 3 control bit 5

Out divider 3 control bit 4

Out divider 4 control bit 3

Out divider 4 control bit 2

Out divider 4 control bit 1

Out divider 4 control bit 0

0

1

0

1

Bit 0

Byte28:

PLL operation control register

Name

Byte 1Ch

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Control Function

Type

0

1

enable (shift 4 bits)

DIV2

PWD

PLL2_HRS_EN

PLL2_refin_sel

PLL3_PDB

PLL2 spread high resolution selection enable R/W

normal

Xtal

0

1

PLL2 reference clock source select

PLL3 Power Down

PLL3 lock bypass

R/W

Power Down

bypass lock

Power Down

bypass lock

Power Down

bypass lock

running

lock

running

lock

running

lock

PLL3_LCKBYPSSB

PLL2_PDB

PLL2_LCKBYPSSB

PLL1_PDB

PLL2 Power Down

PLL2 lock bypass

PLL1 Power Down

PLL1 lock bypass

Bit 0

PLL1_LCKBYPSSB

Byte29:

Output control

Byte 1Dh

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Name

DIFF1_SEL

DIFF2_SEL

DIFF1_EN

Control Function

Differential clock 1 output OE2 control

Differential clock 2 output OE2 control

Differential clock 1 output enable

Differential clock 2 output enable

Output divider 4 source clock selection

SE 1 slew rate control

Type

0

1

PWD

not controlled

disable

controlled

enable

Xtal

0

1

0

R/W

DIFF2_EN

disable

PLL2

normal

OUTDIV4_Source

SE1_SLEW

VDD1_SEL[1]

VDD1_SEL[0]

strong

VDD1 level control bit 1

00/01: 3.3V 10: 2.5V 11: 1.8

Bit 0

VDD1 level control bit 0

VERSACLOCK^®PROGRAMMABLE CLOCK GENERATOR

28

NOVEMBER 30, 2017

5P35021 DATASHEET

Byte30:

OE and DFC control

Byte 1Eh

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Name

SE1_EN

Control Function

Type

R/W

0

1

PWD

SE1 output enable control

OE1 pin function selection bit 1

OE1 pin function selection bit 0

SE3 output enable

OE3 pin function selection bit 1

OE3 pin function selection bit 0

DFC frequency select bit 1

DFC frequency select bit 0

disable

enable

1

0

1

0

OE1_fun_sel[1]

OE1_fun_sel[0]

* SE3_EN

* OE3_fun_sel[1]

* OE3_fun_sel[0]

* DFC_SW_Sel[1]

* DFC_SW_Sel[0]

11:DFC0

01: PD#

10: SE1_PPS

00: SE1 OE

disable

enable

11: DFC1 10: SE3_PPS

01:xx 00:SE3_OE

00: N0 01: N1 10:N2 11:N3

Bit 0

Byte31:

Control Register

Byte 1Fh

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Name

Control Function

SE2 32K free run

Type

0

1

B31 bit6 control source

DIV4

PWD

* SE2_Freerun_32K

* SE2_CLKSEL1

* VDD2_SEL[1]

* VDD2_SEL[0]

* SE2_SLEW

PLL2_3rd_EN_CFG

PLL2_EN_CH2

PLL2_EN_3rdpole

freerun 32K

DIV5

1

0

1

0

1

SE2 source clock selection

VDD2 level control bit 1

VDD2 level control bit 0

SE 2 slew rate control

PLL2 3rd order control

PLL2 channel 2 enable control

PLL2 3rd Pole control

R/W

00/01: 3.3V 10: 2.5V 11: 1.8

normal

1st order

disable

strong

3rd order

enable

R/W

Bit 0

enable

Byte32:

Control Register

Byte 20h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Name

* SE2_EN

* OE2_fun_sel[1]

* OE2_fun_sel[0]

DFC_EN

Control Function

SE2 output enable

OE2 pin function selection bit 1

OE2 pin function selection bit 0

DFC function control

WatchDog timer control

Watchdog timer select bit 1

Watchdog timer select bit 0

Alarm Status(Read Only)

Type

R/W

R

0

1

PWD

disable

enable

1

0

11: RESET 10: SE2_PPS

01: DIFF1/2 OE 00: SE2 OE

disable

enable

WD_EN

Timer_sel<1>

Timer_sel<0>

Alarm_Flag

00: 250mS 01: 500ms

10: 2S 11: 4S

Bit 0

No alarm

Alarmed

Byte33:

SE3 and DIFF1 Control Register

Byte 21h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Control Function

SE3 32K free run

SE3 source clock selection

VDD3 level control bit 1

VDD3 level control bit 0

SE 3 slew rate control

Type

R/W

0

1

PWD

* SE3_Freerun_32K

* SE3_CLKSEL1

* VDD3_SEL[1]

* VDD3_SEL[0]

* SE3_SLEW

DIFF_PDBHiZEN

DIFF1_CMOS2_FLIP

DIFF2_CMOS2_FLIP

freerun 32K

DIV2

DIV2 or DIV4 selected by B33bit6

DIV4

1

0

11: 1.8V 10: 2.5V

0x: 3.3V

normal

TBD

DIFF1_B inverted

DIFF2_B inverted

strong

Differential output high-Z at power down

Differential 1/2 LVCMOS output control

output tri-state, bias off

DIFF1_B non-inverted

DIFF2_B non-inverted

Byte34:

DIFF1 Control Register

Byte 22h

Bit 7

Bit 6

Name

DIFF1_CLK_SEL

DIFF1_io_pwr_sel

Control Function

Differential clock 1 source selection

Differential clock 1 output power

Type

R/W

0

DIV1

2.5V

1

DIV3

3.3V

PWD

1

Bit 5

DIFF1_OUTPUT_TYPE[1]

Differential clock 1 type select bit 1

Differential clock 1 type select bit 0

R/W

1

00: LVMOS 01: LVDS

10: LVPECL 11: LPHCSL

Bit 4

Bit 3

DIFF1_OUTPUT_TYPE[0]

DIFF1_AMP[1]

1

0

LPHCSL: 00=740mV,01=800mV,10=855mV,11=910mV

LPECL:00=710mV,01=810mV,10=875mV,11=920mV

LVDS:00=311mV,01=344mV,10=376mV,11=408mV

Differential clock 1 amplitude control bit 1

Differential clock 1 amplitude control bit 0

R/W

Bit 2

Bit 1

DIFF1_AMP[0]

1

0

DIFF1_CMOS_SLEW

Differential clock 1 LVCMOS slew rate control R/W

Differential clock 1 LVCMOS output_B control R/W

normal

strong

Bit 0

D1FF1_CMOS2_EN

disable

enable

0

NOVEMBER 30, 2017

29

VERSACLOCK^®PROGRAMMABLE CLOCK GENERATOR

5P35021 DATASHEET

Byte35:

DIFF2 Control Register

Byte 23h

Bit 7

Bit 6

Name

DIFF2_CLK_SEL

DIFF2_IO_PWR_SEL

Control Function

Differential clock 2 source selection

Differential clock 2 output power

Type

R/W

0

DIV1

2.5V

1

DIV3

3.3V

PWD

0

1

Bit 5

Bit 4

DIFF2_OUTPUT_TYPE[1]

DIFF2_OUTPUT_TYPE[0]

Differential clock 2 type select bit 1

Differential clock 2 type select bit 0

R/W

1

00: LVMOS 01: LVDS

10: LVPECL 11: LPHCSL

LPHCSL: 00=740mV,01=800mV,10=855mV,11=910mV

LPECL:00=710mV,01=810mV,10=875mV,11=920mV

LVDS:00=311mV,01=344mV,10=376mV,11=408mV

Bit 3

Bit 2

DIFF2_AMP[1]

DIFF2_AMP[0]

Differential clock 2 amplitude control bit 1

Differential clock 2 amplitude control bit 0

R/W

0

1

Bit 1

Bit 0

DIFF2_CMOS_SLEW

DIFF2_CMOS2_EN

Differential clock 2 LVCMOS slew rate control R/W

Differential clock 2 LVCMOS output_B control R/W

normal

disable

strong

enable

0

Byte36:

SE1 and DIV4 control

Byte 24h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Name

I2C_PDB

Ref_free_run

Control Function

chip power down control bit

Reference clock output (SE2/SE3)

SE clocks free run control

SE1 clock output default

SEL1 output select

REF output enable

DIV4 channel 3 output control

DIV4 channel 2 output control

Type

R/W

0

1

normal

freerun

PWD

power down

stop

SE2 free run

32K freerun

DIV5

1

0

1

0

free_run_output_config

SE1_Freerun_32K

SE1_CLKSEL1

REF_EN

SE2/3 free run

B36bit3 control

DIV4

disable

enable

DIV4_CH3_EN

DIV4_CH2_EN

Bit 0

disable

enable

VERSACLOCK^®PROGRAMMABLE CLOCK GENERATOR

30

NOVEMBER 30, 2017

5P35021 DATASHEET

Package Outline Drawings (NDG20)

NOVEMBER 30, 2017

31

VERSACLOCK^®PROGRAMMABLE CLOCK GENERATOR

5P35021 DATASHEET

Package Outline Drawings (NDG20), cont.

VERSACLOCK^®PROGRAMMABLE CLOCK GENERATOR

32

NOVEMBER 30, 2017

5P35021 DATASHEET

Marking Diagrams

-000

-ddd

35021

YW**$

35021

YW**$

Notes:

1. Line 1&2: truncated part number

2. “-000” denotes blank part.

3. “-ddd” denotes dash code.

4. “**” is the lot sequence number.

5. “YW” is the last digit of the year and week that the part was assembled.

6. “$” is the mark code.

Ordering Information

Part / Order Number

5P35021-000NDGI

5P35021-000NDGI8

5P35021-dddNDGI

5P35021-dddNDGI8

Shipping Packaging

Tubes

Package

20-pin QFN

Temperature

-40° to +85°C

Tape and Reel

Tubes

Tape and Reel

Revision History

Date

Description of Change

11/30/17

01/25/17

Updated I²C section.

1. Corrected typos in Byte 27.

2. Updated package outline drawing.

09/20/16

05/26/16

Changed package outline drawing EPAD reference from 1.10mm to 1.65mm.

Initial release.

NOVEMBER 30, 2017

33

VERSACLOCK^®PROGRAMMABLE CLOCK GENERATOR

Corporate Headquarters

6024 Silver Creek Valley Road

San Jose, CA 95138 USA

www.idt.com

Sales

Tech Support

www.idt.com/go/support

1-800-345-7015 or 408-284-8200

Fax: 408-284-2775

www.idt.com/go/sales

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time, without

notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed

in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any

particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intel-

lectual property rights of IDT or any third parties.

IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably

expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.

Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of

5P35021 NOVEMBER 30, 2017

34

厂商	型号	描述	页数
IDT	5P30001GI8	[ Low Skew Clock Driver, 5P Series, 4 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, 2 X 2 MM, 0.50 MM PITCH, ROHS COMPLIANT, DFN-8 ]	7 页
IDT	5P30017NDGI8	[ Low Skew Clock Driver, 5P Series, 2 True Output(s), 0 Inverted Output(s), CMOS, PDSO6, 1.40 X 1.40 MM, 0.40 MM PITCH, ROHS COMPLIANT, DFN-6 ]	8 页
IDT	5P35021	[ VersaClock Programmable Clock Generator ]	34 页
IDT	5P35021-000NDGI	[ Programmable Clock Generator ]	34 页
IDT	5P35021-000NDGI8	[ Programmable Clock Generator ]	34 页
IDT	5P35021-dddNDGI	[ Programmable Clock Generator ]	34 页
IDT	5P35021-dddNDGI8	[ Programmable Clock Generator ]	34 页
IDT	5P35021_17	[ Programmable Clock Generator ]	34 页
IDT	5P35023-000NLGI	[ Programmable Clock Generator ]	34 页
IDT	5P35023-000NLGI8	[ Programmable Clock Generator ]	34 页