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KXPC857TZP100B

型号：

KXPC857TZP100B

品牌：

MOTOROLA[ MOTOROLA ]

页数：

20 页

PDF大小：

311 K

下载PDF手册
Advance Information  
MPC857TEC/D  
Rev. 0.4, 5/2003  
MPC857T  
Hardware Specifications  
This document provides detailed information on power considerations, DC/AC electrical  
characteristics, and AC timing specifications for the MPC857T (refer to Table 1). The  
MPC857T contains a PowerPC™ processor core. This document contains the following  
topics:  
Topic  
Page  
Part I, “Overview”  
1
Part II, “Features”  
2
Part III, “Maximum Tolerated Ratings”  
Part IV, “Thermal Characteristics”  
Part V, “Power Dissipation”  
6
7
8
Part VI, “DC Characteristics”  
9
Part VII, “Thermal Calculation and Measurement”  
Part VIII, “Layout Practices”  
10  
12  
13  
40  
41  
64  
65  
68  
81  
Part IX, “Bus Signal Timing”  
Part X, “IEEE 1149.1 Electrical Specifications”  
Part XI, “CPM Electrical Characteristics”  
Part XII, “UTOPIA AC Electrical Specifications”  
Part XIII, “FEC Electrical Characteristics”  
Part XIV, “Mechanical Data and Ordering Information”  
Part XV, “Document Revision History  
Part I Overview  
The MPC857T is a derivative of Motorola’s MC68360 Quad Integrated Communications  
Controller (QUICC™) and part of the PowerQUICC™ family of devices. It is a versatile  
single-chip integrated microprocessor and peripheral combination that can be used in a variety  
of controller applications and communications and networking systems. The MPC8577T  
provides enhanced ATM functionality over that of other ATM-enabled members of the  
MPC860 family.  
The CPU on the MPC857T is a 32-bit MPC8xx core that incorporates memory management  
units (MMUs) and instruction and data caches. The communications processor module (CPM)  
from the MC68360 QUICC has been enhanced by the addition of the inter-integrated  
2
controller (I C) channel. The memory controller has been enhanced, enabling the MPC857T  
Features  
to support any type of memory, including high-performance memories and new types of DRAMs. A  
PCMCIA socket controller supports up to two sockets. A real-time clock has also been integrated.  
Table 1 shows the functionality supported by the MPC857T and MPC857DSL.  
Table 1. MPC857T Functionality  
Cache  
Ethernet  
Part  
SCC  
Instruction  
Cache  
Data Cache  
10T  
10/100  
MPC857T  
4 Kbyte  
4 Kbyte  
4 Kbyte  
4 Kbyte  
Up to 4  
Up to 4  
1
1
1
1
MPC857DSL  
Unless otherwise specified, the PowerQUICC unit is referred to as the MPC857T in this document.  
Part II Features  
The following list summarizes the key MPC857T features:  
•
Embedded single-issue, 32-bit MPC8xx core (implementing the PowerPC architecture) with  
thirty-two 32-bit general-purpose registers (GPRs)  
— The core performs branch prediction with conditional prefetch, without conditional execution  
— 4-Kbyte data cache and 4- Kbyte instruction cache (see Table 1).  
– 4-Kbyte instruction cache is two-way, set-associative with 128 sets.  
– 4-Kbyte data cache is two-way, set-associative with 128 sets.  
– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word)  
cache blocks.  
– Caches are physically addressed, implement a least recently used (LRU) replacement  
algorithm, and are lockable on a cache block basis.  
— MMU with 32-entry TLB, fully associative instruction and data TLBs  
— MMU supports multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address  
spaces and 16 protection groups  
— Advanced on-chip-emulation debug mode  
•
The MPC857T provides enhancedATM functionality over that of the MPC860SAR. The MPC857T  
adds major new features available in “enhanced SAR” (ESAR) mode, including the following:  
— Multiple APC priority levels available to support a range of traffic pace requirements  
— Port-to-port switching capability without the need for RAM-based microcode  
— Simultaneous MII (100Base-T) and UTOPIA (half-duplex) capability  
— Optional statistical cell counters per PHY  
2
— Parameter RAM for both SPI and I C can be relocated without RAM-based microcode.  
— Supports full-duplex UTOPIA master (ATM side) operation using a “split” bus  
Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)  
32 address lines  
•
•
•
•
Operates at up to 80 MHz  
Memory controller (eight banks)  
2
MPC857THardwareSpecifications  
MOTOROLA  
Features  
— Contains complete dynamic RAM (DRAM) controller  
— Each bank can be a chip select or RAS to support a DRAM bank  
— Up to 30 wait states programmable per memory bank  
— Glueless interface to DRAM, SIMMS, SRAM, EPROMs, flash EPROMs, and other memory  
devices.  
— DRAM controller programmable to support most size and speed memory interfaces  
— Four CAS lines, four WE lines, one OE line  
— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)  
— Variable block sizes (32 Kbyte–256 Mbyte)  
— Selectable write protection  
— On-chip bus arbitration logic  
•
General-purpose timers  
— Four 16-bit timers or two 32-bit timers  
— Gate mode can enable/disable counting  
— Interrupt can be masked on reference match and event capture  
Fast Ethernet controller (FEC)  
•
•
— Simultaneous MII (100Base-T) and UTOPIA operation when using the UTOPIA multiplexed  
bus.  
System integration unit (SIU)  
— Bus monitor  
— Software watchdog  
— Periodic interrupt timer (PIT)  
— Low-power stop mode  
— Clock synthesizer  
— Decrementer, time base, and real-time clock (RTC) from the PowerPC architecture  
— Reset controller  
— IEEE 1149.1 test access port (JTAG)  
Interrupts  
•
•
— Seven external interrupt request (IRQ) lines  
— 12 port pins with interrupt capability  
— 20 internal interrupt sources  
— Programmable highest priority request  
Communications processor module (CPM)  
— RISC controller  
— Communication-specific commands (for example, GRACEFUL STOP TRANSMIT, ENTER HUNT  
MODE, and RESTART TRANSMIT)  
— Supports continuous mode transmission and reception on all serial channels  
— Up to 8-Kbytes of dual-port RAM  
— 10 serial DMA (SDMA) channels  
— Three parallel I/O registers with open-drain capability  
Four baud rate generators  
•
MOTOROLA  
MPC857THardwareSpecifications  
3
Features  
— Independent (can be connected to any SCC or SMC)  
— Allow changes during operation  
— Autobaud support option  
•
One SCC (serial communication controller) (The MPC857DSL supports ethernet only)  
— Serial ATM capability  
— Ethernet/IEEE 802.3 supporting full 10-Mbps operation  
— HDLC/SDLC  
— HDLC bus (implements an HDLC-based local area network (LAN))  
— Asynchronous HDLC to support PPP (point-to-point protocol)  
— AppleTalk  
— Universal asynchronous receiver transmitter (UART)  
— Synchronous UART  
— Serial infrared (IrDA)  
— Binary synchronous communication (BISYNC)  
— Totally transparent (bit streams)  
— Totally transparent (frame based with optional cyclic redundancy check (CRC))  
Two SMCs (serial management channels) (The MPC857DSL has one SMC, for UART)  
— UART  
•
— Transparent  
— General circuit interface (GCI) controller  
— Can be connected to the time-division multiplexed (TDM) channel  
One serial peripheral interface (SPI)  
•
•
•
— Supports master and slave modes  
— Supports multiple-master operation on the same bus  
2
One inter-integrated circuit (I C) port  
— Supports master and slave modes  
— Multiple-master environment support  
Time-slot assigner (TSA) (The MPC857DSL does not have the TSA)  
— Allows SCC and SMCs to run in multiplexed and/or non-multiplexed operation  
— Supports T1, CEPT, PCM highway, user defined  
— 1- or 8-bit resolution  
— Allows independent transmit and receive routing, frame synchronization, clocking  
— Allows dynamic changes  
— Can be internally connected to three serial channels (one SCC and two SMCs)  
Parallel interface port (PIP)  
•
•
— Centronics interface support  
— Supports fast connection between compatible ports on MPC857T or MC68360  
PCMCIA interface  
— Master (socket) interface, release 2.1 compliant  
— Supports two independent PCMCIA sockets  
4
MPC857THardwareSpecifications  
MOTOROLA  
Features  
— 8 memory or I/O windows supported  
Low power support  
•
— Full on—All units fully powered  
— Doze—Core functional units disabled except time base decrementer, PLL, memory controller,  
RTC, and CPM in low-power standby  
— Sleep—All units disabled except RTC, PIT, time base, and decrementer with PLL active for fast  
wake up  
— Deep sleep—All units disabled including PLL except RTC, PIT, time base, and decrementer.  
— Power down mode— All units powered down except PLL, RTC, PIT, time base and  
decrementer  
•
Debug interface  
— Eight comparators: four operate on instruction address, two operate on data address, and two  
operate on data  
— Supports conditions: = ≠ < >  
— Each watchpoint can generate a break point internally  
3.3 V operation with 5-V TTL compatibility except EXTAL and EXTCLK  
357-pin ball grid array (BGA) package  
•
•
The MPC857T is comprised of three modules that each use the 32-bit internal bus—the MPC8xx core, the  
system integration unit (SIU), and the communication processor module (CPM). The MPC857T block  
diagram is shown in Figure 1.  
MOTOROLA  
MPC857THardwareSpecifications  
5
Maximum Tolerated Ratings  
4-Kbyte  
Instruction Cache  
Instruction  
Bus  
System Interface Unit (SIU)  
Unified  
Bus  
Memory Controller  
Instruction MMU  
32-Entry ITLB  
Embedded  
MPC8xx  
Internal BusExternal Bus  
Interface  
Unit  
Interface  
Unit  
Processor  
4-Kbyte  
Data Cache  
Load/Store  
Bus  
Core  
System Functions  
Real-Time Clock  
Data MMU  
32-Entry DTLB  
PCMCIA/ATA Interface  
Fast Ethernet  
Controller  
DMAs  
FIFOs  
4
Interrupt  
8-Kbyte  
10 Virtual  
Serial  
Parallel I/O  
Timers ControllersDual-Port RAM  
10/100  
Base-T  
Media  
Access  
Control  
and  
2
Independent  
DMA  
Channels  
4 Baud Rate  
Generators  
32-Bit RISC Controller  
and Program  
ROM  
Parallel Interface  
Port and UTOPIA  
Timers  
MII  
SCC1  
SMC1 SMC2*  
SPI  
I2C  
Time Slot Assigner  
Serial Interface  
Figure 1. MPC857T Block Diagram  
NOTE  
The MPC857DSL does not contain SMC2 nor the Time Slot Assigner, and  
provides eight SDMA channels.  
Part III Maximum Tolerated Ratings  
This section provides the maximum tolerated voltage and temperature ranges for the MPC857T. Table 2  
provides the maximum ratings.  
6
MPC857THardwareSpecifications  
MOTOROLA  
Thermal Characteristics  
Table 2. Maximum Tolerated Ratings  
(GND = 0V)  
Rating  
Symbol  
VDDH  
Value  
Unit  
1
Supply voltage  
-0.3 to 4.0  
-0.3 to 4.0  
-0.3 to 4.0  
-0.3 to 4.0  
V
V
VDDL  
KAPWR  
VDDSYN  
V
V
2
Input voltage  
V
GND-0.3 to VDDH  
V
in  
3
Temperature (standard)  
T
0
˚C  
˚C  
˚C  
˚C  
˚C  
A(min)  
T
95  
j(max)  
3
Temperature (extended)  
T
-40  
A(min)  
T
105  
j(max)  
stg  
Storage temperature range  
T
-55 to +150  
1
The power supply of the device must start its ramp from 0.0 V.  
2
Functional operating conditions are provided with the DC electrical specifications in Table 5.  
Absolute maximum ratings are stress ratings only; functional operation at the maxima is not  
guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage  
to the device.  
Caution: All inputs cannot be more than 2.5 V greater than the supply voltage. This restriction  
applies to power-up and normal operation (that is, if the MPC857T is unpowered, voltage greater  
than 2.5 V must not be applied to its inputs).  
3
Minimum temperatures are guaranteed as ambient temperature, T . Maximum temperatures are  
A
guaranteed as junction temperature, T .  
j
This device contains circuitry protecting against damage due to high-static voltage or electrical fields;  
however, it is advised that normal precautions be taken to avoid application of any voltages higher than  
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused  
inputs are tied to an appropriate logic voltage level (for example, either GND or V ).  
CC  
Part IV Thermal Characteristics  
Table 3 shows the thermal characteristics for the MPC857T.  
MOTOROLA  
MPC857THardwareSpecifications  
7
Power Dissipation  
Table 3. MPC857T Thermal Resistance Data  
Rating  
Environment  
Single layer board (1s)  
Symbol  
Value  
Unit  
1
2
Junction to ambient  
Natural Convection  
R
40  
25  
32  
21  
15  
7
°C/W  
θJA  
3
Four layer board (2s2p)  
Single layer board (1s)  
Four layer board (2s2p)  
R
θJMA  
3
Air flow (200 ft/min)  
R
R
θJMA  
3
θJMA  
4
Junction to board  
R
θJB  
θJC  
5
Junction to case  
R
6
Junction to package top Natural Convection  
Air flow (200 ft/min)  
Ψ
2
JT  
JT  
Ψ
3
1
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site  
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board,  
and board thermal resistance.  
2
3
4
Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.  
Per JEDEC JESD51-6 with the board horizontal.  
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature  
is measured on the top surface of the board near the package.  
5
Indicates the average thermal resistance between the die and the case top surface as measured by the cold  
plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case  
temperature. For exposed pad packages where the pad would be expected to be soldered, junction to case  
thermal resistance is a simulated value from the junction to the exposed pad without contact resistance.  
6
Thermal characterization parameter indicating the temperature difference between package top and the  
junction temperature per JEDEC JESD51-2.  
Part V Power Dissipation  
Table 4 provides power dissipation information. The modes are 1:1, where CPU and bus speeds are equal,  
and 2:1 mode, where CPU frequency is twice bus speed.  
Table 4. Power Dissipation (P )  
D
1
2
Die Revision  
Frequency  
Typical  
Maximum  
Unit  
0
50 MHz  
66 MHz  
66 MHz  
80 MHz  
656  
TBD  
722  
851  
735  
TBD  
762  
909  
mW  
mW  
mW  
mW  
(1:1 Mode)  
0
(2:1 Mode)  
1
2
Typical power dissipation is measured at 3.3V.  
Maximum power dissipation is measured at 3.5V.  
NOTE  
Values in Table 4 represent VDDL based power dissipation and do not  
include I/O power dissipation over VDDH. I/O power dissipation varies  
widely by application due to buffer current, depending on external  
circuitry.  
8
MPC857THardwareSpecifications  
MOTOROLA  
DC Characteristics  
Part VI DC Characteristics  
Table 5 provides the DC electrical characteristics for the MPC857T.  
Table 5. DC Electrical Specifications  
Uni  
t
Characteristic  
Symbol  
Min  
Max  
3.6  
Operating voltage at 40 MHz or less  
VDDH, VDDL, VDDSYN  
3.0  
V
V
V
KAPWR (power-down mode) 2.0  
3.6  
KAPWR (all other operating VDDH -  
VDDH  
modes)  
0.4  
Operating voltage greater than 40 MHz  
VDDH, VDDL, KAPWR,  
VDDSYN  
3.135  
3.465  
V
KAPWR (power-down mode) 2.0  
3.6  
V
V
KAPWR (all other operating VDDH -  
VDDH  
modes)  
0.4  
Input High Voltage (all inputs except EXTAL and EXTCLK) VIH  
2.0  
5.5  
0.8  
V
V
Input Low Voltage  
VIL  
GND  
EXTAL, EXTCLK Input High Voltage  
VIHC  
0.7*(VCC) VCC+0.3 V  
Input Leakage Current, Vin = 5.5V (Except TMS, TRST,  
DSCK and DSDI pins)  
I
I
I
—
—
—
100  
µA  
µA  
µA  
in  
In  
In  
Input Leakage Current, Vin = 3.6V (Except TMS, TRST,  
DSCK, and DSDI)  
10  
Input Leakage Current, Vin = 0V (Except TMS, TRST,  
DSCK and DSDI pins)  
10  
1
Input Capacitance  
C
—
20  
—
pF  
V
in  
Output High Voltage, IOH = -2.0 mA, VDDH = 3.0V  
Except XTAL, XFC, and Open drain pins  
VOH  
2.4  
Output Low Voltage  
VOL  
—
0.5  
V
IOL = 2.0 mA (CLKOUT)  
2
IOL = 3.2 mA  
IOL = 5.3 mA  
3
IOL = 7.0 mA (TXD1/PA14, PA12)  
IOL = 8.9 mA (TS, TA, TEA, BI, BB, HRESET, SRESET)  
1
Input capacitance is periodically sampled.  
2
A(0:31), TSIZ0/REG, TSIZ1, D(0:31), DP(0:3)/IRQ(3:6), RD/WR, BURST, RSV/IRQ2, IP_B(0:1)/IWP(0:1)/VFLS(0:1),  
IP_B2/IOIS16_B/AT2, IP_B3/IWP2/VF2, IP_B4/LWP0/VF0, IP_B5/LWP1/VF1, IP_B6/DSDI/AT0, IP_B7/PTR/AT3,  
RXD1 /PA15, PA13, PA11, PA10, L1TXDA/PA9, L1RXDA/PA8, TIN1/L1RCLKA/BRGO1/CLK1/PA7,  
BRGCLK1/TOUT1/CLK2/PA6, TIN2/L1TCLKA/BRGO2/CLK3/PA5, TOUT2/CLK4/PA4, TIN3/BRGO3/CLK5/PA3,  
BRGCLK2/TOUT3/CLK6/PA2, TIN4/BRGO4/CLK7/PA1, TOUT4/CLK8/PA0, REJCT1/SPISEL/PB31, SPICLK/PB30,  
SPIMOSI/PB29, BRGO4/SPIMISO/PB28, BRGO1/I2CSDA/PB27, BRGO2/I2CSCL/PB26, SMTXD1/PB25,  
SMRXD1/PB24, SMSYN1/SDACK1/PB23, SMSYN2/SDACK2/PB22, SMTXD2/PB21, SMRXD2/L1CLKOA/PB20,  
L1ST1/RTS1/PB19, L1ST2/PB18, L1ST3/PB17, L1ST4/L1RQA/PB16, BRGO3/PB15, RSTRT1/PB14,  
L1ST1/RTS1/DREQ0/PC15, L1ST2/DREQ1/PC14, L1ST3/PC13, L1ST4/L1RQA/PC12, CTS1/PC11,  
TGATE1/CD1/PC10, PC9, TGATE2/PC8, SDACK2/PC7, PC6, SDACK1/L1TSYNCA/PC5, L1RSYNCA/PC4, PD15,  
PD14, PD13, PD12, PD11, PD10, PD9, PD8, PD5, PD6, PD7, PD4, PD3, MII_MDC, MII_TX_ER, MII_EN, MII_MDIO,  
MII_TXD[0:3]  
MOTOROLA  
MPC857THardwareSpecifications  
9
Thermal Calculation and MeasurementEstimation with Junction-to-Ambient Thermal Resistance  
3
BDIP/GPL_B(5), BR, BG, FRZ/IRQ6, CS(0:5), CS(6)/CE(1)_B, CS(7)/CE(2)_B, WE0/BS_B0/IORD,  
WE1/BS_B1/IOWR, WE2/BS_B2/PCOE, WE3/BS_B3/PCWE, BS_A(0:3), GPL_A0/GPL_B0, OE/GPL_A1/GPL_B1,  
GPL_A(2:3)/GPL_B(2:3)/CS(2:3), UPWAITA/GPL_A4, UPWAITB/GPL_B4, GPL_A5, ALE_A, CE1_A, CE2_A,  
ALE_B/DSCK/AT1, OP(0:1), OP2/MODCK1/STS, OP3/MODCK2/DSDO, BADDR(28:30)  
Part VII Thermal Calculation and Measurement  
For the following discussions, P = (VDD x IDD) + PI/O, where PI/O is the power dissipation of the I/O  
D
drivers.  
7.1Estimation with Junction-to-Ambient Thermal  
Resistance  
An estimation of the chip junction temperature, TJ, in °C can be obtained from the equation:  
T = T +( R  
x P )  
D
J
A
θJA  
where:  
T = ambient temperature ºC  
A
R
= package junction-to-ambient thermal resistance (ºC/W)  
θJA  
P = power dissipation in package  
D
The junction-to-ambient thermal resistance is an industry standard value which provides a quick and easy  
estimation of thermal performance. However, the answer is only an estimate; test cases have demonstrated  
that errors of a factor of two (in the quantity T -T ) are possible.  
J
A
7.2 Estimation with Junction-to-Case Thermal  
Resistance  
Historically, the thermal resistance has frequently been expressed as the sum of a junction-to-case thermal  
resistance and a case-to-ambient thermal resistance:  
R
= R  
+ R  
θJA  
θJC θCA  
where:  
R
= junction-to-ambient thermal resistance (ºC/W)  
= junction-to-case thermal resistance (ºC/W)  
= case-to-ambient thermal resistance (ºC/W)  
θJA  
θJC  
θCA  
R
R
R
is device related and cannot be influenced by the user. The user adjusts the thermal environment to  
θJC  
affect the case-to-ambient thermal resistance, R  
. For instance, the user can change the air flow around  
θCA  
the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the  
thermal dissipation on the printed circuit board surrounding the device. This thermal model is most useful  
for ceramic packages with heat sinks where some 90% of the heat flows through the case and the heat sink  
to the ambient environment. For most packages, a better model is required.  
10  
MPC857THardwareSpecifications  
MOTOROLA  
Thermal Calculation and MeasurementEstimation with Junction-to-Board Thermal Resistance  
7.3 Estimation with Junction-to-Board Thermal  
Resistance  
A simple package thermal model which has demonstrated reasonable accuracy (about 20%) is a two resistor  
model consisting of a junction-to-board and a junction-to-case thermal resistance. The junction-to-case  
covers the situation where a heat sink is used or where a substantial amount of heat is dissipated from the  
top of the package. The junction-to-board thermal resistance describes the thermal performance when most  
of the heat is conducted to the printed circuit board. It has been observed that the thermal performance of  
most plastic packages and especially PBGA packages is strongly dependent on the board temperature; see  
Figure 2.  
100  
9 0  
8 0  
7 0  
6 0  
5 0  
4 0  
3 0  
2 0  
1 0  
0
0
2 0  
4 0  
6 0  
8 0  
Board Temperture Rise Above Ambient Divided by Package  
Power  
Figure 2. Effect of Board Temperature Rise on Thermal Behavior  
If the board temperature is known, an estimate of the junction temperature in the environment can be made  
using the following equation:  
T = T +( R  
x P )  
D
J
B
θJB  
where:  
R
= junction-to-board thermal resistance (ºC/W)  
θJB  
T = board temperature ºC  
B
P = power dissipation in package  
D
If the board temperature is known and the heat loss from the package case to the air can be ignored,  
acceptable predictions of junction temperature can be made. For this method to work, the board and board  
mounting must be similar to the test board used to determine the junction-to-board thermal resistance,  
namely a 2s2p (board with a power and a ground plane) and vias attaching the thermal balls to the ground  
plane.  
MOTOROLA  
MPC857THardwareSpecifications  
11  
Layout PracticesEstimation Using Simulation  
7.4 Estimation Using Simulation  
When the board temperature is not known, a thermal simulation of the application is needed. The simple  
two resistor model can be used with the thermal simulation of the application [2], or a more accurate and  
complex model of the package can be used in the thermal simulation.  
7.5 Experimental Determination  
To determine the junction temperature of the device in the application after prototypes are available, the  
thermal characterization parameter (Ψ ) can be used to determine the junction temperature with a  
JT  
measurement of the temperature at the top center of the package case using the following equation:  
T = T +( Ψ x P )  
J
T
JT  
D
where:  
Ψ
= thermal characterization parameter  
JT  
T = thermocouple temperature on top of package  
T
P = power dissipation in package  
D
The thermal characterization parameter is measured per JESD51-2 specification published by JEDEC using  
a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be  
positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over  
the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire  
is placed flat against the package case to avoid measurement errors caused by cooling effects of the  
thermocouple wire.  
7.6 References  
Semiconductor Equipment and Materials International  
(415) 964-5111  
805 East Middlefield Rd  
Mountain View, CA 94043  
MIL-SPEC and EIA/JESD (JEDEC) specifications  
(Available from Global Engineering Documents)  
800-854-7179 or  
303-397-7956  
JEDEC Specifications  
http://www.jedec.org  
1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive  
Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47-54.  
2. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its  
Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212-220.  
Part VIII Layout Practices  
Each VCC pin on the MPC857T should be provided with a low-impedance path to the board’s supply. Each  
GND pin should likewise be provided with a low-impedance path to ground. The power supply pins drive  
distinct groups of logic on chip. The VCC power supply should be bypassed to ground using at least four 0.1  
µF by-pass capacitors located as close as possible to the four sides of the package. The capacitor leads and  
associated printed circuit traces connecting to chip VCC and GND should be kept to less than half an inch  
per capacitor lead.A four-layer board is recommended, employing two inner layers asVCC and GND planes.  
12  
MPC857THardwareSpecifications  
MOTOROLA  
Bus Signal TimingReferences  
All output pins on the MPC857T have fast rise and fall times. Printed circuit (PC) trace interconnection  
length should be minimized in order to minimize undershoot and reflections caused by these fast output  
switching times. This recommendation particularly applies to the address and data busses. Maximum PC  
trace lengths of six inches are recommended. Capacitance calculations should consider all device loads as  
well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing becomes  
especially critical in systems with higher capacitive loads because these loads create higher transient  
currents in the VCC and GND circuits. Pull up all unused inputs or signals that will be inputs during reset.  
Special care should be taken to minimize the noise levels on the PLL supply pins.  
Part IX Bus Signal Timing  
Table 6 provides the bus operation timing for the MPC857T at 33 MHz, 40 Mhz, 50 MHz and 66 Mhz.  
The maximum bus speed supported by the MPC857T is 66 MHz. Higher-speed parts must be operated in  
half-speed bus mode (for example, an MPC857T used at 80MHz must be configured for a 40 MHz bus).  
The timing for the MPC857T bus shown assumes a 50-pF load for maximum delays and a 0-pF load for  
minimum delays.  
Table 6. Bus Operation Timings  
33 MHz  
Min Max  
30.30 30.30 25.00 30.30 20.00 30.30 15.15 30.30 ns  
40 MHz  
50 MHz  
66 MHz  
Num  
Characteristic  
Unit  
Min Max  
Min Max  
Min Max  
B1 CLKOUT period  
B1a EXTCLK to CLKOUT phase skew  
(EXTCLK > 15 MHz and MF <= 2)  
-0.90  
-2.30  
-0.60  
0.90  
2.30  
0.60  
-0.90 0.90 -0.90 0.90 -0.90 0.90  
-2.30 2.30 -2.30 2.30 -2.30 2.30  
-0.60 0.60 -0.60 0.60 -0.60 0.60  
-2.00 2.00 -2.00 2.00 -2.00 2.00  
ns  
ns  
ns  
B1b EXTCLK to CLKOUT phase skew  
(EXTCLK > 10 MHz and MF < 10)  
B1c CLKOUT phase jitter (EXTCLK > 15  
1
MHz and MF <= 2)  
1
B1d CLKOUT phase jitter  
-2.00  
—
2.00  
0.50  
2.00  
ns  
%
%
1
B1e CLKOUT frequency jitter (MF < 10)  
—
—
0.50  
2.00  
—
—
0.50  
2.00  
—
—
0.50  
2.00  
B1f CLKOUT frequency jitter (10 < MF <  
—
1
500)  
1
B1g CLKOUT frequency jitter (MF > 500)  
—
—
3.00  
0.50  
—
—
—
3.00  
0.50  
—
—
—
3.00  
0.50  
—
—
—
3.00  
0.50  
—
%
%
2
B1h Frequency jitter on EXTCLK  
B2 CLKOUT pulse width low  
B3 CLKOUT width high  
12.12  
12.12  
—
10.00  
10.00  
—
8.00  
8.00  
—
6.06  
6.06  
—
ns  
ns  
ns  
ns  
ns  
—
—
—
—
3
B4 CLKOUT rise time  
4.00  
4.00  
—
4.00  
4.00  
—
4.00  
4.00  
—
4.00  
4.00  
—
33  
3
B5  
CLKOUT fall time  
—
—
—
—
B7 CLKOUT to A(0:31), BADDR(28:30),  
RD/WR, BURST, D(0:31), DP(0:3)  
invalid  
7.58  
6.25  
5.00  
3.80  
B7a CLKOUT to TSIZ(0:1), REG, RSV,  
AT(0:3), BDIP, PTR invalid  
7.58  
—
6.25  
—
5.00  
—
3.80  
—
ns  
MOTOROLA  
MPC857THardwareSpecifications  
13  
Bus Signal TimingReferences  
Table 6. Bus Operation Timings (continued)  
33 MHz  
40 MHz  
50 MHz  
66 MHz  
Num  
Characteristic  
Unit  
Min  
7.58  
Max  
Min  
6.25  
Max  
Min  
5.00  
Max  
Min  
3.80  
Max  
B7b CLKOUT to BR, BG, FRZ, VFLS(0:1),  
VF(0:2) IWP(0:2), LWP(0:1), STS  
—
—
—
—
ns  
4
invalid  
B8 CLKOUT to A(0:31), BADDR(28:30)  
RD/WR, BURST, D(0:31), DP(0:3) valid  
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04 ns  
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04 ns  
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04 ns  
B8a CLKOUT to TSIZ(0:1), REG, RSV,  
AT(0:3) BDIP, PTR valid  
B8b CLKOUT to BR, BG, VFLS(0:1),  
VF(0:2), IWP(0:2), FRZ, LWP(0:1),  
4
STS Valid  
B9 CLKOUT to A(0:31), BADDR(28:30),  
RD/WR, BURST, D(0:31), DP(0:3),  
TSIZ(0:1), REG, RSV, AT(0:3), PTR  
High-Z  
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04 ns  
B11 CLKOUT to TS, BB assertion  
7.58 13.58 6.25 12.25 5.00 11.00 3.80 11.29 ns  
B11 CLKOUT to TA, BI assertion (when  
2.50  
9.25  
2.50  
9.25  
2.50  
9.25  
2.50  
9.75  
ns  
a
driven by the memory controller or  
PCMCIA interface)  
B12 CLKOUT to TS, BB negation  
7.58 14.33 6.25 13.00 5.00 11.75 3.80  
2.50 11.00 2.50 11.00 2.50 11.00 2.50  
8.54  
9.00  
ns  
ns  
B12 CLKOUT to TA, BI negation (when  
a
driven by the memory controller or  
PCMCIA interface)  
B13 CLKOUT to TS, BB High-Z  
7.58 21.58 6.25 20.25 5.00 19.00 3.80 14.04 ns  
B13 CLKOUT to TA, BI High-Z (when driven 2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 ns  
a
by the memory controller or PCMCIA  
interface)  
B14 CLKOUT to TEA assertion  
B15 CLKOUT to TEA High-Z  
2.50 10.00 2.50 10.00 2.50 10.00 2.50  
9.00  
ns  
2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 ns  
B16 TA, BI valid to CLKOUT (setup time)  
9.75  
—
—
9.75  
—
—
9.75  
—
—
6.00  
4.50  
—
—
ns  
ns  
B16 TEA, KR, RETRY, CR valid to CLKOUT 10.00  
(setup time)  
10.00  
10.00  
a
B16 BB, BG, BR, valid to CLKOUT (setup  
8.50  
—
—
—
—
8.50  
1.00  
2.00  
6.00  
—
—
—
—
8.50  
1.00  
2.00  
6.00  
—
—
—
—
4.00  
2.00  
2.00  
6.00  
—
—
—
—
ns  
ns  
ns  
ns  
5
b
time)  
B17 CLKOUT to TA, TEA, BI, BB, BG, BR  
valid (hold time).  
1.00  
B17 CLKOUT to KR, RETRY, CR valid (hold 2.00  
time)  
a
B18 D(0:31), DP(0:3) valid to CLKOUT  
6.00  
6
rising edge (setup time)  
14  
MPC857THardwareSpecifications  
MOTOROLA  
Bus Signal TimingReferences  
Table 6. Bus Operation Timings (continued)  
33 MHz  
40 MHz  
50 MHz  
66 MHz  
Num  
Characteristic  
Unit  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
B19 CLKOUT rising edge to D(0:31),  
1.00  
4.00  
2.00  
—
1.00  
4.00  
2.00  
—
1.00  
4.00  
2.00  
—
2.00  
4.00  
2.00  
—
ns  
ns  
ns  
6
DP(0:3) valid (hold time)  
B20 D(0:31), DP(0:3) valid to CLKOUT  
—
—
—
—
—
—
—
—
7
falling edge (setup time)  
B21 CLKOUT falling edge to D(0:31),  
7
DP(0:3) valid (hold Time)  
B22 CLKOUT rising edge to CS asserted  
GPCM ACS = 00  
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04 ns  
B22 CLKOUT falling edge to CS asserted  
—
8.00  
—
8.00  
—
8.00  
—
8.00  
ns  
a
GPCM ACS = 10, TRLX = 0  
B22 CLKOUT falling edge to CS asserted  
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns  
10.86 17.99 8.88 16.00 7.00 14.13 5.18 12.31 ns  
b
GPCM ACS = 11, TRLX = 0, EBDF = 0  
B22 CLKOUT falling edge to CS asserted  
c
GPCM ACS = 11, TRLX = 0, EBDF = 1  
B23 CLKOUT rising edge to CS negated  
GPCM read access, GPCM write  
access ACS = 00, TRLX = 0 & CSNT =  
0
2.00  
8.00  
2.00  
8.00  
2.00  
8.00  
2.00  
8.00  
ns  
B24 A(0:31) and BADDR(28:30) to CS  
asserted GPCM ACS = 10, TRLX = 0.  
5.58  
13.15  
—
—
—
4.25  
—
—
3.00  
8.00  
—
—
1.79  
5.58  
—
—
ns  
ns  
ns  
B24 A(0:31) and BADDR(28:30) to CS  
10.50  
a
asserted GPCM ACS = 11 TRLX = 0  
B25 CLKOUT rising edge to OE, WE(0:3)  
asserted  
9.00  
9.00  
9.00  
9.00  
B26 CLKOUT rising edge to OE negated  
2.00  
9.00  
—
2.00  
9.00  
—
2.00  
9.00  
—
2.00  
9.00  
—
ns  
ns  
B27 A(0:31) and BADDR(28:30) to CS  
asserted GPCM ACS = 10, TRLX = 1  
35.88  
29.25  
23.00  
16.94  
B27 A(0:31) and BADDR(28:30) to CS  
43.45  
—
—
35.50  
—
—
28.00  
—
—
20.73  
—
—
ns  
ns  
a
asserted GPCM ACS = 11, TRLX = 1  
B28 CLKOUT rising edge to WE(0:3)  
negated GPCM write access CSNT = 0  
9.00  
9.00  
9.00  
9.00  
B28 CLKOUT falling edge to WE(0:3)  
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns  
a
negated GPCM write accessTRLX = 0,  
CSNT = 1, EBDF = 0  
B28 CLKOUT falling edge to CS negated  
—
14.33  
—
13.00  
—
11.75  
—
10.54 ns  
b
GPCM write accessTRLX = 0, CSNT =  
1 ACS = 10 or ACS = 11, EBDF = 0  
B28 CLKOUT falling edge to WE(0:3)  
10.86 17.99 8.88 16.00 7.00 14.13 5.18 12.31 ns  
c
negated GPCM write accessTRLX = 0,  
CSNT = 1 write access TRLX = 0,  
CSNT = 1, EBDF = 1  
MOTOROLA  
MPC857THardwareSpecifications  
15  
Bus Signal TimingReferences  
Table 6. Bus Operation Timings (continued)  
33 MHz  
40 MHz  
50 MHz  
66 MHz  
Num  
Characteristic  
Unit  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
B28 CLKOUT falling edge to CS negated  
—
17.99  
—
16.00  
—
14.13  
—
12.31 ns  
d
GPCM write accessTRLX = 0, CSNT =  
1, ACS = 10, or ACS = 11, EBDF = 1  
B29 WE(0:3) negated to D(0:31), DP(0:3)  
High-Z GPCM write access, CSNT = 0,  
EBDF = 0  
5.58  
13.15  
—
—
—
—
—
—
—
—
—
—
—
—
4.25  
10.5  
4.25  
10.5  
35.5  
35.5  
6.88  
6.88  
31.38  
31.38  
4.25  
10.50  
—
—
—
—
—
—
—
—
—
—
—
—
3.00  
8.00  
3.00  
8.00  
28.00  
28.00  
5.00  
5.00  
24.50  
24.50  
3.00  
8.00  
—
—
—
—
—
—
—
—
—
—
—
—
1.79  
5.58  
—
—
—
—
—
—
—
—
—
—
—
—
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
B29 WE(0:3) negated to D(0:31), DP(0:3)  
a
High-Z GPCM write access, TRLX = 0,  
CSNT = 1, EBDF = 0  
B29 CS negated to D(0:31), DP(0:3), High Z 5.58  
1.79  
b
GPCM write access, ACS = 00,TRLX =  
0 & CSNT = 0  
B29 CS negated to D(0:31), DP(0:3) High-Z 13.15  
5.58  
c
GPCM write access, TRLX = 0, CSNT  
= 1, ACS = 10, or ACS = 11 EBDF = 0  
B29 WE(0:3) negated to D(0:31), DP(0:3)  
43.45  
20.73  
29.73  
3.18  
d
High-Z GPCM write access, TRLX = 1,  
CSNT = 1, EBDF = 0  
B29 CS negated to D(0:31), DP(0:3) High-Z 43.45  
e
GPCM write access, TRLX = 1, CSNT  
= 1, ACS = 10, or ACS = 11 EBDF = 0  
B29f WE(0:3) negated to D(0:31), DP(0:3)  
High Z GPCM write access, TRLX = 0,  
CSNT = 1, EBDF = 1  
8.86  
B29 CS negated to D(0:31), DP(0:3) High-Z 8.86  
3.18  
g
GPCM write access, TRLX = 0, CSNT  
= 1 ACS = 10 or ACS = 11, EBDF = 1  
B29 WE(0:3) negated to D(0:31), DP(0:3)  
38.67  
17.83  
17.83  
1.79  
h
High Z GPCM write access, TRLX = 1,  
CSNT = 1, EBDF = 1  
B29i CS negated to D(0:31), DP(0:3) High-Z 38.67  
GPCM write access, TRLX = 1, CSNT  
= 1, ACS = 10 or ACS = 11, EBDF = 1  
B30 CS, WE(0:3) negated to A(0:31),  
BADDR(28:30) Invalid GPCM write  
5.58  
8
access  
B30 WE(0:3) negated to A(0:31),  
13.15  
5.58  
a
BADDR(28:30) Invalid GPCM, write  
access, TRLX = 0, CSNT = 1, CS  
negated to A(0:31) invalid GPCM write  
access TRLX = 0, CSNT =1 ACS = 10,  
or ACS == 11, EBDF = 0  
16  
MPC857THardwareSpecifications  
MOTOROLA  
Bus Signal TimingReferences  
Table 6. Bus Operation Timings (continued)  
33 MHz  
40 MHz  
50 MHz  
66 MHz  
Num  
Characteristic  
Unit  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
B30 WE(0:3) negated to A(0:31) Invalid  
43.45  
—
35.50  
—
28.00  
—
20.73  
—
ns  
b
GPCM BADDR(28:30) invalid GPCM  
write access, TRLX = 1, CSNT = 1. CS  
negated to A(0:31) Invalid GPCM write  
accessTRLX = 1, CSNT = 1, ACS = 10,  
or ACS == 11 EBDF = 0  
B30 WE(0:3) negated to A(0:31),  
8.36  
—
—
6.38  
—
—
4.50  
—
—
2.68  
—
—
ns  
ns  
ns  
c
BADDR(28:30) invalid GPCM write  
access, TRLX = 0, CSNT = 1. CS  
negated to A(0:31) invalid GPCM write  
access,TRLX = 0, CSNT = 1 ACS = 10,  
ACS == 11, EBDF = 1  
B30 WE(0:3) negated to A(0:31),  
38.67  
1.50  
31.38  
1.50  
24.50  
1.50  
17.83  
1.50  
d
BADDR(28:30) invalid GPCM write  
access TRLX = 1, CSNT =1, CS  
negated to A(0:31) invalid GPCM write  
access TRLX = 1, CSNT = 1, ACS = 10  
or 11, EBDF = 1  
B31 CLKOUT falling edge to CS valid - as  
requested by control bit CST4 in the  
corresponding word in the UPM  
6.00  
6.00  
6.00  
6.00  
B31 CLKOUT falling edge to CS valid - as  
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns  
a
requested by control bit CST1 in the  
corresponding word in the UPM  
B31 CLKOUT rising edge to CS valid - as  
1.50  
8.00  
1.50  
8.00  
1.50  
8.00  
1.50  
8.00  
ns  
b
requested by control bit CST2 in the  
corresponding word in the UPM  
B31 CLKOUT rising edge to CS valid- as  
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04 ns  
13.26 17.99 11.28 16.00 9.40 14.13 7.58 12.31 ns  
c
requested by control bit CST3 in the  
corresponding word in the UPM  
B31 CLKOUT falling edge to CS valid, as  
d
requested by control bit CST1 in the  
corresponding word in the UPM EBDF  
= 1  
B32 CLKOUT falling edge to BS valid- as  
requested by control bit BST4 in the  
corresponding word in the UPM  
1.50  
6.00  
1.50  
6.00  
1.50  
6.00  
1.50  
6.00  
ns  
B32 CLKOUT falling edge to BS valid - as  
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns  
a
requested by control bit BST1 in the  
corresponding word in the UPM, EBDF  
= 0  
B32 CLKOUT rising edge to BS valid - as  
1.50  
8.00  
1.50  
8.00  
1.50  
8.00  
1.50  
8.00  
ns  
b
requested by control bit BST2 in the  
corresponding word in the UPM  
MOTOROLA  
MPC857THardwareSpecifications  
17  
Bus Signal TimingReferences  
Table 6. Bus Operation Timings (continued)  
33 MHz  
Min Max  
40 MHz  
Min Max  
50 MHz  
Min Max  
66 MHz  
Min Max  
Num  
Characteristic  
Unit  
B32 CLKOUT rising edge to BS valid - as  
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns  
c
requested by control bit BST3 in the  
corresponding word in the UPM  
B32 CLKOUT falling edge to BS valid- as  
13.26 17.99 11.28 16.00 9.40 14.13 7.58 12.31 ns  
d
requested by control bit BST1 in the  
corresponding word in the UPM, EBDF  
= 1  
B33 CLKOUT falling edge to GPL valid - as 1.50  
requested by control bit GxT4 in the  
6.00  
1.50  
6.00  
1.50  
6.00  
1.50  
6.00  
ns  
corresponding word in the UPM  
B33 CLKOUT rising edge to GPL Valid - as 7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns  
a
requested by control bit GxT3 in the  
corresponding word in the UPM  
B34 A(0:31), BADDR(28:30), and D(0:31)  
to CS valid - as requested by control bit  
CST4 in the corresponding word in the  
UPM  
5.58  
13.15  
20.73  
—
—
4.25  
—
—
3.00  
8.00  
—
—
1.79  
5.58  
—
—
ns  
ns  
B34 A(0:31), BADDR(28:30), and D(0:31)  
10.50  
a
to CS valid - as requested by control bit  
CST1 in the corresponding word in the  
UPM  
B34 A(0:31), BADDR(28:30), and D(0:31)  
—
—
—
—
16.75  
4.25  
—
—
—
—
13.00  
3.00  
—
—
—
—
9.36  
1.79  
5.58  
9.36  
—
—
—
—
ns  
ns  
ns  
ns  
b
to CS valid - as requested by CST2 in  
the corresponding word in UPM  
B35 A(0:31), BADDR(28:30) to CS valid - as 5.58  
requested by control bit BST4 in the  
corresponding word in the UPM  
B35 A(0:31), BADDR(28:30), and D(0:31)  
13.15  
20.73  
10.50  
16.75  
8.00  
a
to BS valid - As Requested by BST1 in  
the corresponding word in the UPM  
B35 A(0:31), BADDR(28:30), and D(0:31)  
13.00  
b
to BS valid - as requested by control bit  
BST2 in the corresponding word in the  
UPM  
B36 A(0:31), BADDR(28:30), and D(0:31)  
to GPL valid as requested by control bit  
GxT4 in the corresponding word in the  
UPM  
5.58  
—
4.25  
—
3.00  
—
1.79  
—
ns  
B37 UPWAIT valid to CLKOUT falling edge 6.00  
—
—
—
6.00  
1.00  
7.00  
—
—
—
6.00  
1.00  
7.00  
—
—
—
6.00  
1.00  
7.00  
—
—
—
ns  
ns  
ns  
9
B38 CLKOUT falling edge to UPWAIT valid 1.00  
9
10  
B39 AS valid to CLKOUT rising edge  
7.00  
18  
MPC857THardwareSpecifications  
MOTOROLA  
Bus Signal TimingReferences  
Table 6. Bus Operation Timings (continued)  
33 MHz  
40 MHz  
50 MHz  
66 MHz  
Num  
Characteristic  
Unit  
Min  
7.00  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
B40 A(0:31), TSIZ(0:1), RD/WR, BURST,  
valid to CLKOUT rising edge  
—
7.00  
7.00  
2.00  
—
—
7.00  
7.00  
2.00  
—
—
7.00  
7.00  
2.00  
—
—
ns  
ns  
ns  
ns  
B41 TS valid to CLKOUT rising edge (setup 7.00  
time)  
—
—
—
—
—
—
—
—
B42 CLKOUT rising edge to TS valid (hold  
time)  
2.00  
B43 AS negation to memory controller  
signals negation  
—
TBD  
TBD  
TBD  
TBD  
1
2
Phase and frequency jitter performance results are only valid if the input jitter is less than the prescribed value.  
If the rate of change of the frequency of EXTAL is slow (I.e. it does not jump between the minimum and maximum  
values in one cycle) or the frequency of the jitter is fast (I.e., it does not stay at an extreme value for a long time) then  
the maximum allowed jitter on EXTAL can be up to 2%.  
3
4
The timings specified in B4 and B5 are based on full strength clock.  
The timing for BR output is relevant when the MPC857T is selected to work with external bus arbiter. The timing for  
BG output is relevant when the MPC857T is selected to work with internal bus arbiter.  
5
6
7
The timing required for BR input is relevant when the MPC857T is selected to work with internal bus arbiter.The timing  
for BG input is relevant when the MPC857T is selected to work with external bus arbiter.  
The D(0:31) and DP(0:3) input timings B18 and B19 refer to the rising edge of the CLKOUT in which the TA input  
signal is asserted.  
The D(0:31) and DP(0:3) input timings B20 and B21 refer to the falling edge of the CLKOUT. This timing is valid only  
for read accesses controlled by chip-selects under control of the UPM in the memory controller, for data beats where  
DLT3 = 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)  
8
9
The timing B30 refers to CS when ACS = 00 and to WE(0:3) when CSNT = 0.  
The signal UPWAIT is considered asynchronous to the CLKOUT and synchronized internally. The timings specified  
in B37 and B38 are specified to enable the freeze of the UPM output signals as described in Figure 18.  
10  
The AS signal is considered asynchronous to the CLKOUT.The timing B39 is specified in order to allow the behavior  
specified in Figure 21.  
Figure 3 is the control timing diagram.  
MOTOROLA  
MPC857THardwareSpecifications  
19  
Bus Signal TimingReferences  
Figure 3. Control Timing  
Figure 4 provides the timing for the external clock.  
Figure 4. External Clock Timing  
Figure 5 provides the timing for the synchronous output signals.  
20  
MPC857THardwareSpecifications  
MOTOROLA  
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