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IX2R11S3

型号：

IX2R11S3

品牌：

IXYS[ IXYS CORPORATION ]

页数：

13 页

PDF大小：

290 K

下载PDF手册
IX2R11  
500 Volt, 2 Ampere High & Low-side Driver  
for N-Channel MOSFETs and IGBTs  
General Description  
Features  
• Floating High Side Driver with boot-strap power  
supply along with a Low Side Driver.  
• Fully operational to 500V  
• ± 50V/ns dV/dt immunity  
• Gate drive power supply range: 10 - 35V  
• Undervoltage lockout for both output drivers  
• Separate logic power supply range: 3.3V to VCL  
• Built using the advantages and compatibility  
of CMOS and IXYS HDMOSTM processes  
• Latch-Up protected over entire  
operating range  
The IX2R11 High Side and Low Side Driver is for driving N-  
channel MOSFETs and IGBTs with high side and low side  
outputs, whose input signals reference the low side. The High  
Side driver can control a MOSFET or IGBT connected to a  
positive bus voltage up to 500V. The logic input stages are  
compatible with TTL or CMOS, have built-in hysteresis and are  
fully immune to latch up over the entire operating range. The  
IX2R11 can withstand dV/dt on the output side up to ± 50V/ns.  
The IX2R11 comes in either the 16-PIN SOIC package  
(IX2R11S3) or the 14-PIN DIP through-hole package  
(IX2R11P7).  
• Matched propagation delay for both outputs  
• High peak output current: 2A  
• Lowoutputimpedance  
• Low power supply current  
• Immunetonegativevoltagetransients  
Ordering Information  
Part Number  
Package Type  
IX2R11P7  
IX2R11S3  
14-PIN DIP  
Applications  
16-PIN SOIC  
• Driving MOSFETs and IGBTs in half-bridge circuits  
• High voltage, high side and low side drivers  
• Motor Controls  
• Switch Mode Power Supplies (SMPS)  
• DC to DC Converters  
Warning: The IX2R11 is ESD sensitive.  
Precaution: When performing the High-Voltage  
tests, adequate safety precautions should be taken.  
• Class D Switching Amplifiers  
* Operational voltage rating of 500V determined in a typical half-bridge circuit configuration (refer to Figure 10 and Figure 11).  
Operational voltage in other circuit configurations may vary  
Figure 1. Typical Circuit Connection  
Up to 500V  
© 2007 IXYS CORPORATION All rights reserved  
1
DS99165C(10/07)  
First Release  
IX2R11  
Figure 2 - IX2R11 Functional Block Diagram  
Pin Description And Configuration  
SYMBOL  
VDD  
HIN  
FUNCTION  
Logic Supply  
HS Input  
LS Input  
DESCRIPTION  
Positive power supply for the chip CMOS functions  
High side Input signal, TTL or CMOS compatible; HGO in phase  
Low side Input signal, TTL or CMOS compatible; LGO in phase  
Chip enable, active low. When driven high, both outputs go low.  
Logic reference ground  
LIN  
ENB  
DG  
Enable  
Ground  
VCH  
Supply Voltage High side power supply, referenced to HS  
HGO  
HS  
Output  
Return  
High side driver output  
High side voltage return  
VCL  
Supply Voltage Low side power supply, referenced to LS  
LGO  
LS  
Output  
Low side driver output  
Low side return  
Ground  
16-PIN SOIC  
14-PIN DIP  
8
7
N/C  
VDD  
HIN  
ENB  
LIN  
HGO  
VCH  
HS  
9
6
10  
11  
12  
13  
14  
5
4
3
2
1
N/C  
VCL  
LS  
DG  
NC  
LGO  
IXYS reserves the right to change limits, test conditions, and dimensions.  
2
IX2R11  
Absolute Maximum Ratings*  
Symbol  
Definition  
Min  
Max  
Units  
VCH  
High side floating supply voltage  
-0.3  
+ 35  
V
VHS  
High side floating supply offset voltage  
Highsidefloatingoutputvoltage  
Low side fixed supply voltage  
-200  
VHS - 0.3  
-0.3  
-0.3  
-0.3  
VLS - 1  
VLS - 0.3  
---  
+500  
VCH + 0.3  
+35  
V
VHGO  
VCL  
V
V
VLGO  
VDD  
Lowsideoutputvoltage  
VCL + 0.3  
VCL+ 0.3  
VLS + 1  
VCL + 0.3  
50  
V
Logicsupplyvoltage  
V
VDG  
Logic supply offset voltage  
V
V
Logic input voltage(HIN, LIN, ENB)  
Allowableoffsetsupplyvoltagetransient  
Package power dissipation@ TAMBIENT ≤ 25oC  
Package power dissipation@ TCASE ≤ 25oC  
Thermalresistance,junction-to-ambient  
Thermalresistance,junction-to-case  
JunctionTemperature  
V
IN  
dVHS/dt  
PD  
V/ns  
W
---  
1.25  
PD  
---  
2.5  
W
RTHJA  
RTHJC  
TJ  
---  
100  
oC/W  
oC/W  
---  
50  
---  
150  
oC  
TS  
Storagetemperature  
-55  
150  
oC  
oC  
TL  
Lead temperature (soldering, 10 secs.)  
---  
300  
Recommended Operating Conditions  
Symbol  
VCH  
Definition  
Min  
VHS+10  
-250  
VHS  
Max  
VHS+20  
+500  
Units  
V
Highsidefloatingsupplyabsolutevoltage  
High side floating supply offset voltage  
Highsidefloatingoutputvoltage  
Low side fixed supply voltage  
Lowsideoutputvoltage  
VHS  
V
VHGO  
VCL  
VHS+VCH  
20  
V
10  
V
VLGO  
VDD  
0
VCL  
V
Logicsupplyvoltage  
VDG+3  
VLS-0.3  
VDG  
VDG+VCL  
VLS+0.3  
VDD  
V
VDG  
Logic supply offset voltage  
Logic input voltage(HIN, LIN, ENB)  
AmbientTemperature  
V
V
V
IN  
TA  
-40  
125  
oC  
*Note: Operating the device beyond parameters with listed “absolute maximum ratings” may cause permanent  
damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device  
reliability.  
© 2007 IXYS CORPORATION All rights reserved  
3
IX2R11  
*
Dynamic Electrical Characteristics  
Symbol Definition  
Test Conditions  
Min  
---  
Typ  
140  
100  
90  
Max Units  
ton  
toff  
tenb  
tr  
Turn-onpropagationdelay  
Turn-offpropagationdelay  
Enable delay, active low  
Turn-onrisetime  
Cload = 1nF VDD, VCL,VCH=15V  
Cload= 1nF VDD, VCL,VCH=15V  
VDD=15V VCL,VCH=18V  
Cload= 1nF VCH, VCL=15V  
Cload= 1nF VCH, VCL=15V  
170  
120  
110  
11  
ns  
ns  
ns  
ns  
ns  
ns  
---  
---  
---  
8
tf  
Turn-offfalltime  
---  
7
10  
tdm  
Delay matching, HS & LS turn-on/off  
---  
30  
40  
Static Electrical Characteristics  
Symbol  
Definition  
Test Conditions  
VDD,VCL,VCH=15V  
VDD,VCL,VCH=15V  
IO= 20mA  
Min  
9.5  
---  
Typ  
9.8  
5.8  
0.3  
Max Units  
VINH  
Logic“1”inputvoltage  
Logic“0”inputvoltage  
---  
6
V
V
V
VINL  
VHLGO // VHHGO High level output voltage,  
VCH-VHGO or VCL-VLGO  
---  
1
VLLGO // VLHGO Low level output voltage,  
VHGO or VLGO  
IO= 20mA  
---  
0.04  
0.1  
V
IHL  
HS to LS bias (leakage) current.  
Quiescent VCH supply current  
Quiescent VCL supply current  
Quiescent VDD supply current  
Logic “1” input bias current  
Logic “0” input bias current  
VHS Offset = 600V  
VIN= 0V, VCH =15V  
VIN= 0V, VCL=15V  
VIN= 0V, VDD=15V  
VIN= VDD = 15V  
VIN= 0V  
---  
---  
---  
---  
---  
---  
7
100  
700  
160  
0.2  
11  
150  
1000  
300  
5
uA  
uA  
uA  
uA  
uA  
uA  
V
IQHS  
IQLS  
IQDD  
IIN+  
25  
1
IIN-  
---  
VCHUV  
VCHUV  
+
-
VCH supplyunder-voltagepositivegoingthreshold.  
8.1  
8
9
VCH supplyunder-voltagenegativegoingthreshold.  
7
9
V
VCLUV  
+
-
VCL supplyunder-voltagepositivegoingthreshold  
9
9.9  
9.2  
2.5  
-2.5  
11  
10.5  
---  
V
VCLUV  
VCL supplyunder-voltagenegativegoingthreshold.  
8.2  
2
V
IGO  
+
HS or LS output high short circuit sourcing current; VGO= 15V, PW<10us  
HS or LS output low short circuit sinking current; VGO= 0V, PW<10us  
A
IGO-  
---  
-2  
A
* These characteristics are guaranteed by design only. Tested on a sample basis.  
IXYS reserves the right to change limits, test conditions, and dimensions.  
4
IX2R11  
Timing Waveform Definitions  
ENB  
50%  
HIN/LIN  
ENB  
tenb  
10%  
LGO/HGO  
LGO/HGO  
Figure3.INPUT/OUTPUTTimingDiagram  
Figure 4. ENABLE Waveform Definitions  
50%  
50%  
50%  
tr  
50%  
tdoff  
HIN  
LIN  
HIN/LIN  
Input Signal  
tdon  
tf  
90%  
tdm  
90%  
10%  
90%  
10%  
LGO  
HGO  
10%  
LGO  
HGO  
HGO/LGO  
tdm  
Outgoing Signal  
Figure 5. Definitions of Switching Time Waveforms  
Figure 6. Definitions of Delay Matching Waveforms  
VCL=15V  
650V  
VCH  
500V  
400V  
10  
uF  
0.1  
uF  
+
0.1  
uF  
10  
uF  
9
3
6
-
5
7
VHS  
CL  
10  
uF  
10  
(0 to 650V)  
HGO  
HIN  
ENB  
LIN  
~
~
~
~
11  
12  
IX2R11  
1
LGO  
0
CL  
13  
2
200kHz  
500kHz  
1MHz  
fPWM  
Figure 7. Switching Time Test Circuit  
Figure 8. Device operating range: Buss voltage vs. Frequency  
Tested in typical circuit configuration (refer to Figures 10 & 11)  
© 2007 IXYS CORPORATION All rights reserved  
5
IX2R11  
C2  
10uF  
+
U1  
C5  
IX2R11  
0.1uF  
HS  
VCH  
OUTPUT MONITOR  
HV SCOPE PROBE  
HGO  
HS  
HGO  
HS  
GND2  
C1  
GND2  
VDD  
HIN  
ENB  
LIN  
DG  
LS  
VCL  
LGO  
LS  
L1  
200uH  
D1  
C6  
0.1uF  
+
+
C3  
10uF  
LS  
100uF/250V  
U2  
15V  
3
1
78L15 Vout  
Vin  
GND1  
dVs/dt > 50V/ns  
18V  
V1  
2
HV  
600V  
GND1  
BATTERY  
15V  
V3  
C9  
10uF  
C8  
Measure dV/dt (HV Scope Probe)  
0.1uF  
PULSE  
Q1  
VCC  
16  
U3  
BNC  
2
U2  
D2  
DSEI12-10A  
1,8  
6,7  
2
OUT  
IXDD414  
3
15  
HCPL-314J  
½
14  
VEE  
4,5  
-600V  
IXFP4N100Q  
GND2  
10K  
GND3  
GND3  
Figure 9. Test circuit for allowable offset supply voltage transient.  
Up to 400V  
1
VCH  
VIN+  
3
1
IXCP  
10M90S  
2
10  
11  
12  
15  
1k  
VOUT-  
VOUT+  
GND  
VOUT-  
VOUT+ 14  
1uF/35V MLCC  
30  
5.1  
1N5817  
15  
IXTH14N60P  
18uH  
11  
12  
8
7
6
HS  
NC  
VDD  
HGO  
VCH  
1uF/35V MLCC  
10uF/35V  
13  
14  
15  
16  
17  
18  
VDD  
HIN  
ENB  
LIN  
HS  
NC  
NC  
0.1uF/1kV  
1k  
1k  
1k  
5
4
HIN  
ENB  
LIN  
DG  
LS  
0.47uF  
5.1  
0.47uF  
IXTH14N60P  
3
2
1
1N5817  
VCL  
LS  
15  
LGO  
VCL  
1uF/35V MLCC  
10uF/35V  
Figure 10. Test circuit for high frequency, 750kHz, operation.  
VDD, VCH, VCL = 15V  
IXYS reserves the right to change limits, test conditions, and dimensions.  
6
IX2R11  
Up to 500V  
1
VCH  
VIN+  
3
1
IXCP  
10M90S  
2
10  
11  
12  
15  
1k  
VOUT-  
VOUT+  
GND  
VOUT-  
VOUT+ 14  
1uF/35V MLCC  
30  
5.1  
1N5817  
51  
11  
12  
IXTH14N60P  
8
7
6
HS  
NC  
VDD  
HIN  
HGO  
VCH  
1uF/35V MLCC  
10uF/35V  
13  
14  
15  
16  
17  
18  
VDD  
HIN  
HS  
NC  
NC  
0.1uF/1kV  
1k  
1k  
1k  
5
4
ENB  
LIN  
ENB  
LIN  
DG  
LS  
5.1  
3
2
1
1N5817  
VCL  
IXTH14N60P  
LS  
51  
LGO  
VCL  
1uF/35V MLCC  
10uF/35V  
Figure 11. Test circuit for low frequency, 75kHz, operation.  
VDD, VCH, VCL = 15V  
© 2007 IXYS CORPORATION All rights reserved  
7
IX2R11  
Figure 13  
Figure 12  
Fall Times vs. VCL, VCH Supply Voltage  
Rise Times vs. VCL, VCH Supply Voltage  
CLOAD = 1000pF VDD = 5V  
CLOAD = 1000pF VDD = 5V  
8.5  
8
10  
9.5  
9
High Side  
7.5  
7
High Side  
Low Side  
8.5  
8
6.5  
6
7.5  
7
Low Side  
5.5  
5
6.5  
6
4.5  
5.5  
5
5
4
5
10  
15  
20  
25  
30  
35  
10  
15  
20  
25  
30  
35  
VCL / VCH Supply Voltage (V)  
VCL / VCH Supply Voltage (V)  
Figure 14  
Figure 15  
Fall Times vs. Temperature  
LOAD = 1000pF VDD, VCL, VCH = 15V  
Rise Times vs. Temperature  
LOAD = 1000pF VDD, VCL, VCH = 15V  
C
C
12  
10  
8
14  
12  
10  
8
High side  
Low side  
High side  
Low side  
6
6
4
4
2
2
0
0
-100  
-50  
0
50  
100  
150  
-100  
-50  
0
50  
100  
150  
Temperature (C)  
Temperature (C)  
Figure 16  
Figure 17  
Input Threshold Level vs. Temperature  
VDD,VCL,VCH = 15V  
Input Threshold vs. VDD Supply Voltage  
18  
16  
14  
12  
10  
8
12  
10  
8
Rising input level  
Falling input level  
Positive going  
6
6
4
Negative going  
4
2
2
0
0
0
5
10  
15  
20  
25  
30  
-60  
-10  
40  
90  
140  
VDD Supply Voltage (V)  
Temperature (C)  
IXYS reserves the right to change limits, test conditions, and dimensions.  
8
IX2R11  
Figure 19  
Turn Off Propagation Delay vs. VCL, VCH Voltage  
DD = 5V  
Figure 18  
Turn On Propagation Delay vs. VCL, VCH Voltage  
DD = 5V  
V
V
180  
160  
140  
120  
100  
80  
140  
120  
100  
80  
Low Side  
High Side  
High Side  
Low Side  
60  
60  
40  
40  
20  
20  
0
0
5
10  
15  
20  
25  
30  
35  
5
10  
15  
20  
25  
30  
35  
VCL / VCH Supply Voltage (V)  
VCL / VCH Supply Voltage (V)  
Figure 21  
Figure 20  
Turn Off Propagation Delay vs. VDD Supply Voltage  
Turn On Propagation Delay vs. VDD Supply Voltage  
130  
120  
110  
100  
90  
170  
160  
150  
140  
130  
120  
110  
100  
VCH=12V  
V
CH=18V  
VCL=25V  
VCH=25V  
80  
V
CL=18V  
VCL=12V  
VCL=12V  
VCH=12V  
70  
VCL=18V  
60  
VCL=25V  
VCH=18V  
50  
VCH=25V  
40  
0
5
10  
15  
20  
25  
0
5
10  
15  
20  
25  
VDD Logic Supply (V)  
VDD Supply Voltage (V)  
Figure 22  
Figure 23  
Turn Off Propagation Delay vs. Temperature  
VDD, VCL, VCH = 15V  
Turn On Propagation Delay vs. Temperature  
V
DD, VCL, VCH = 15V  
120  
100  
80  
140  
120  
100  
80  
Low side  
High side  
High Side  
60  
Low side  
60  
40  
40  
20  
20  
0
0
-100  
-50  
0
50  
100  
150  
-100  
-50  
0
50  
100  
150  
Temperature (C)  
Temperature (C)  
© 2007 IXYS CORPORATION All rights reserved  
9
IX2R11  
Figure 24  
Figure 25  
Enable Threshold vs. VDD Logic Supply Voltage  
Active Low Enable  
ENABLE Shut Off Delay vs. VDD Supply Voltage  
130  
120  
110  
100  
90  
18  
16  
14  
12  
10  
8
Low Side  
VCL = 10V  
Postive Going  
Outputs Disabled  
V
CL = 18V  
CL = 25V  
CL = 35V  
High Side  
V
V
6
VCH = 10V  
80  
Negative Going  
Outputs Enabled  
4
70  
VCH = 18V  
2
VCH = 25,35V  
20 25  
60  
0
0
5
5
10  
15  
10  
15  
20  
25  
VDD Supply Voltage (V)  
VDD Supply Voltage (V)  
Figure 26  
Figure 27  
Quiescent Supply Currents vs. Supply Voltages  
VINL, VINH = 0V  
ENABLE Shutdown Delay vs. Temperature  
VDD, VCL, VCH = 15V  
140  
120  
100  
80  
1
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
High side  
I
CH (mA)  
60  
Low side  
40  
IDD (uA)  
ICL (mA)  
20  
0
0
0
-60  
-40  
-20  
0
20  
40  
60  
80  
100  
120  
140  
5
10  
15  
20  
25  
30  
35  
40  
Temperature (C)  
VCL, VCH, VDD Supply Voltage (V)  
Figure 28  
Figure 29  
Quiescent Supply Current vs. Temperature  
LIN, HIN Input Bias Current vs. VDD Supply Voltage  
V
DD,VCL,VCH = 15V VINL, VINH = 0V  
20  
18  
16  
14  
12  
10  
8
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
VCH (mA)  
6
V
CL (mA)  
4
VDD (uA)  
2
0
0
-100  
-50  
0
50  
100  
150  
0
5
10  
15  
20  
25  
VDD Voltage (V)  
Temperature (C)  
IXYS reserves the right to change limits, test conditions, and dimensions.  
10  
IX2R11  
Figure 30  
Figure 31  
High Level Ouput Voltage vs. Supply Voltage  
Low Level Output Voltage vs. Supply Voltage  
VLLGO / VLHGO = VLGO / VHGO IO = 20mA  
VHLGO / VHHGO = VCL - VLGO / VCH - VHGO IOUT = 20mA  
0.45  
0.4  
0.06  
0.05  
0.04  
0.03  
0.02  
0.01  
0.35  
0.3  
0.25  
0.2  
0.15  
0.1  
0.05  
0
0
5
5
10  
15  
20  
25  
30  
35  
10  
15  
20  
25  
30  
35  
VCL, VCH (V)  
VCL, VCH (V)  
Figure 32  
Figure 33  
Under Voltage Lock Out vs. Temperature  
Negative Going Trip Point  
Under Voltage Lock Out vs. Temperature  
Positive Going Trip Point  
12  
10  
8
12  
10  
8
VCL  
VCL  
VCH  
VCH  
6
6
4
4
2
2
0
0
-100  
-50  
0
50  
100  
150  
-100  
-50  
0
50  
100  
150  
Temperature (C)  
Temperature (C)  
Figure 34  
Figure 35  
Output Sink Current vs. Supply Voltage  
Output Source Current vs. Supply Voltage  
0
6
5
4
3
2
1
-1  
-2  
-3  
-4  
-5  
0
0
-6  
0
5
10  
15  
20  
25  
30  
35  
40  
5
10  
15  
20  
25  
30  
35  
40  
VCL, VCH Supply Voltage (V)  
© 2007 IXYS CORPORATION All rights reserved  
VCL, VCH Supply Voltage (V)\  
11  
IX2R11  
Figure 36  
Offset Leakage Current vs. High Side Offset Voltage  
Figure 37  
Offset Leakage Current vs. Temperature  
High Side Offset Voltage = 600V  
106  
104  
102  
100  
98  
120  
100  
80  
60  
40  
20  
0
96  
94  
92  
90  
-100  
-50  
0
50  
100  
150  
0
100  
200  
300  
400  
500  
600  
700  
Temperature (C)  
High Side Offset Voltage (V)  
Figure 38  
Figure 39  
Output Sinking Current vs. Temperture  
DD, VCL, VCH = 15V  
Output Sourcing Current vs. Temperature  
VDD, VCL, VCH = 15V  
V
2.5  
2
3
2.5  
2
1.5  
1
1.5  
1
0.5  
0.5  
0
0
-100  
-50  
0
50  
100  
150  
-100  
-50  
0
50  
100  
150  
Temperature (C)  
Temperature (C)  
IXYS reserves the right to change limits, test conditions, and dimensions.  
12  
IX2R11  
IX2R11S3 Package Outline  
IX2R11P7 Package Outline  
IXYS Corporation  
IXYS Semiconductor GmbH  
3540 Bassett St; Santa Clara, CA 95054  
Tel: 408-982-0700; Fax: 408-496-0670  
e-mail: sales@ixys.net  
Edisonstrasse15 ; D-68623; Lampertheim  
Tel: +49-6206-503-0; Fax: +49-6206-503627  
e-mail: marcom@ixys.de  
www.ixys.com  
© 2007 IXYS CORPORATION All rights reserved  
13  
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