请登录

免费注册
全部商品
电子元器件
方案中心
工业品
PDF资料
购物车 0
上传BOM

产品分类

找货询价

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

QQ咨询

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

会员中心
购物车
技术支持

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

售后咨询

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

5V9950PFGI

型号：

5V9950PFGI

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

9 页

PDF大小：

109 K

下载PDF手册
JR.  
3.3V PROGRAMMABLE SKEW  
PLL CLOCK DRIVER  
IDT5V9950  
NRND  
TURBOCLOCK™ II JR.  
FEATURES:  
DESCRIPTION:  
• Ref input is 5V tolerant  
The IDT5V9950 is a high fanout 3.3V PLL based clock driver intended  
for high performance computing and data-communications applica-  
tions. A key feature of the programmable skew is the ability of outputs  
to lead or lag the REF input signal. The IDT5V9950 has eight program-  
mable skew outputs in four banks of 2. Skew is controlled by 3-level  
input signals that may be hard-wired to appropriate HIGH-MID-LOW  
levels.  
• 4 pairs of programmable skew outputs  
• Low skew: 185ps same pair, 250ps all outputs  
• Selectable positive or negative edge synchronization:  
Excellent for DSP applications  
• Synchronous output enable  
• Input frequency: 6MHz to 200MHz  
• Output frequency: 6MHz to 200MHz  
• 2x, 4x, 1/2, and 1/4 outputs  
• 3-level inputs for skew and PLL range control  
• PLL bypass for DC testing  
• External feedback, internal loop filter  
• 12mA balanced drive outputs  
• Low Jitter: <100ps cycle-to-cycle  
• Available in TQFP package  
When the sOEpin is held low, all the outputs are synchronously  
enabled. However, if sOEis held high, all the outputs except 2Q0 and  
2Q1 are synchronously disabled.  
Furthermore, when PE is held high, all the outputs are synchronized  
with the positive edge of the REF clock input. When PE is held low, all  
the outputs are synchronized with the negative edge of REF. The  
IDT5V9950 has LVTTL outputs with 12mA balanced drive outputs.  
• Not Recommended for New Design  
FUNCTIONAL BLOCK DIAGRAM  
sOE  
1Q0  
Skew  
Select  
1Q1  
3
3
1F1:0  
2F1:0  
PE TEST  
3
2Q0  
2Q1  
Skew  
Select  
3
3
3
3
REF  
PLL  
FB  
3Q0  
3Q1  
Skew  
Select  
3
3
FS  
3F1:0  
4F1:0  
4Q0  
4Q1  
Skew  
Select  
3
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
INDUSTRIAL TEMPERATURE RANGE  
JULY 2012  
1
c
2012 Integrated Device Technology, Inc.  
DSC 5870/7  
IDT5V9950  
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II  
INDUSTRIAL TEMPERATURE RANGE  
JR.  
PIN CONFIGURATION  
ABSOLUTE MAXIMUM RATINGS(1)  
Symbol  
Description  
Max  
–0.5 to +4.6  
–0.5 to VDD+0.5  
–0.5 to +5.5  
0.7  
Unit  
V
VDDQ, VDD Supply Voltage to Ground  
VI  
DC Input Voltage  
REF Input Voltage  
Maximum Power  
Dissipation  
V
V
32 31 30 29 28 27 26 25  
TA = 85°C  
TA = 55°C  
W
24  
23  
22  
21  
20  
19  
18  
17  
3F1  
4F0  
1
2
3
4
5
6
7
8
1F1  
1F0  
1.1  
TSTG  
Storage Temperature Range  
–65 to +150  
°C  
NOTE:  
4F1  
PE  
sOE  
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause per-  
manent damage to the device. These are stress ratings only, and functional operation of  
the device at these or any other conditions above those indicated in the operational  
sections of this specification is not implied. Exposure to absolute-maximum-rated condi-  
tions for extended periods may affect device reliability.  
VDDQ  
VDDQ  
4Q1  
1Q0  
1Q1  
GND  
GND  
4Q0  
CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V)  
GND  
Parameter Description  
Typ.  
Max.  
Unit  
9
10 11 12 13 14 15 16  
CIN  
Input Capacitance  
5
7
pF  
NOTE:  
1. Capacitance applies to all inputs except TEST, FS, nF[1:0], and DS[1:0].  
TQFP  
TOP VIEW  
PIN DESCRIPTION  
Pin Name  
REF  
Type  
IN  
Description  
Reference Clock Input  
Feedback Input  
FB  
IN  
TEST (1)  
IN  
WhenMIDorHIGH, disablesPLL(exceptforconditionsofNote1). REFgoestoalloutputs. SkewSelections(SeeControlSummary  
Table) remain in effect. Set LOW for normal operation.  
sOE(1)  
IN  
IN  
Synchronous Output Enable. When HIGH, it stops clock outputs (except 2Q0 and 2Q1) in a LOW state (for PE = H) - 2Q0 and 2Q1  
may be used as the feedback signal to maintain phase lock. When TEST is held at MID level and sOEis HIGH, the nF[1:0] pins  
act as output disable controls for individual banks when nF[1:0] = LL. Set sOELOW for normal operation (has internal pull-down).  
PE  
Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the  
reference clock (has internal pull-up).  
nF[1:0]  
FS  
IN  
3-level inputs for selecting 1 of 9 skew taps or frequency functions  
Selects appropriate oscillator circuit based on anticipated frequency range. (See Programmable Skew Range.)  
Four banks of two outputs with programmable skew  
IN  
nQ[1:0]  
VDDQ  
VDD  
OUT  
PWR  
PWR  
PWR  
Power supply for output buffers  
Power supply for phase locked loop, lock output, and other internal circuitry  
Ground  
GND  
NOTE:  
1. When TEST = MID and sOE= HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections remain in effect unless  
nF[1:0] = LL.  
2
IDT5V9950  
INDUSTRIAL TEMPERATURE RANGE  
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II  
JR.  
PROGRAMMABLE SKEW  
Output skew with respect to the REF input is adjustable to com- the nF1:0 control pins. In order to minimize the number of control  
pensate for PCB trace delays, backplane propagation delays or to pins, 3-level inputs (HIGH-MID-LOW) are used, they are intended for  
accommodate requirements for special timing relationships between but not restricted to hard-wiring. Undriven 3-level inputs default to  
clocked components. Skew is selectable as a multiple of a time unit the MID level. Where programmable skew is not a requirement, the  
(tU) which ranges from 625ps to 1.3ns (see Programmable Skew control pins can be left open for the zero skew default setting. The  
Range and Resolution Table). There are nine skew configurations Control Summary Table shows how to select specific skew taps by  
available for each output pair. These configurations are chosen by using the nF1:0 control pins.  
EXTERNAL FEEDBACK  
By providing external feedback, the IDT5V9950 gives users flex-  
An internal loop filter moderates the response of the VCO to the  
ibility with regard to skew adjustment. The FB signal is compared phase detector. The loop filter transfer function has been chosen to  
with the input REF signal at the phase detector in order to drive the provide minimal jitter (or frequency variation) while still providing ac-  
VCO. Phase differences cause the VCO of the PLL to adjust upwards curate responses to input frequency changes.  
or downwards accordingly.  
PROGRAMMABLE SKEW RANGE AND RESOLUTION TABLE  
FS = LOW  
1/(32 x FNOM)  
24 to 50MHz  
FS = MID  
FS = HIGH  
1/(8 x FNOM)  
96 to 200MHz  
Comments  
Timing Unit Calculation (tU)  
VCO Frequency Range (FNOM)(1,2)  
Skew Adjustment Range(3)  
Max Adjustment:  
1/(16 x FNOM)  
48 to 100MHz  
±7.8125ns  
±67.5°  
±18.75%  
tU = 1.25ns  
tU = 0.833ns  
tU = 0.625ns  
—
±7.8125ns  
±135°  
±7.8125ns  
±270°  
±75%  
ns  
Phase Degrees  
% of Cycle Time  
±37.5%  
—
Example 1, FNOM = 25MHz  
Example 2, FNOM = 37.5MHz  
Example 3, FNOM = 50MHz  
Example 4, FNOM = 75MHz  
Example 5, FNOM = 100MHz  
Example 6, FNOM = 150MHz  
Example 7, FNOM = 200MHz  
—
—
—
tU = 1.25ns  
tU = 0.833ns  
tU = 0.625ns  
—
—
—
—
tU = 1.25ns  
tU = 0.833ns  
tU = 0.625ns  
—
—
—
NOTES:  
1. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed.  
2. The level to be set on FS is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO frequency always appears at 1Q1:0, 2Q1:0, and the higher outputs  
when they are operated in their undivided modes. The frequency appearing at the REF and FB inputs will be the same as VCO when the output connected to FB is undivided. The frequency  
of the REF and FB inputs will be 1/2 or 1/4 the VCO frequency when the part is configured for frequency multiplication by using a divided output as the FB input.  
3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then adjustment range will be greater. For example if a 4tU skewed  
output is used for feedback, all other outputs will be skewed –4tU in addition to whatever skew value is programmed for those outputs. ‘Max adjustment’ range applies to output pairs 3 and  
4 where ± 6tU skew adjustment is possible and at the lowest FNOM value.  
3
IDT5V9950  
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II  
INDUSTRIAL TEMPERATURE RANGE  
JR.  
CONTROL SUMMARY TABLE FOR FEEDBACK SIGNALS  
nF1:0  
LL (1)  
LM  
Skew (Pair #1, #2)  
Skew (Pair #3)  
Divide by 2  
–6tU  
Skew (Pair #4)  
Divide by 2  
–6tU  
–4tU  
–3tU  
LH  
–2tU  
–4tU  
–4tU  
ML  
–1tU  
–2tU  
–2tU  
MM  
MH  
HL  
Zero Skew  
1tU  
Zero Skew  
2tU  
Zero Skew  
2tU  
2tU  
4tU  
4tU  
HM  
HH  
3tU  
6tU  
6tU  
Inverted (2)  
4tU  
Divide by 4  
NOTES:  
1. LL disables outputs if TEST = MID and sOE = HIGH.  
2. When pair #4 is set to HH (inverted), sOEdisables pair #4 HIGH when PE = HIGH, sOE disables pair #4 LOW when PE = LOW.  
RECOMMENDED OPERATING RANGE  
Symbol  
VDD/VDDQ  
TA  
Description  
Min.  
3
Typ.  
3.3  
Max.  
3.6  
Unit  
V
Power Supply Voltage  
Ambient Operating Temperature  
-40  
+25  
+85  
°C  
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE  
Symbol  
Parameter  
Conditions  
Guaranteed Logic HIGH (REF, FB Inputs Only)  
Guaranteed Logic LOW (REF, FB Inputs Only)  
3-Level Inputs Only  
Min.  
Max.  
Unit  
V
VIH  
Input HIGH Voltage  
2
—
—
0.8  
VIL  
Input LOW Voltage  
Input HIGH Voltage(1)  
Input MID Voltage(1)  
Input LOW Voltage(1)  
Input Leakage Current  
(REF, FB Inputs Only)  
V
VIHH  
VIMM  
VILL  
IIN  
VDD−0.6  
VDD/2−0.3  
—
—
V
3-Level Inputs Only  
VDD/2+0.3  
0.6  
V
3-Level Inputs Only  
V
VIN = VDD or GND  
−5  
+5  
μA  
VDD = Max.  
VIN = VDD  
HIGH Level  
MID Level  
LOW Level  
—
−50  
−200  
−100  
—
+200  
+50  
—
I3  
3-Level Input DC Current (TEST, FS, nF[1:0])  
VIN = VDD/2  
μA  
VIN = GND  
IPU  
IPD  
Input Pull-Up Current (PE)  
Input Pull-Down Current (sOE)  
Output HIGH Voltage  
VDD = Max., VIN = GND  
VDD = Max., VIN = VDD  
VDDQ = Min., IOH = −12mA2.4  
VDDQ = Min., IOL = 12mA  
—
μA  
μA  
+100  
V
VOH  
VOL  
—
Output LOW Voltage  
—
0.4  
V
NOTE:  
1. These inputs are normally wired to VDD, GND, or unconnected. Internal termination resistors bias unconnected inputs to VDD/2. If these inputs are switched, the function and timing of the  
outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are achieved.  
4
IDT5V9950  
INDUSTRIAL TEMPERATURE RANGE  
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II  
JR.  
POWER SUPPLY CHARACTERISTICS  
Symbol  
Parameter  
Test Conditions(1)  
VDD = Max., TEST = MID, REF = LOW,  
PE = LOW, sOE= LOW, FS = MID  
All outputs unloaded  
Typ.(2)  
Max.  
Unit  
IDDQ  
Quiescent Power Supply Current  
20  
30  
mA  
ΔIDD  
IDDD  
ITOT  
Power Supply Current per Input HIGH  
(REF and FB inputs only)  
VIN = 3V, VDD = Max., TEST = HIGH  
1
30  
μA  
μA/MHz  
mA  
FS = L  
190  
150  
130  
56  
290  
230  
200  
—
Dynamic Power Supply Current per Output FS = M  
FS = H  
FS = L , FVCO = 50MHz, CL = 0pF  
Total Power Supply Current  
FS = M , FVCO = 100MHz, CL = 0pF  
FS = H, FVCO = 200MHz, CL = 0pF  
80  
—
125  
—
NOTES:  
1. Measurements are for divide-by-1 outputs and nF[1:0] = MM.  
2. For nominal voltage and temperature.  
INPUT TIMING REQUIREMENTS  
Symbol  
tR, tF  
tPWC  
DH  
Description(1)  
Maximum input rise and fall times, 0.8V to 2V  
Input clock pulse, HIGH or LOW  
Input duty cycle  
Min.  
—
2
Max.  
Unit  
10  
—
ns/V  
ns  
10  
6
90  
%
FS = LOW  
FS = MID  
FS = HIGH  
50  
FREF  
Reference clock input frequency  
12  
24  
100  
200  
MHz  
NOTE:  
1. Where pulse width implied by DH is less than tPWC limit, tPWC limit applies.  
5
IDT5V9950  
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II  
INDUSTRIAL TEMPERATURE RANGE  
JR.  
SWITCHING CHARACTERISTICS OVER OPERATING RANGE  
Symbol  
FNOM  
tRPWH  
tRPWL  
tU  
Parameter  
Min.  
Typ.  
Max.  
Unit  
VCO Frequency Range  
REF Pulse Width HIGH(1)  
REF Pulse Width LOW(1)  
See Programmable Skew Range and Resolution Table  
2
2
—
—
—
ns  
ns  
—
Programmable Skew Time Unit  
See Control Summary Table  
tSKEWPR  
tSKEW0  
tSKEW1  
tSKEW2  
tSKEW3  
tSKEW4  
tDEV  
Zero Output Matched-Pair Skew (xQ0, xQ1)(2,3)  
Zero Output Skew (All Outputs)(4)  
—
—
50  
0.1  
0.1  
0.2  
0.15  
0.3  
—
185  
0.25  
0.25  
0.5  
0.5  
0.9  
0.75  
0.25  
1
ps  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ms  
Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs)(5)  
Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided)(5)  
Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs)(5)  
Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted)(2)  
Device-to-Device Skew(2,6)  
REF Input to FB Static Phase Offset)(7)  
Output Duty Cycle Variation from 50%  
Output HIGH Time Deviation from 50%(8)  
Output LOW Time Deviation from 50%(9)  
Output Rise Time  
—
—
—
—
—
t(φ)  
−0.25  
−1  
—
—
tODCV  
tPWH  
0
—
1.5  
2
tPWL  
—
—
tORISE  
tOFALL  
tLOCK  
tCCJH  
0.15  
0.15  
—
0.7  
0.7  
—
1.5  
1.5  
0.5  
100  
Output Fall Time  
PLL Lock Time(10)  
Cycle-to-Cycle Output Jitter (peak-to-peak)  
(divide by 1 output frequency, FS = H, FB divide-by-n=1,2)  
Cycle-to-Cycle Output Jitter (peak-to-peak)  
(divide by 1 output frequency, FS = M)  
Cycle-to-Cycle Output Jitter (peak-to-peak)  
(divide by 1 output frequency, FS = L, FREF > 3MHz)  
—
—
tCCJM  
tCCJL  
—
—
—
—
150  
200  
ps  
NOTES:  
1. Refer to Input Timing Requirements table for more detail.  
2. Skew is the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with the specified load.  
3. tSKEWPR is the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.  
4. tSK(0) is the skew between outputs when they are selected for 0tU.  
5. There are 3 classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-2 or Divide-by-4 mode).  
Test condition: nF0:1=MM is set on unused outputs.  
6. tDEV is the output-to-output skew between any two devices operating under the same conditions (VDDQ, VDD, ambient temperature, air flow, etc.)  
7. tφ is measured with REF input rise and fall times (from 0.8V to 2V) of 0.5ns. Measured from 1.5V on REF to 1.5V on FB.  
8. Measured at 2V.  
9. Measured at 0.8V.  
10. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VDD/VDDQ is stable and within normal operating limits. This parameter is measured  
from the application of a new signal or frequency at REF or FB until tPD is within specified limits.  
6
IDT5V9950  
INDUSTRIAL TEMPERATURE RANGE  
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II  
JR.  
AC TEST LOADS AND WAVEFORMS  
VDDQ  
150  
Output  
150  
20pF  
tOFALL  
tORISE  
2.0V  
VTH = 1.5V  
0.8V  
tPWH  
tPWL  
LVTTL Output Waveform  
1ns  
1ns  
3.0V  
2.0V  
VTH = 1.5V  
0.8V  
0V  
LVTTL Input Test Waveform  
7
IDT5V9950  
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II  
INDUSTRIAL TEMPERATURE RANGE  
JR.  
AC TIMING DIAGRAM  
tRPWL  
tREF  
tRPWH  
REF  
FB  
Q
t(  
tODCV  
tODCV  
tCCJH,M,L  
tSKEWPR  
tSKEW0, 1  
tSKEWPR  
tSKEW0, 1  
OTHER Q  
tSKEW2  
tSKEW2  
INVERTED Q  
tSKEW3, 4  
tSKEW3, 4  
tSKEW3, 4  
tSKEW2, 4  
REF DIVIDED BY 2  
tSKEW1, 3, 4  
REF DIVIDED BY 4  
NOTES:  
PE:  
The AC Timing Diagram applies to PE=VDD. For PE=GND, the negative edge of FB aligns with the negative edge of REF, divided outputs change on the negative edge of REF,  
and the positive edges of the divide-by-2 and the divide-by-4 signals align.  
Skew:  
The time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with 20pF and terminated with  
75Ω to VDDQ/2.  
tSKEWPR:  
tSKEW0:  
tDEV:  
The skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.  
The skew between outputs when they are selected for 0tU  
.
The output-to-output skew between any two devices operating under the same conditions (VDDQ, VDD, ambient temperature, air flow, etc.)  
The deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications.  
tODCV:  
tPWH is measured at 2V.  
tPWL is measured at 0.8V.  
tORISE and tOFALL are measured between 0.8V and 2V.  
tLOCK:  
The time that is required before synchronization is achieved. This specification is valid only after VDD/VDDQ is stable and within normal operating limits. This parameter is measured  
from the application of a new signal or frequency at REF or FB until tPD is within specified limits.  
8
IDT5V9950  
INDUSTRIAL TEMPERATURE RANGE  
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II  
JR.  
ORDERING INFORMATION  
X
XXXXX  
XX  
IDT  
Package Package  
Device Type  
I
-40°C to +85°C (Industrial)  
Thin Quad Flat Pack  
TQFP - Green  
PF  
PFG  
5V9950  
3.3V Programmable Skew PLL Clock  
Driver TurboClock II Jr.  
CORPORATE HEADQUARTERS  
6024 Silver Creek Valley Road  
San Jose, CA 95138  
for SALES:  
800-345-7015 or 408-284-8200  
fax: 408-284-2775  
for Tech Support:  
clockhelp@idt.com  
www.idt.com  
9
厂商 型号 描述 页数 下载

IDT

 		5V925BQGI 可编程LVCMOS / LVTTL时钟发生器[ Programmable LVCMOS/LVTTL Clock Generator ] 18 页

IDT

 		5V925BQGI8 可编程LVCMOS / LVTTL时钟发生器[ Programmable LVCMOS/LVTTL Clock Generator ] 18 页

IDT

 		5V925BQI 可编程LVCMOS / LVTTL时钟发生器[ Programmable LVCMOS/LVTTL Clock Generator ] 18 页

IDT

 		5V925BQI8 可编程LVCMOS / LVTTL时钟发生器[ Programmable LVCMOS/LVTTL Clock Generator ] 18 页

IDT

 		5V925QGI [ Clock Generator, PDSO16 ] 7 页

IDT

 		5V925QGI8 [ Clock Generator, PDSO16 ] 7 页

IDT

 		5V926APGGI [ TSSOP-16, Tube ] 6 页

IDT

 		5V926APGGI8 [ TSSOP-16, Reel ] 6 页

IDT

 		5V926APGI [ Clock Generator, 160MHz, PDSO16, TSSOP-16 ] 6 页

IDT

 		5V927PGGI8 [ TSSOP-16, Reel ] 6 页

购物指南

支付方式

配送服务

售后服务

发票须知

优惠券使用规则

特色服务

PCBA制造

国产品牌推荐

国产料号替代

质量保证

技术资料

行业资讯

关于我们

关于壹壹捌

联系我们

联系我们

服务热线：400-618-9990

企业邮箱：sales@ic118.com

服务时间：周一至周六 8:30-17:30

壹壹捌官方微信号

PDF索引：

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Q

R

S

T

U

V

W

X

Y

Z

0

1

2

3

4

5

6

7

8

9

IC型号索引：

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Q

R

S

T

U

V

W

X

Y

Z

0

1

2

3

4

5

6

7

8

9

Copyright 2024 gkzhan.com Al Rights Reserved 京ICP备06008810号-21 京

深圳网络警察报警平台
公共信息安全网络监察
经营性网站备案信息
不良信息举报中心
工商网监电子标识
全国公安机关备案
0.193465s