NX25P80-VPI-GT,PDF,NX25P80-VPI-GT PDF资料,Datasheet,下载NX25P80-VPI-GT技术资料

PRELIMINARY

APRIL2005

NX25P80, NX25P16 AND NX25P32

8M-BIT, 16M-BIT AND 32M-BIT

Serial Flash Memory

NexFlashTechnologies, Inc.

1

PRELIMINARY MKP-0010 Rev5 NXSF044G-0405

04/22/05 ©

8M, 16M AND 32M-BIT SERIAL FLASH MEMORY

NX25P80,NX25P16ANDNX25P32

Table of Contents

NX25P80, NX25P16 AND NX25P32

8M-BIT, 16M-BIT AND 32M-BIT Serial Flash Memory ..................................................................................................1

FEATURES..................................................................................................................................................................... 4

GENERAL DESCRIPTION ............................................................................................................................................. 4

Figure 1. NX25P80, NX25P16 and NX25P32 Block Diagram .................................................................................... 5

PIN DESCRIPTIONS ...................................................................................................................................................... 6

PackageTypes ......................................................................................................................................................... 6

Serial Data Input (DI) ................................................................................................................................................ 6

Serial Data Output (DO) ............................................................................................................................................6

Serial Clock (CLK) .................................................................................................................................................... 6

Chip Select (CS) ....................................................................................................................................................... 6

Hold (HOLD) ............................................................................................................................................................. 6

Figure 2A. NX25P80/16 Pin Assignments, 8-pin SOIC (Package Code S) ................................................................ 6

Figure 2B. NX25P16/32 Pin Assignments, 16-pin SOIC (Package Code F )..............................................................6

Table 1.Pin Descriptions .......................................................................................................................................... 6

Write Protect (WP).................................................................................................................................................... 7

SPI OPERATION ............................................................................................................................................................ 7

SPI Modes ............................................................................................................................................................... 7

Hold Function ...........................................................................................................................................................7

WRITE PROTECTION .................................................................................................................................................... 7

Write Protect Features.............................................................................................................................................. 7

STATUS REGISTER....................................................................................................................................................... 8

BUSY .......................................................................................................................................................................8

Write Enable Latch (WEL).........................................................................................................................................8

Figure 3. Status Register Bit Locations..................................................................................................................... 8

Block Protect Bits (BP2, BP1, BP0) ......................................................................................................................... 8

Reserved Bits ...........................................................................................................................................................8

Status Register Protect (SRP) .................................................................................................................................. 8

Table 2:Status Register Memory Protection ............................................................................................................. 9

INSTRUCTIONS ........................................................................................................................................................... 10

Table 3: Instruction Set ........................................................................................................................................... 10

Table 4:Manufacturer and Device Identification ...................................................................................................... 11

Write Enable (06h).................................................................................................................................................... 11

Figure 4.Write Enable Instruction Sequence Diagram ............................................................................................. 11

Write Disable (04h) ................................................................................................................................................... 11

Figure 5.Write Disable Instruction Sequence Diagram ............................................................................................ 11

Read Status Register (05h) ...................................................................................................................................... 12

Figure 6. Read Status Register Instruction Sequence Diagram ............................................................................... 12

Write Status Register (01h) ...................................................................................................................................... 13

Figure 7.Write Status Register Instruction Sequence Diagram ............................................................................... 13

Read Data (03h) ........................................................................................................................................................ 14

Figure 8. Read Data Instruction Sequence Diagram ................................................................................................ 14

Fast Read (0Bh) ........................................................................................................................................................ 15

Figure 9.Fast Read Instruction Sequence Diagram ................................................................................................ 15

Page Program (02h) ................................................................................................................................................. 16

Figure 10.Page Program Instruction Sequence Diagram ........................................................................................ 16

2

NexFlashTechnologies, Inc.

PRELIMINARYMKP-0010 Rev5 NXSF044G-0405

04/22/05 ©

8M, 16M AND 32M-BIT SERIAL FLASH MEMORY

NX25P80,NX25P16ANDNX25P32

Table of Contents

Sector Erase (D8h) ................................................................................................................................................... 17

Figure 11. Sector Erase Instruction Sequence Diagram .......................................................................................... 17

1

Bulk Erase (C7h) ...................................................................................................................................................... 18

Figure 12. Bulk Erase Instruction Sequence Diagram ............................................................................................. 18

2

Power-down (B9h) .................................................................................................................................................... 19

Figure 13.Deep Power-down Instruction Sequence Diagram ................................................................................... 19

Release Power-down / Device ID (ABh)................................................................................................................... 20

Figure 14.Release Power-down Instruction Sequence ............................................................................................ 20

Figure 15.Release Power-down / Device ID Instruction Sequence Diagram ............................................................ 20

3

Read Manufacturer / Device ID (90h) ....................................................................................................................... 21

Figure 16. Read Manufacturer / Device ID Diagram ................................................................................................ 21

4

JEDEC ID (9Fh) ........................................................................................................................................................ 22

Figure 17. Read JEDEC ID ..................................................................................................................................... 22

Read Parameter Page (53h) ..................................................................................................................................... 23

Figure 18.Read Parameter Page Instruction Sequence Diagram............................................................................. 23

5

Fast Read Parameter Page (5Bh)............................................................................................................................. 24

Figure 19.Fast Read Parameter Page Instruction Sequence Diagram ..................................................................... 24

Program Parameter Page (52h) ............................................................................................................................... 25

Figure 20.Parameter Page Program Instruction Sequence Diagram........................................................................ 25

6

Erase Parameter Page (D5h).................................................................................................................................... 26

Figure 21.Parameter Page Erase Instruction Sequence Diagram............................................................................ 26

7

SPECIFICATIONS ANDTIMING DIAGRAMS ............................................................................................................... 27

Table 5. Absolute Maximum Ratings ....................................................................................................................... 27

Table 6.Operating Ranges ...................................................................................................................................... 27

Table 7.Power-upTiming andWrite InhibitThreshold .............................................................................................. 27

Figure 22.Power-upTiming andVoltage Levels....................................................................................................... 27

Table 8.DC Electrical Characteristics (Preliminary) ................................................................................................ 28

Table 9.AC Measurement Conditions ..................................................................................................................... 28

Figure 23.AC Measurement I/O Waveform ............................................................................................................. 28

Table 10.AC Electrical Characteristics (Preliminary)............................................................................................... 29

Figure 24.Serial OutputTiming ............................................................................................................................... 30

Figure 25.InputTiming ........................................................................................................................................... 30

Figure 26.HoldTiming ............................................................................................................................................ 30

8

9

PACKAGING INFORMATION ........................................................................................................................................ 31

8-Pin SOIC 208-mil (Package Code S) ....................................................................................................................... 31

16-Pin SOIC 300-mil (Package Code F) ..................................................................................................................... 32

10

11

12

PRELIMINARY DESIGNATION .................................................................................................................................... 33

IMPORTANT NOTICE ................................................................................................................................................... 33

ORDERING INFORMATION ......................................................................................................................................... 33

LIFE SUPPORT POLICY ............................................................................................................................................. 33

TRADEMARKS ............................................................................................................................................................. 33

Document Revision History ........................................................................................................................................ 34

NexFlashTechnologies, Inc.

3

PRELIMINARY MKP-0010 Rev5 NXSF044G-0405

04/22/05 ©

8M, 16M AND 32M-BIT SERIAL FLASH MEMORY

NX25P80,NX25P16ANDNX25P32

FEATURES

GENERAL DESCRIPTION

•

8M, 16M and 32M-bit Serial Flash Memories

TheNX25P80(8M-bit),NX25P16(16M-bit)andNX25P32

(32M-bit)SerialFlashmemoriesprovideastoragesolution

for systems with limited space, pins and power. They are

ideal for code download applications as well as storing

voice, text and data. The devices operate on a single 2.7V

to 3.6V power supply with current consumption as low as

4mAactiveand1µAforpower-down.Devicesareofferedin

space-saving SOIC packages. As part of a family of Serial

Flashproducts,NexFlashalsoofferscompatibledevicesin

1M/2M/4M-bitdensities.

• Family of Serial Flash Memories

– NX25P80: 8M-bit / 1M-byte (1,048,576 ) 4,096 pages

– NX25P16:16M-bit/2M-byte(2,097,152)8,192pages

– NX25P32:32M-bit/4M-byte(4,194,304)16,384pages

– 256-bytesperprogrammablepage

– Compatible 1M/2M/4M-bit devices also available

•

4-pin SPI Serial Interface

– Clock, Chip Select, Data In, Data Out

– Easily interfaces to popular microcontrollers

– Compatible with SPI Modes 0 and 3

– Optional Hold function for SPI flexibility

The NX25P80/16/32 array is organized into 4,096/8,192/

16,384programmablepagesof256-byteseach.Upto256

bytescanbeprogrammedatatimeusingthePageProgram

instruction. Pages are grouped into 16/32/64 erasable

sectorsof256pages(64K-byte)eachasshowninfigure1.

Both Sector Erase and Bulk (full chip) Erase instructions

aresupported. Additionally, a256-byteParameterPageis

provided for user data that is typically stored in EEPROMs

such as ID or revision numbers and configuration param-

eters. Theparameterpageisseparatefromthemainarray

allowing for much faster erase times.

• Low Power Consumption,WideTemperature Range

– Single 2.7 to 3.6V supply

– 4mA active current, 1µA Power-down (typ)

– -40°to+85°Coperatingrange

• Fast and Flexible Serial Data Access

– Clock operation to 50MHz

The Serial Peripheral Interface (SPI) consists of four pins

(Serial Clock, Chip Select, Serial Data In and Serial Data

Out) that support high speed serial data transfers up to

50MHz. A Hold pin, Write Protect pin and programmable

write protect features provide further control flexibility.

Additionally, the device can be queried for manufacturer

and device type.

– Auto-incrementReadcapability

– Manufacturer and device type ID

• Programming Features

– Page program up to 256 bytes <2ms

– Sector Erase (64K-byte) 2 seconds

– 100,000 erase/write cycles

– Twenty year data retention

• Software and HardwareWrite Protection

– Write-Protect all or portion of memory via software

– Enable/Disable protection with WP pin

8-Pin SOIC 208-mil

NX25P80andNX25P16

(PackageCodeS)

• Parameter Page

– 256 Byte page for ID# revision# or configuration data

– Separate from array, erase time < 200ms

• Space Efficient Packaging

16-Pin SOIC 300-mil

NX25P16andNX25P32

(PackageCodeF)

– 8-pinSOIC(NX25P80andNX25P16)

– 16-pinSOIC(NX25P16andNX25P32)

• Ideal for systems with limited pins, space, and power

– ASICandController-basedserialcode-download

– Microcontroller systems storing data, text or voice

– Battery-operatedandportableproducts

See Pin Descriptions for optional packaging

4

NexFlashTechnologies, Inc.

PRELIMINARYMKP-0010 Rev5 NXSF044G-0405

04/22/05 ©

8M, 16M AND 32M-BIT SERIAL FLASH MEMORY

NX25P80,NX25P16ANDNX25P32

Parameter Page

1

3FFF00h

3F0000h

3FFFFFh

3F00FFh

Sector 63

2

3

4

20FF00h

20FFFFh

5

Sector 32

Sector 31

200000h

1FFF00h

2000FFh

1FFFFFh

6

1F0000h

1F00FFh

7

10FF00h

01FFFFh

Write Control

Logic

WP

Sector 16

Sector 15

100000h

0FFF00h

1000FFh

0FFFFFh

8

0F0000h

0F00FFh

Status

Register

9

00FF00h

000000h

00FFFFh

0000FFh

High Voltage

Generators

Sector 0

*

HOLD

Beginning

Page Address

Ending

Page Address

10

11

12

Page Address

Latch / Counter

CLK

SPI

CS

Command and

Control Logic

Column Decode

and 256 Byte Page Buffer

Data

DI

Byte Address

Latch / Counter

DO

Figure 1. NX25P80, NX25P16 and NX25P32 Block Diagram

NexFlashTechnologies, Inc.

5

PRELIMINARY MKP-0010 Rev5 NXSF044G-0405

04/22/05 ©

8M, 16M AND 32M-BIT SERIAL FLASH MEMORY

NX25P80,NX25P16ANDNX25P32

PIN DESCRIPTIONS

8

7

6

5

1

2

3

4

CS

DO

VCC

HOLD

CLK

DI

PackageTypes

The NX25P80/16/32 are primarily offered in SOIC pack-

ages.TheNX25P80andNX25P16usean8-pinplastic208-

mil width SOIC (package code S) and the NX25P16 and

NX25P32usea16-pinplastic300-milwidthSOIC(package

code F) as shown in figures 2A and 2B respectively.

Packagediagramsanddimensionsareillustratedattheend

of this data sheet. Optional 8-contact MLP packages may

be available. Please contact NexFlash for further MLP

packageinformation.

WP

GND

Figure 2A. NX25P80/16 Pin Assignments,

8-pin SOIC (Package Code S)

Serial Data Input (DI)

16

15

14

13

12

11

10

9

HOLD

VCC

N/C

CS

1

2

3

4

5

6

7

8

The SPI Serial Data Input (DI) pin provides a means for

instructions, addresses and data to be serially written to

(shifted into) the device. Data is latched on the rising edge

of the Serial Clock (CLK) input pin.

CLK

DI

N/C

GND

WP

SerialDataOutput(DO)

The SPI Serial Data Output (DO) pin provides a means for

data and status to be serially read from (shifted out of) the

device. Data is shifted out on the falling edge of the Serial

Clock (CLK) input pin.

DO

SerialClock(CLK)

TheSPISerialClockInput(CLK)pinprovidesthetimingfor

serialinputandoutputoperations.("SeeSPI"Operations")

Figure 2B. NX25P16/32 Pin Assignments,

16-pin SOIC (Package Code F )

Chip Select (CS)

The SPI Chip Select (CS) pin enables and disables device

operation.WhenCSishighthedeviceisdeselectedandthe

Serial Data Output (DO) pin is at high impedance. When

deselected, the devices power consumption will be at

standby levels unless an internal erase, program or status

register cycle is in progress. When CS is brought low the

devicewillbeselected,powerconsumptionwillincreaseto

activelevelsandinstructionscanbewrittentoanddataread

from the device. After power-up, CS must transition from

hightolowbeforeanewinstructionwillbeaccepted.TheCS

input must track the Vcc supply level at power-up (see

“WriteProtection”andfigure17).Ifneededapull-upresister

on CS can be used to accomplish this.

Table 1. Pin Descriptions

DI

DataInput

DO

DataOutput

CLK

CS

Serial Clock Input

Chip Select Input

Write Protect Input

HoldInput

WP

HOLD

Vcc, GND

N/C

PowerSupply

NoConnect

Hold(HOLD)

The HOLD pin allows the device to be paused while it is

actively selected. When HOLD is brought low, while CS is

low,theDOpinwillbeathighimpedanceandsignalsonthe

DI and CLK pins will be ignored (don’t care). When

HOLD is brought high, device operation can resume. The

hold function can be useful when multiple devices are

sharing the same SPI signals. (“See Hold function”)

6

NexFlashTechnologies, Inc.

PRELIMINARYMKP-0010 Rev5 NXSF044G-0405

04/22/05 ©

8M, 16M AND 32M-BIT SERIAL FLASH MEMORY

NX25P80,NX25P16ANDNX25P32

WriteProtect(WP)

WRITE PROTECTION

TheWriteProtect(WP)pincanbeusedtopreventtheStatus

Register from being written. Used in conjunction with the

StatusRegister’sBlockProtect(BP0andBP1)bitsandStatus

Register Protect (SRP) bits, a portion or the entire memory

array can be hardware protected. The WP pin is active low.

Applications that use non-volatile memory must take into

consideration the possibility of noise and other adverse

system conditions that may compromise data integrity. To

addressthisconcerntheNX25P80/16/32providesseveral

means to protect data from inadvertent writes.

1

SPI OPERATION

2

WriteProtectFeatures

• Device resets when Vcc is below threshold.

• Time delay write disable after Power-up.

• Writeenable/disableinstructions.

• Automatic write disable after program and erase.

• Software write protection using Status Register.

• Hardware write protection using Status Register and

WP pin.

• WriteProtectionusingPower-downinstruction.

SPI Modes

The NX25P80/16/32 is accessed through an SPI compat-

iblebusconsistingoffoursignals:SerialClock(CLK),Chip

Select (CS), Serial Data Input (DI) and Serial Data Output

(DO).BothSPIbusoperationModes0(0,0)and3(1,1)are

supported. The primary difference between Mode 0 and

Mode 3 concerns the normal state of the CLK signal when

the SPI bus master is in standby and data is not being

transferred to the Serial Flash. For Mode 0 the CLK signal

isnormallylow.ForMode3theCLKsignalisnormallyhigh.

In either case data input on the DI pin is sampled on the

risingedgeoftheCLK.DataoutputontheDOpinisclocked

out on the falling edge of CLK.

3

4

Upon power-up or at power-down the NX25P80/16/32 will

maintain a reset condition while Vcc is below the threshold

value of V^WI, (See Power-up Timing and Voltage Levels:

Table 7 and Figure 22). While reset, all operations are

disabled and no instructions are recognized. During

power-up and after the Vcc voltage exceeds V^WI, all

programanderaserelatedinstructionsarefurtherdisabled

for a time delay of t^PUW. This includes the Write Enable,

Page Program, Sector Erase, Bulk Erase and the Write

Status Register instructions. Note that the chip select pin

(CS) must track the Vcc supply level at power-up until the

Vcc-min level and t^VSLtime delay is reached. If needed a

pull-up resister on CS can be used to accomplish this.

5

HoldFunction

TheHOLDsignalallowstheNX25P80/16/32operationtobe

paused while it is actively selected (when CS is low). The

holdfunctionmaybeusefulincaseswheretheSPIdataand

clock signals are shared with other devices. For example,

considerifthepagebufferwasonlypartiallywrittenwhena

priorityinterruptrequiresuseoftheSPIbus.Inthiscasethe

hold function can save the state of the instruction and the

data in the buffer so programming can resume where it left

off once the bus is available again.

6

7

After power-up the device is automatically placed in a

write-disabled state with the Status Register Write Enable

Latch (WEL) set to a 0. A Write Enable instruction must be

issuedbeforeaPageProgram,SectorErase,BulkEraseor

Write Status Register instruction will be accepted. After

completing a program, erase or write instruction the Write

Enable Latch (WEL) is automatically cleared to a

write-disabled state of 0.

Toinitiateaholdcondition,thedevicemustbeselectedwith

CS low. A hold condition will activate on the falling edge of

the HOLD signal if the CLK signal is already low. If the CLK

is not already low the hold condition will activate after the

next falling edge of CLK. The hold condition will terminate

on the rising edge of the hold signal if the CLK signal is

alreadylow. IftheCLKisnotalreadylowtheholdcondition

will terminate after the next falling edge of CLK.

8

9

Software controlled write protection is facilitated using the

Write Status Register instruction and setting the Status

Register Protect (SRP) and Block Protect (BP0, BP2) bits.

These Status Register bits allow a portion or all of the

memorytobeconfiguredasreadonly.Usedinconjunction

with the Write Protect (WP) pin, changes to the Status

Registercanbeenabledordisabledunderhardwarecontrol.

See Status Register for further information.

Duringaholdcondition,theSerialDataOutput(DO)ishigh

impedance, and Serial Data Input (DI) and Serial Clock

(CLK) are ignored. The Chip Select (CS) signal should be

keptactive(low)forthefulldurationoftheholdoperationto

avoid resetting the internal logic state of the device.

10

11

12

NexFlashTechnologies, Inc.

7

PRELIMINARY MKP-0010 Rev5 NXSF044G-0405

04/22/05 ©

8M, 16M AND 32M-BIT SERIAL FLASH MEMORY

NX25P80,NX25P16ANDNX25P32

Additionally, the Power-down instruction offers an extra

level of write protection as all instructions are ignored

except for the Release Power-down instruction.

Block Protect Bits (BP2, BP1, BP0)

The Block Protect Bits (BP2, BP1, BP0) are non-volatile

read/writebitsinthestatusregister(S4,S3,S2)thatprovide

Write Protection control and status. Block Protect bits can

besetusingtheWriteStatusRegisterInstruction(seetW in

AC characteristics). All, none or a portion of the memory

arraycanbeprotectedfromProgramandEraseinstructions

(see table 2). The factory default setting for the Block

Protection Bits is 0, none of the array protected. The Block

Protect bits can not be written to if the Status Register

Protect (SRP) bit is set to 1 and the Write Protect (WP) pin

is low.

STATUS REGISTER

TheReadStatusRegisterinstructioncanbeusedtoprovide

status on the availability of the Flash memory array, if the

device is write enabled or disabled, and the state of write

protection. The Write Status Register instruction can be

usedtoconfigurethedeviceswriteprotectionfeatures.See

Figure3.

BUSY

ReservedBits

BUSY is a read only bit in the status register (S0) that is set

to a 1 state when the device is executing a Page Program,

Sector Erase, Bulk Erase or Write Status Register

instruction. During this time the device will ignore further

instructionsexceptfortheReadStatusRegisterinstruction

(see t^W, tPP, tSE and tBE in AC Characteristics). When the

program, erase or write status register instruction has

completed, the BUSY bit will be cleared to a 0 state

indicating the device is ready for further instructions.

Status register bit locations 5 and 6 are reserved for future

use. Current devices will read 0 for these bit locations. It is

recommendedtomaskoutthereservedbitwhentestingthe

Status Register. Doing this will ensure compatibility with

future devices.

StatusRegisterProtect(SRP)

The Status Register Protect (SRP) bit is a non-volatile

read/write bit in the status register (S7) that can be used in

conjunctionwiththeWriteProtect(WP)pintodisablewrites

to the status register. When the SRP bit is set to a 0 state

(factory default) the WP pin has no control over the status

register. When the SRP pin is set to a 1, the Write Status

Register instruction is locked out while the WP pin is low.

When the WP pin is high the Write Status Register

instruction is allowed.

Write Enable Latch (WEL)

Write Enable Latch (WEL) is a read only bit in the status

register(S1)thatissettoa1afterexecutingaWriteEnable

Instruction. The WEL status bit is cleared to a 0 when the

device is write disabled. A write disable state occurs upon

power-up or after any of the following instructions: Write

Disable, Page Program, Sector Erase, Bulk Erase and

Write Status Register.

S7

S6

S5

S4

S3

S2

S1

S0

SRP (RESERVED) BP2

BP1

BP0

WEL BUSY

STATUS REGISTER

PROTECT

BLOCK PROTECT BITS

(NON-VOLATILE)

WRITE ENABLE

LATCH

ERASE OR WRITE

IN PROGRESS

Figure 3. Status Register Bit Locations

8

NexFlashTechnologies, Inc.

PRELIMINARYMKP-0010 Rev5 NXSF044G-0405

04/22/05 ©

8M, 16M AND 32M-BIT SERIAL FLASH MEMORY

NX25P80,NX25P16ANDNX25P32

Table2:StatusRegisterMemoryProtection

Status Register ⁽¹⁾

NX25P32 (32M-bit) Memory Protection

BP2 BP1 BP0

Sector(s)

NONE

Addresses

Portion

Density

NONE

512K-bit

1M-bit

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

NONE

63

3F0000h - 3FFFFFh

3E0000h - 3FFFFFh

3C0000h - 3FFFFFh

380000h - 3FFFFFh

300000h - 3FFFFFh

200000h - 3FFFFFh

000000h - 3FFFFFh

Upper 1/64

Upper 1/32

Upper 1/16

Upper 1/8

Upper 1/4

Upper 1/2

62 and 63

60 thru 63

56 thru 63

48 thru 63

32 thru 63

ALL

2

2M-bit

4M-bit

8M-bit

3

16M-bit

All memory plus Parameter Page

Status Register ⁽¹⁾

BP2 BP1 BP0

NX25P16 (16M-bit) Memory Protection

4

Sector(s)

NONE

Addresses

Portion

Density

NONE

512K-bit

1M-bit

0

1

0

1

0

1

0

1

0

1

0

1

x

NONE

31

1F0000h - 1FFFFFh

1E0000h - 1FFFFFh

1C0000h - 1FFFFFh

180000h - 1FFFFFh

100000h - 1FFFFFh

000000h - 1FFFFFh

Upper 1/32

Upper 1/16

Upper 1/8

Upper 1/4

Upper 1/2

5

30 and 31

28 thru 31

24 thru 31

16 thru 31

ALL

2M-bit

4M-bit

6

8M-bit

All memory plus Parameter Page

7

Status Register ⁽¹⁾

BP2 BP1 BP0

NX25P80 (8M-bit) Memory Protection

Sector(s)

NONE

15

Addresses

Portion

Density

NONE

512K-bit

1M-bit

0

1

0

1

0

1

0

1

0

1

0

1

x

NONE

8

0F0000h - 0FFFFFh

0E0000h - 0FFFFFh

0C0000h - 0FFFFFh

080000h - 0FFFFFh

000000h - 0FFFFFh

Upper 1/16

Upper 1/8

Upper 1/4

Upper 1/2

14 and 15

12 thru 15

8 thru 15

ALL

2M-bit

9

4M-bit

All memory plus Parameter Page

ALL

10

11

12

Notes:

1. x = don't care

NexFlashTechnologies, Inc.

9

PRELIMINARY MKP-0010 Rev5 NXSF044G-0405

04/22/05 ©

8M, 16M AND 32M-BIT SERIAL FLASH MEMORY

NX25P80,NX25P16ANDNX25P32

INSTRUCTIONS

CS. Clock relative timing diagrams for each instruction are

includedinfigures6through19.Allreadinstructionscanbe

completed after any clocked bit. However, all instructions

that Write, Program or Erase must complete on a byte

boundary (CS driven high after a full 8-bits have been

clocked) otherwise the instruction will be terminated. This

feature further protects the device from inadvertent writes.

Additionally, while the memory is being programmed or

erased, or when the Status Register is being written, all

instructionsexceptforReadStatusRegisterwillbeignored

until the program or erase cycle has completed.

The instruction set of the NX25P80/16/32 consists of

thirteen basic instructions that are fully controlled through

theSPIbus(seeTable3).Instructionsareinitiatedwiththe

falling edge of Chip Select (CS). The first byte of data

clockedintotheDIinputprovidestheinstructioncode.Data

on the DI input is sampled on the rising edge of clock with

most significant bit (MSB) first.

Instructions vary in length from a single byte to several

bytes and may be followed by address bytes, data bytes,

dummy bytes (don’t care), and in some cases, a combina-

tion.Instructionsarecompletedwiththerisingedgeofedge

Table 3: Instruction Set ⁽¹⁾

InstructionName

Byte1 Byte2

(Code)

Byte3

Byte4

Byte5

Byte6

n-Bytes

WriteEnable

06h

04h

WriteDisable

(2)

Read Status Register

Write Status Register

ReadData

05h

01h

03h

0Bh

(S7–S0)⁽¹⁾

S7–S0

A23–A16

A15–A8

A7–A0

(D7–D0)

dummy

(Next byte)

(D7–D0)

continuous

Fast Read

(Next Byte)

continuous

PageProgram

02h

A23–A16

A15–A8

A7–A0⁽³⁾(D7-D0)

A7–A0

(D15–D8)

Upto256Bytes

(128Words)⁽⁵⁾

Sector Erase

D8h

C7h

B9h

53h

5Bh

52h

Bulk Erase

Power-down

ReadParameterPage

Fast Read Parameter Page

ProgramParameterPage

Don’tcare Don’tcare A7-A0

Don’tcare Don’tcare A7-A0⁽⁶⁾

D7-D0

dummy

D7-D0

Next Byte

D7-D0

Next Byte

D15-D8

Upto256Bytes

(128Words)

EraseParameterPage

D5h

ABh

(5)

ReleasePower-down

and Device ID⁽⁴⁾

dummy

00h

(ID7-ID0)

Manufacturer/DeviceID⁽⁴⁾

JEDEC ID

90h

9Fh

(M7-M0) (ID7-ID0)

(M7-M0)

(ID15-ID8) (ID7-ID0)

Manufacturer

MemoryType Capacity

Notes:

1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data being read from

the device on the DO pin.

2. The Status Register contents will repeat continuously until /CS terminate the instruction.

3. The Page Program instruction programs in increments of one word (two bytes) at a time. The Program address A23-A16

must be an “Even” Address (A0 must equal 0).

4. See Table 4 for Device ID information

5. The Device ID will repeat continuously until /CS terminates the instruction.

6. A0 must = 0, programming is in word (two byte) increments

10

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Table4:ManufacturerandDeviceIdentification

Manufacturer ID

(M7-M0)

NexFlash

EFh

1

Device ID

Instruction

NX25P80

NX25P16

NX25P32

(ID7-ID0)

ABH, 90h

13h

(ID15-ID0)

9Fh

2014h

2015h

2016h

2

14h

15h

3

Write Enable (06h)

The Write Enable instruction (Figure 4) sets the Write

Enable Latch (WEL) bit in the Status Register to a 1. The

WEL bit must be set prior to every Page Program, Sector

Erase, Bulk Erase and Write Status Register instruction.

The Write Enable instruction is entered by driving CS low,

shiftingtheinstructioncode“06h”intotheDataInput(DI)pin

on the rising edge of CLK, and then driving CS high.

4

CS

5

Mode 3

Mode 0

0

1

2

3

4

5

6

7

CLK

Instruction (06h)

High Impedance

6

DI

DO

7

Figure 4. Write Enable Instruction Sequence Diagram

8

Write Disable (04h)

drivingCShigh.NotethattheWELbitisautomaticallyreset

after Power-up and upon completion of the Write Status

Register, Page Program, Sector Erase, and Bulk Erase

instructions.

The Write Disable instruction (Figure 5) resets the Write

Enable Latch (WEL) bit in the Status Register to a 0. The

Write Disable instruction is entered by driving CS low,

shifting the instruction code “04h” into the DI pin and then

9

10

11

12

CS

0

1

2

3

4

5

6

7

Mode 3

Mode 0

CLK

Instruction (04h)

DI

High Impedance

DO

Figure 5. Write Disable Instruction Sequence Diagram

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Read Status Register (05h)

TheReadStatusRegisterinstructionallowsthe8-bitStatus

Register to be read. The instruction is entered by

drivingCSlowandshiftingtheinstructioncode“05h”intothe

DIpinontherisingedgeofCLK.Thestatusregisterbitsare

thenshiftedoutontheDOpinatthefallingedgeofCLKwith

most significant bit (MSB) first as shown in figure 6. The

Status Register bits are shown in figure 3 and include the

BUSY, WEL, BPO-BP2, and STP bits (see description of

the Status Register earlier in this data sheet).

The Status Register instruction may be used at any time,

evenwhileaProgram,EraseorWriteStatusRegistercycle

is in progress. This allows the BUSY status bit to be

checkedtodeterminewhenthecycleiscompleteandifthe

devicecanacceptanotherinstruction.TheStatusRegister

can be read continuously, as shown in Figure 6. The

instruction is completed by driving CS high.

CS

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23

Mode 3

Mode 0

CLK

DI

Instruction (05h)

Status Register Out

High Impedance

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

DO

7

*

= MSB

*

Figure 6. Read Status Register Instruction Sequence Diagram

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Write Status Register (01h)

The Write Status Register instruction allows the Status

Register to be written. A Write Enable instruction must

previouslyhavebeenexecutedforthedevicetoacceptthe

Write Status Register Instruction (Status Register bit WEL

mustequal1).Oncewriteenabled,theinstructionisentered

by driving CS low, sending the instruction code “01h”, and

then writing the status register data byte as illustrated in

figure 7. The Status Register bits are shown in figure 3 and

described earlier in this data sheet.

Read Status Register instruction may still accessed to

checkthestatusoftheBUSYbit.TheBUSYbitisa1during

the Write Status Register cycle and a 0 when the cycle is

finishedandreadytoacceptotherinstructionsagain. After

theWriteRegistercyclehasstartedtheWriteEnableLatch

(WEL) bit in the Status Register will be cleared to 0.

1

2

The Write Status Register instruction allows the Block

Protectbits(BP2, BP1andBP0)tobesetforprotectingall,

a portion, or none of the memory from erase and program

instructions. Protectedareasbecomeread-only(seetable

2). The Write Status Register instruction also allows the

Status Register Protect bit (SRP) to be set. This bit is used

in conjunction with the Write Protect (WP) pin to disable

writes to the status register. When the SRP bit is set to a 0

state (factory default) the WP pin has no control over the

status register. When the SRP pin is set to a 1, the Write

Status Register instruction is locked out while the WP pin

is low. When the WP pin is high the Write Status Register

instruction is allowed.

Only non-volatile Status Register bits STP, BP2, BP1 and

BP0 (bits 7, 4, 3 and 2) can be written to. All other Status

Registerbitlocationsareread-onlyandwillnotbeaffected

by the Write Status Register instruction.

3

4

TheCSpinmustbedrivenhighaftertheeighthbitofthelast

byte has been latched. If this is not done the Write Status

Registerinstructionwillnotbeexecuted. AfterCS isdriven

high, the self-timed Write Status Register cycle will com-

mence for a time duration of t^W(See AC Characteristics).

While the Write Status Register cycle is in progress, the

5

6

CS

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

Status Register In

Mode 3

Mode 0

7

CLK

Instruction (01h)

8

7

6

5

4

3

2

1

0

DI

*

High Impedance

DO

9

= MSB

*

Figure 7. Write Status Register Instruction Sequence Diagram

10

11

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Read Data (03h)

TheReadDatainstructionallowsonemoredatabytestobe

sequentially read from the memory. The instruction is

initiated by driving the CS pin low and then shifting the

instructioncode“03h” followedbya24-bitaddress(A23-A0)

intotheDIpin.Thecodeandaddressbitsarelatchedonthe

risingedgeoftheCLKpin.Aftertheaddressisreceived,the

data byte of the addressed memory location will be shifted

out on the DO pin at the falling edge of CLK with most

significant bit (MSB) first. The address is automatically

incremented to the next higher address after each byte of

dataisshiftedoutallowingforacontinuousstreamofdata.

This means that the entire memory can be accessed with

a single instruction as long as the clock continues. The

instructioniscompletedbydrivingCShigh.TheReadData

instruction sequence is shown in figure 8. If a Read Data

instructionisissuedwhileanErase,ProgramorWritecycle

isinprocess(BUSY=1)theinstructionisignoredandwillnot

have any effects on the current cycle. The Read Data

instruction allows clock rates from D.C. to a maximum of fR

( see AC Electrical Characteristics).

CS

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31 32 33 34 35 36 37 38 39

Mode 3

Mode 0

CLK

Instruction (03h)

24-Bit Address

DI

23 22 21

3

2

1

0

Data Out 1

Data Out 2

*

High Impedance

7

6

5

4

3

2

1

0

DO

*

= MSB

*

Figure 8. Read Data Instruction Sequence Diagram

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Fast Read (0Bh)

The Fast Read instruction is similar to the Read Data

instructionexceptthatitcanoperateatthehighestpossible

frequency of FR (seeACElectricalCharacteristics). Thisis

accomplished by adding a “dummy” byte after the 24-bit

address as shown in figure 9. The dummy byte allows the

devices internal circuits additional time for setting up the

initial address. The dummy byte data value on the DI pin is

a “don’t care”.

1

2

CS

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31

Mode 3

Mode 0

3

CLK

Instruction (0Bh)

24-Bit Address

23 22 21

DI

3

2

1

0

4

DO

5

CS

6

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

CLK

DI

Dummy Byte

7

6

5

4

3

2

1

0

Data Out 1

Data Out 2

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

DO

8

*

= MSB

*

9

Figure 9. Fast Read Instruction Sequence Diagram

10

11

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Page Program (02h)

ThePagePrograminstructionallowsupto256bytesofdata

to be programmed at previously erased to all 1s (FFh)

memory locations. A Write Enable instruction must be

executed before the device will accept the Page Program

Instruction (Status Register bit WEL must equal 1). The

instructionisinitiatedbydrivingtheCSpinlowthenshifting

theinstructioncode“02h”followedbya24-bitaddress(A23-

A0)andatleasttwodatabytes,intotheDIpin.Becausethe

NX25P80/16/32 programs in increments of one word (two

bytes) at a time the 24-bit address (A23-A0) must be an

even address (A0 must equal 0). The CS pin must be held

lowfortheentirelengthoftheinstructionwhiledataisbeing

senttothedevice.ThePagePrograminstructionsequence

is shown in figure 10.

can be programmed without having any effect on other

byteswithinthesamepage.Ifmorethan256bytesaresent

tothedevicetheaddressingwillwraptothebeginningofthe

page and overwrite previously sent data.

Aswiththewriteanderaseinstructions,theCSpinmustbe

driven high after the eighth bit of the last byte has been

latched.IfthisisnotdonethePagePrograminstructionwill

not be executed. After CS is driven high, the self-timed

PagePrograminstructionwillcommenceforatimeduration

of tpp (See AC Characteristics). While the Page Program

cycle is in progress, the Read Status Register instruction

may still be accessed for checking the status of the BUSY

bit. The BUSY bit is a 1 during the Page Program cycle and

becomesa0whenthecycleisfinishedandthedeviceisready

to accept other instructions again. After the Page Program

cycle has started the Write Enable Latch (WEL) bit in the

StatusRegisterisclearedto0.ThePagePrograminstruction

willnotbeexecutediftheaddressedpageisprotectedbythe

Block Protect (BP2, BP1, BP0) bits (see Table 2).

If an entire 256 byte page is to be programmed, the last

addressbyte(the8leastsignificantaddressbits)shouldbe

setto0. Ifthelastaddressbyteisnotzero, andthenumber

ofclocksexceedtheremainingpagelength,theaddressing

will wrap to the beginning of the page. Less than 256 bytes

CS

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31 32 33 34 35 36 37 38 39

CLK

DI

Instruction (02h)

24-Bit Address

Data Byte 1

**

23 22 21

3

2

1

0

7

6

5

4

3

2

1

0

*

CS

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

CLK

DI

Data Byte 2

Data Byte 3

Data Byte 256

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

*

= MSB

*

** ^{= Address A0 must be 0}

Figure 10. Page Program Instruction Sequence Diagram

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Sector Erase (D8h)

The Sector Erase instruction sets all memory within a

specified sector to the erased state of all 1s (FFh). A Write

Enable instruction must be executed before the device will

accept the Erase Sector Instruction (Status Register bit

WELmustequal1).Theinstructionisinitiatedbydrivingthe

CS pin low and shifting the instruction code “D8h” followed

a24-bitsectoraddress(A23-A0)(seeFigure1).TheSector

Erase instruction sequence is shown in figure 11.

self-timed Sector Erase instruction will commence for a

time duration of t^SE(See AC Characteristics). While the

SectorErasecycleisinprogress,theReadStatusRegister

instruction may still be accessed for checking the status of

the BUSY bit. The BUSY bit is a 1 during the Sector Erase

cycle and becomes a 0 when the cycle is finished and the

deviceisreadytoacceptotherinstructionsagain. Afterthe

Sector Erase cycle has started the Write Enable Latch

(WEL) bit in the Status Register is cleared to 0. The Sector

Eraseinstructionwillnotbeexecutediftheaddressedpage

isprotectedbytheBlockProtect(BP2, BP1, BP0)bits(see

Table2).

1

2

TheCSpinmustbedrivenhighaftertheeighthbitofthelast

byte has been latched. If this is not done the Sector Erase

instructionwillnotbeexecuted. AfterCS isdrivenhigh, the

3

4

CS

0

1

2

3

4

5

6

7

8

9

29 30 31

Mode 3

Mode 0

5

CLK

Instruction (D8h)

24-Bit Address

DI

23 22

2

1

0

6

*

High Impedance

DO

7

= MSB

*

Figure 11. Sector Erase Instruction Sequence Diagram

8

9

10

11

12

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Bulk Erase (C7h)

The Bulk Erase instruction sets all memory within the

device to the erased state of all 1s (FFh). A Write Enable

instruction must be executed before the device will accept

the Bulk Erase Instruction (Status Register bit WEL must

equal1).TheinstructionisinitiatedbydrivingtheCSpinlow

and shifting the instruction code “C7h”. The Bulk Erase

instruction sequence is shown in figure 12.

Erase instruction will commence for a time duration of tBE

(See AC Characteristics). While the Bulk Erase cycle is in

progress, the Read Status Register instruction may still be

accessed to check the status of the BUSY bit. The BUSY

bitisa1duringtheBulkErasecycleandbecomesa0when

finishedandthedeviceisreadytoacceptotherinstructions

again. After the Bulk Erase cycle has started the Write

Enable Latch (WEL) bit in the Status Register is cleared to

0. The Bulk Erase instruction will not be executed if any

pageisprotectedbytheBlockProtect(BP2,BP1,BP0)bits

(see Table 2).

TheCSpinmustbedrivenhighaftertheeighthbithasbeen

latched.IfthisisnotdonetheBulkEraseinstructionwillnot

be executed. After CS is driven high, the self-timed Bulk

CS

0

1

2

3

4

5

6

7

Mode 3

Mode 0

CLK

Instruction (C7)

High Impedance

DI

DO

Figure 12. Bulk Erase Instruction Sequence Diagram

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Power-down (B9h)

Although the standby current during normal operation is

relatively low, standby current can be further reduced with

thePower-downinstruction.Thelowerpowerconsumption

makes the Power-down instruction especially useful for

battery powered applications (See ICC1 and ICC2 in AC

Characteristics). The instruction is initiated by driving the

CSpinlowandshiftingtheinstructioncode“B9h”asshown

in figure 13.

not be executed. After CS is driven high, the power-down

state will entered within the time duration of tDP (See AC

Characteristics). While in the power-down state only the

Release from Power-down / Device ID instruction, which

restoresthedevicetonormaloperation,willberecognized.

All other instructions are ignored. This includes the Read

Status Register instruction, which is always available

during normal operation. Ignoring all but one instruction

makesthePowerDownstateausefulconditionforsecuring

maximumwriteprotection.Thedevicealwayspowers-upin

the normal operation with the standby current of ICC1.

1

2

TheCSpinmustbedrivenhighaftertheeighthbithasbeen

latched. If this is not done the Power-down instruction will

3

4

CS

t

DP

0

1

2

3

4

5

6

7

Mode 3

Mode 0

CLK

5

Instruction (B9h)

DI

High Impedance

6

DO

Stand-by Current

Power-down Current

Figure 13. Deep Power-down Instruction Sequence Diagram

7

8

9

10

11

12

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Release Power-down / Device ID (ABh)

The Release from Power-down / Device ID instruction is a

multi-purpose instruction. It can be used to release the

device from the power-down state, obtain the devices

electronic identification (ID) number or do both.

first as shown in figure 15. The Device ID values for the

NX25P80,NX25P16andNX25P32arelistedinTable4.The

Device ID can be read continuously. The instruction is

completed by driving CS high.

Whenusedonlytoreleasethedevicefromthepower-down

state, the instruction is issued by driving the CS pin low,

shifting the instruction code “ABh” and driving CS high as

shown in figure 14. After the time duration of t^RES1 (SeeAC

Characteristics) the device will resume normal operation

and other instructions will be accepted. The CS pin must

remain high during the t^RES1 time duration.

Whenusedtoreleasethedevicefromthepower-downstate

and obtain the Device ID, the instruction is the same as

previously described, and shown in figure 13, except that

afterCSisdrivenhighitmustremainhighforatimeduration

of t^RES2 (See AC Characteristics). After this time duration

the device will resume normal operation and other instruc-

tions will be accepted.

When used only to obtain the Device ID while not in the

power-down state, the instruction is initiated by driving the

CS pin low and shifting the instruction code “ABh” followed

by 3-dummy bytes. The Device ID bits are then shifted out

on the falling edge of CLK with most significant bit (MSB)

If the Release from Power-down / Device ID instruction is

issuedwhileanErase,ProgramorWritecycleisinprocess

(whenBUSYequals1)theinstructionisignoredandwillnot

have any effects on the current cycle.

CS

t

RES1

0

1

2

3

4

5

6

7

Mode 3

Mode 0

CLK

Instruction (ABh)

DI

High Impedance

DO

Power-down Current

Stand-by Current

Figure14. ReleasePower-downInstructionSequence

CS

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31 32 33 34 35 36 37 38

Mode 3

Mode 0

CLK

Instruction (ABh)

3 Dummy Bytes

tRES2

23 22 21

3

2

1

0

DI

Device ID

*

**

High Impedance

DO

7

6

5

4

3

2

1

0

*

Power-down Current

Stand-by Current

= MSB

*

** ^{= See Table 4}

Figure 15. Release Power-down / Device ID Instruction Sequence Diagram

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Read Manufacturer / Device ID (90h)

turerIDforNexFlash(EFh)andtheDeviceIDareshiftedout

on the falling edge of CLK with most significant bit (MSB)

first as shown in figure 16. The Device ID values for the

NX25P80, NX25P16 and NX25P32 are listed in Table 4. If

the 24-bit address is initially set to 000001h the Device ID

will be read first and then followed by the Manufacturer ID.

TheManufacturerandDeviceIDscanbereadcontinuously,

alternating from one to the other. The instruction is com-

pleted by driving CS high.

TheReadManufacturer/DeviceIDinstructionisanalterna-

tivetotheReleasefromPower-down/DeviceIDinstruction

that provides both the JEDEC assigned manufacturer ID

and the specific device ID.

1

TheReadManufacturer/DeviceIDinstructionisverysimilar

to the Release from Power-down / Device ID instruction.

The instruction is initiated by driving the CS pin low and

shifting the instruction code “90h” followed by a 24-bit

address (A23-A0) of 000000h. After which, the Manufac-

2

3

CS

4

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31

Mode 3

Mode 0

CLK

Instruction (90h)

Address (000000h)

5

23 22 21

3

2

1

0

DI

*

High Impedance

DO

6

CS

32 33 34 35 36 37 38

39 40 41 42 43 44 45 46

7

CLK

DI

8

^{Device ID (}**⁾

Manufacturer ID (EFh

)

7

6

5

4

3

2

1

0

DO

*

9

= MSB

** ^{= See Table 4}

*

10

11

12

Figure 16. Read Manufacturer / Device ID Diagram

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JEDEC ID (9Fh)

For compatibility reasons, the NX25P80/16/32 provides

several instructions to electronically determine the identity

ofthedevice.TheReadJEDECIDinstructioniscompatible

with the JEDEC standard for SPI compatible serial memo-

ries that was adopted in 2003.

ManufacturerIDbyteforNexFlash(EFh)andtwoDeviceID

bytes,MemoryType(ID15-ID8)andCapacity(ID7-ID0)are

then shifted out on the falling edge of CLK with most

significant bit (MSB) first as shown in figure 17. For the

NX25P80,theMemoryTypeis20handtheCapacityis14h.

For the NX25P16, the Memory type is also 20h and the

Capacityis15h.FortheNX25P32,theMemorytypeisalso

20h and the Capacity is 16h.

The instruction is initiated by driving the CS pin low and

shifting the instruction code “9Fh”. The JEDEC assigned

CS

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

Mode 3

Mode 0

CLK

Instruction (9Fh)

High Impedance

DI

Manufacturer ID (EFh)

DO

CS

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

CLK

DI

Memory Type ID15-ID8

Capacity ID7-ID0

DO

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

= MSB

*

Figure 17. Read JEDEC ID

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Read Parameter Page (53h)

(don’t care). The code and address bits are latched on the

risingedgeoftheCLKpin.Aftertheaddressisreceived,the

data byte of the addressed memory location will be shifted

out on the DO pin at the falling edge of CLK with most

significant bit (MSB) first. The address is automatically

incremented to the next higher address after each byte of

dataisshiftedoutallowingforacontinuousstreamofdata.

WhentheendoftheParameterpageisreachedtheaddress

will wrap to the beginning. The Read Parameter Page

instruction is shown in figure 18. If the Read Parameter

PageinstructionisissuedwhileanErase,ProgramorWrite

cycleisinprocess(BUSY=1)theinstructionisignoredand

will not have any effects on the current cycle. The Read

ParameterPageinstructionallowsclockratesfromD.C.to

a maximum of fR (see AC Electrical Characteristics).

The Parameter Page is a 256-byte page of Flash memory

that can be used for storing serial numbers, revision

information and configuration data that might typically be

stored in an additional Serial EEPROM memory. Because

the Parameter Page is relatively small and separate from

thearray,theerasetimeissignificantlyshorterthanthatof

a sector erase (see tPE in AC Electrical Characteristics).

This makes it convenient for more frequent updates.

1

2

The Read Parameter Page instruction allows one or more

bytes of the Parameter page to be read. The instruction is

initiated by driving the CS pin low and then shifting the

instructioncode“53h”followedbya24-bitaddress(A23-A0)

into the DI pin. Only the lower 8 address bits (A7-A0) are

used,the16uppermostaddressbits(A23-A8)areignored

3

4

5

CS

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31 32 33 34 35 36 37 38 39

Mode 3

Mode 0

CLK

6

Instruction (53h)

24-Bit Address

**

DI

23 22 21

3

2

1

0

Data Out 1

Data Out 2

*

7

High Impedance

7

6

5

4

3

2

1

0

DO

*

8

= MSB

*

** ^{= Upper 16-bits of Address are "don't care"}

9

Figure 18. Read Parameter Page Instruction Sequence Diagram

10

11

12

NexFlashTechnologies, Inc.

23

PRELIMINARY MKP-0010 Rev5 NXSF044G-0405

04/22/05 ©

8M, 16M AND 32M-BIT SERIAL FLASH MEMORY

NX25P80,NX25P16ANDNX25P32

Fast Read Parameter Page (5Bh)

The Fast Read Parameter Page instruction is basically the

same as the Read Parameter Page instruction except that

it allows for a faster clock rate to be used. The Fast Read

Parameter Page instruction can opperate at clock rates

from D.C. to a maximum of FR (see AC Electrical Charac-

teristics). This is accomplished by adding a “dummy” byte

afterthe24-bitaddress, asshowninfigure19. Thedummy

byte allows the devices internal circuits additional time for

setting up the initial address. The dummy byte data value

on the DI pin is a “don’t care”.

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31

Mode 3

Mode 0

CLK

Instruction (5Bh)

24-Bit Address

**

DI

23 22 21

3

2

1

0

*

DO

CS

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

CLK

DI

Dummy Byte

7

6

5

4

3

2

1

0

Data Out 1

Data Out 2

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

DO

*

= MSB

*

** ^{= Upper 16-bits of Address are "don't care"}

Figure 19. Fast Read Parameter Page Instruction Sequence Diagram

24

NexFlashTechnologies, Inc.

PRELIMINARYMKP-0010 Rev5 NXSF044G-0405

04/22/05 ©

8M, 16M AND 32M-BIT SERIAL FLASH MEMORY

NX25P80,NX25P16ANDNX25P32

Program Parameter Page (52h)

The Program Parameter Page instruction allows up to 256

bytes (128 words) to be programmed at memory word

locationsthathavebeenpreviouslyerasedtoall1s“FFFFh”

(see Erase Parameter Page instruction). A Write Enable

instruction must be executed before the device will accept

the Program Parameter Page instruction (Status Register

bitWELmustequal1).Theinstructionisinitiatedbydriving

the CS pin low then shifting the instruction code “52h”

followedbya24-bitaddress(A23-A0)andatleasttwodata

bytes,intotheDIpin.Onlythelower8addressbits(A7-A0)

are used, the 16 upper most address bit (A23-A8) are

ignored (don’t care). Because the NX25P80/16/32 pro-

grams in increments of one word (two bytes) at a time, the

address must be an even address (A0 must equal 0). The

CS pin must be held low for the entire length of the

instruction while data is being sent to the device. The

ProgramParameterPageinstructionsequenceisshownin

figure20.

In most applications it is best to read the full 256-byte

contents of the page into a temporary RAM. Data can then

bemodifiedasneededandtheentire256bytescanthenbe

reprogrammed into the Parameter Page at one time.

1

Aswiththewriteanderaseinstructions,theCSpinmustbe

driven high after the eighth bit of the last byte has been

latched. If this is not done the Parameter Page Program

instructionwillnotbeexecuted. AfterCS isdrivenhigh, the

self-timed Page Program instruction will commence for a

time duration of t^PP(See AC Characteristics). While the

Page Program cycle is in progress, the Read Status

Register instruction may still be accessed for checking the

status of the BUSY bit. The BUSY bit is a 1 during the

program cycle and becomes a 0 when the cycle is finished

and the device is ready to accept other instructions again.

AftertheprogramcyclehasstartedtheWriteEnableLatch

(WEL)bitintheStatusRegisterisclearedto0.TheProgram

Parameter Page instruction will not be executed if the

addressed page is protected by the Block Protect (BP2,

BP1, BP0) bits (see Table 2).

2

3

4

Less than 256 bytes (128 words) can be programmed

without having any effect on other data within the page. If

more than 256 bytes are sent to the device the addressing

will wrap to the beginning of the page. If previously written

data bytes are over-written the data will not be valid.

5

6

CS

Mode 3

0

1

2

3

4

5

6

7

8

9

10

7

28 29 30 31 32 33 34 35 36 37 38 39

Mode 0

CLK

DI

Instruction (52h)

24-Bit Address

Data Byte 1

**

8

23 22 21

3

2

1

0

7

6

5

4

3

2

1

0

*

9

CS

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

10

11

12

CLK

DI

Data Byte 2

Data Byte 3

Data Byte 256

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

*

= MSB

*

** ^{= Upper 16-bits of Address are "don't care" Address A0 must be 0}

Figure 20. Parameter Page Program Instruction Sequence Diagram

NexFlashTechnologies, Inc.

25

PRELIMINARY MKP-0010 Rev5 NXSF044G-0405

04/22/05 ©

8M, 16M AND 32M-BIT SERIAL FLASH MEMORY

NX25P80,NX25P16ANDNX25P32

Erase Parameter Page (D5h)

TheEraseParameterPageinstructionsetsall256bytesof

memoryintheParameterPagetotheerasedstateofall1s

(FFh). AWriteEnableinstructionmustbeexecutedbefore

thedevicewillaccepttheEraseParameterPageinstruction

(Status Register bit WEL must equal 1). The instruction is

initiatedbydrivingtheCSpinlowandshiftingtheinstruction

code “D5h”. The Erase Parameter Page instruction se-

quence is shown in figure 21.

self-timed Erase Parameter Page instruction will com-

mence for a time duration of t^PE(See AC Characteristics).

While the Erase Parameter Page cycle is in progress, the

Read Status Register instruction may still be accessed to

checkthestatusoftheBUSYbit.TheBUSYbitisa1during

the Erase Parameter Page cycle and becomes a 0 when

finishedandthedeviceisreadytoacceptotherinstructions

again. After the Erase Parameter Page cycle has started

the Write Enable Latch (WEL) bit in the Status Register is

clearedto0.TheEraseParameterPageinstructionwillnot

be executed if any page is protected by the Block Protect

(BP2, BP1, BP0) bits (see Table 2).

TheCSpinmustbedrivenhighaftertheeighthbithasbeen

latched. If this is not done the Erase Parameter Page

instructionwillnotbeexecuted. After CS isdrivenhigh, the

CS

0

1

2

3

4

5

6

7

Mode 3

Mode 0

CLK

Instruction (D5)

High Impedance

DI

DO

Figure 21. Parameter Page Erase Instruction Sequence Diagram

26

NexFlashTechnologies, Inc.

PRELIMINARYMKP-0010 Rev5 NXSF044G-0405

04/22/05 ©

8M, 16M AND 32M-BIT SERIAL FLASH MEMORY

NX25P80,NX25P16ANDNX25P32

SPECIFICATIONS AND TIMING DIAGRAMS

Table 5. Absolute Maximum Ratings⁽¹⁾

1

Symbol

Vcc

Parameters

Conditions

Range

Unit

V

°C

SupplyVoltage

–0.6 to +4.0

–0.6 to Vcc + 0.4

–65 to +150

See Note 2

VIO

Voltage Applied to Any Pin

StorageTemperature

LeadTemperature

RelativetoGround

TSTG

2

TLEAD

VESD

Electrostatic Discharge Voltage

Human Body Model⁽³⁾

–2000 to +2000

V

Note:

3

1. This device has been designed and tested for the specified operation ranges. Proper operation outside of these levels is

not guaranteed. Exposure beyond absolute maximum ratings (listed above) may cause permanent damage.

2. Compliant with JEDEC Standard J-STD-20C for small body Sn-Pb or Pb-free (Green) assembly and the European directive

on restrictions on hazardous substances (RoHS) 2002/95/EU.

3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 ohms, R2=500 ohms).

4

Table 6. Operating Ranges

Symbol

Parameter

Supply Voltage⁽¹⁾

Conditions

Min

2.7

3.0

Max

3.6

Unit

V

5

Vcc

FR = 33MHz, fR = 20MHz

FR = 50MHz, fR = 33MHz

Industrial

TA

AmbientTemperature,Operating

–40

+85

°C

Note:

6

1. Vcc voltage during Read can operate across the min and max range but should not exceed 10ꢀ of the programming

(erase/write) voltage.

Table 7. Power-up Timing and Write Inhibit Threshold

7

Symbol

Parameter

Min

10

1

Max

Unit

µs

ms

V

(1)

tVSL

VCC(min) to CS Low

Time Delay Before Write Instruction

Write Inhibit Threshold Voltage

(1)

tPUW

10

2

(1)

VWI

1

8

Note:

1. These parameters are characterized only.

9

Vcc

Vcc ^(max)

Program, Erase and Write Instructions are Ignored

CS Must Track Vcc

10

11

12

Vcc (min)

tVSL

Read Instructions

Allowed

Device is Fully

Accessible

Reset

State

VWI

tPUW

Time

Figure 22. Power-up Timing and Voltage Levels

NexFlashTechnologies, Inc.

27

PRELIMINARY MKP-0010 Rev5 NXSF044G-0405

04/22/05 ©

8M, 16M AND 32M-BIT SERIAL FLASH MEMORY

NX25P80,NX25P16ANDNX25P32

Table 8. DC Electrical Characteristics (Preliminary) ⁽¹⁾

Symbol

Parameter

Conditions

VIN = 0V⁽²⁾

Min

Typ

Max

6

8

2

75

5

8

15

20

Unit

pf

µA

mA

(2)

CIN

InputCapacitance

OutputCapacitance

InputLeakage

I/O Leakage

StandbyCurrent

Power-downCurrent

CurrentReadData1MHz⁽³⁾

CurrentReadData20MHz⁽³⁾

CurrentReadData33MHz⁽³⁾

Cout⁽²⁾

VOUT = 0V⁽²⁾

ILI

ILO

ICC1

ICC2

ICC3

CS = VCC, VIN = GND or VCC

C = 0.1VCC / 0.9 VCC DO = Open

25

<1

4

8

9

ICC4

ICC5

ICC6

ICC7

VIL

CurrentPageProgram

Current Write Status Register

CurrentSectorErase

Current Bulk Erase

Input Low Voltage

Input High Voltage

CS = VCC

16

25

20

25

32

25

mA

V

25

–0.5

Vccx0.7

Vccx0.3

Vcc +0.4

0.4

VIH

VOL

VOH

Output Low Voltage

OutputHighVoltage

IOL = 1.6 mA

IOH = –100 µA

VCC–0.2

Notes:

1. See Preliminary Designation.

2. Tested on sample basis and specified through design and characterization data. TA=25° C, Vcc 3V, Frequency 20MHz.

3. Checker Board Pattern.

Table 9. AC Measurement Conditions

Symbol

CL

Parameter

Min

Max

30

5

0.8VCC

0.7VCC

Unit

pF

ns

V

LoadCapacitance

30

TR, TF

VIN

Input Rise and Fall Times

Input Pulse Voltages

Output Timing Reference Voltages

0.2VCC to

0.3VCC to

OUT

V

Note:

1. Output Hi-Z is defined as the point where data out is no longer driven.

Input and Output

Timing Reference Levels

Input Levels

0.8 Vcc

0.7 Vcc

0.3 Vcc

0.2 Vcc

Figure 23. AC Measurement I/O Waveform

28

NexFlashTechnologies, Inc.

PRELIMINARYMKP-0010 Rev5 NXSF044G-0405

04/22/05 ©

8M, 16M AND 32M-BIT SERIAL FLASH MEMORY

NX25P80,NX25P16ANDNX25P32

Table10.ACElectricalCharacteristics(Preliminary)

Symbol

Alt

Description

Min Typ Max Unit

FR

fC

Clock frequency, for Fast Read (0Bh) and all other

instructions except Read Data (03h) 2.7V-3.6V Vcc

3.0V-3.6V Vcc

1

D.C.

33

50

MHz

f^R

Clock freq. Read Data instruction (03h) 2.7V-3.6V Vcc

3.0V-3.6V Vcc

Clock High, Low Time, for Fast Read (0Bh)

and all other instructions except Read Data (03h)

Clock High, Low Time for Read Data instruction

Clock Rise Time peak to peak

Clock Fall Time peak to peak

D.C.

9

20

33

MHz

ns

(1)

2

t^CLH,tCLL

(1)

tCRLH,tCRLL

9

0.1

5

2

ns

V / ns

ns

(2)

tCLCH

3

(2)

tCHCL

tSLCH

tCHSL

tDVCH

tCHDX

tCHSH

tSHCH

tSHSL

tCSS CS Active Setup Time relative to CLK

CS Not Active Hold Time relative to CLK

tDSU Data In Setup Time

4

tDH

Data In Hold Time

CS Active Hold Time relative to CLK [2.7-3.6V / 3.0-3.6V]

CS Not Active Setup Time relative to CLK

5

10 / 8

5

100

5

tCSH CS Deselect Time

(2)

tSHQZ

tDIS

tV

Output Disable Time [2.7-3.6V / 3.0-3.6V]

Clock Low to Output Valid [2.7-3.6V / 3.0-3.6V]

Output Hold Time

HOLD Active Setup Time relative to CLK

HOLD Active Hold Time relative to CLK

HOLD Not Active Setup Time relative to CLK

HOLD Not Active Hold Time relative to CLK

HOLD to Output Low-Z

12 / 10 ns

12 / 8 ns

tCLQV

tCLQX

tHLCH

tCHHH

tHHCH

tCHHL

tHO

0

5

ns

µs

ms

6

7

(2)

tHHQX

tLZ

tHZ

9

(2)

tHLQZ

HOLD to Output High-Z

(4)

tWHSL

Write Protect Setup Time Before CS Low

Write Protect Hold Time After CS High

CSHightoPower-downMode

CS High to Standby Mode without Electronic Signature Read

CS High to Standby Mode with Electronic Signature Read

Write Status Register Cycle Time

20

100

8

(4)

tSHWL

(2)

tDP

3

tRES1⁽²⁾

tRES2⁽²⁾

tW

30

9

17

tPP

Page Program Cycle Time ⁽⁵⁾3.0V-3.6V Vcc

2.7V-3.6V Vcc

3.5

4

7

8

ms

tSE

tBE

Sector Erase Cycle Time

0.6

1.5

s

10

11

12

Bulk Erase Cycle Time 25P80

Bulk Erase Cycle Time 25P16

Bulk Erase Cycle Time 25P32

7

12

25

20

40

80

s

tPE

Parameter Page Erase Cycle Time

100

200

ms

Notes:

1. Clock high + Clock low must be less than or equal to 1/f^C.

2. Value guaranteed by design and/or characterization, not 100ꢀ tested in production.

3. Expressed as a slew-rate.

4. Only applicable as a constraint for a Write Status Register instruction when Sector Protect Bit is set at 1.

5 Maximum Tpp uses worse-case user pattern at 85°C.

NexFlashTechnologies, Inc.

29

PRELIMINARY MKP-0010 Rev5 NXSF044G-0405

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8M, 16M AND 32M-BIT SERIAL FLASH MEMORY

NX25P80,NX25P16ANDNX25P32

CS

tCH

CLK

tCLQV

tCLQX

tCLQV

tCL

tSHQZ

tCLQX

DO

DI

LSB OUT

tQLQH

tQHQL

*

LEAST SIGNIFICANT ADDRESS BIT (LSB) IN

Figure 24. Serial Output Timing

tSHSL

CS

tCHSL

tSLCH

tCHSH

tSHCH

CLK

DI

tDVCH

tCHCL

tCLCH

tCHDX

MSB IN

(High Impedance)

LSB IN

DO

Figure 25. Input Timing

CS

tHLCH

tCHHH

tCHHL

tHLQZ

tHHCH

CLK

DO

tHHQX

DI

HOLD

Figure 26. Hold Timing

30

NexFlashTechnologies, Inc.

PRELIMINARYMKP-0010 Rev5 NXSF044G-0405

04/22/05 ©

8M, 16M AND 32M-BIT SERIAL FLASH MEMORY

NX25P80,NX25P16ANDNX25P32

PACKAGING INFORMATION

8-Pin SOIC 208-mil (Package Code S)

1

2

SEATING PLANE

A2 A

3

y

A1

b

E1

E

e

4

5

1

θ

D

L

C

6

7

Package Dimensions

Millimeters

Inches

Symbol

Min

1.75

0.05

1.70

0.35

0.19

5.18

7.70

5.18

Max

2.16

0.25

1.91

0.48

0.25

5.38

8.10

5.38

Min

Max

8

A

0.069

0.002

0.067

0.014

0.007

0.204

0.303

0.204

0.085

0.010

0.075

0.019

0.010

0.212

0.319

0.212

A1

A2

b

9

C

D

E

10

11

12

Notes:

E1

e

1. Controlling dimensions: inches, unless otherwise

1.27BSC

0.050 BSC

specified.

L

0.50

0^o

0.80

8^o

0.020

0^o

0.031

8^o

2. BSC = Basic lead spacing between centers.

3. Dimensions D and E1 do not include mold flash

protrusions and should be measured from the

bottom of the package.

θ

y

0.10

0.004

NexFlashTechnologies, Inc.

31

PRELIMINARY MKP-0010 Rev5 NXSF044G-0405

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8M, 16M AND 32M-BIT SERIAL FLASH MEMORY

NX25P80,NX25P16ANDNX25P32

16-Pin SOIC 300-mil (Package Code F)

SEATING PLANE

A

E1

E

y

A1

e

b

1

D

L

C

θ

Package Dimensions⁽¹⁾

Millimeters

Inches

Min

Symbol

Min

2.36

0.10

0.33

0.18

10.08

10.01

7.39

Max

2.64

0.30

0.51

0.28

10.49

10.64

7.59

Max

A

0.093

0.004

0.013

0.007

0.397

0.394

0.291

0.104

0.012

0.020

0.011

0.413

0.419

0.299

A1

b

C

D⁽³⁾

E

E1⁽³⁾

e⁽²⁾

L

Notes:

1. Controlling dimensions: inches, unless otherwise

1.27BSC

0.050 BSC

specified.

0.38

0^o

1.27

8^o

0.015

0^o

0.050

8^o

2. BSC = Basic lead spacing between centers.

3. Dimensions D and E1 do not include mold flash

protrusions and should be measured from the

bottom of the package.

θ

y

0.076

0.003

32

NexFlashTechnologies, Inc.

PRELIMINARYMKP-0010 Rev5 NXSF044G-0405

04/22/05 ©

8M, 16M AND 32M-BIT SERIAL FLASH MEMORY

NX25P80,NX25P16ANDNX25P32

PRELIMINARY DESIGNATION

LIFE SUPPORT POLICY

The “Preliminary” designation on a NexFlash data sheet

indicates that the product is not fully characterized. The

specifications are subject to change and are not guaran-

teed. NexFlash or an authorized sales representative

shouldbeconsultedforcurrentinformationbeforeusingthis

product.

NexFlash does not recommend the use of any of it's

products in life support applications where the failure or

malfunctionoftheproductcanreasonablybeexpectedto

cause failure in the life support system or to significantly

affect its safety or effectiveness. Products are not

authorized for use in such applications unless NexFlash

receives written assurances, to it’s satisfaction, that:

1

2

IMPORTANT NOTICE

(a) the risk of injury or damage has been minimized;

(b) the user assumes all such risks; and

NexFlash reserves the right to make changes to the

products contained in this publication in order to improve

design, performance or reliability. NexFlash assumes no

responsibility for the use of any circuits described herein,

conveys no license under any patent or other right, and

makesnorepresentationthatthecircuitsarefreeofpatent

infringement.Chartsandschedulescontainedhereinreflect

representative operating parameters, and may vary

depending upon a user’s specific application. While the

information in this publication has been carefully checked,

NexFlash shall not be liable for any damages arising as a

result of any error or omission.

3

(c) potential liability of NexFlash is adequately

protected under the circumstances.

4

TRADEMARKS

NexFlash is a trademark of NexFlash Technologies, Inc. All

other marks are the property of their respective owner.

5

ORDERING INFORMATION

6

NX 25P xx - V x I - xx..

Company Prefix

NX = NexFlash

7

Product Family

25P = spiFlash Serial Flash Memory

Product Number / Density

8

80 = 8M-bit

16 = 16M-bit

32 = 32M-bit

9

Supply Voltage

V = 2.7V to 3.6V

Package Type

10

11

12

S = 8-pin SOIC 208-mil

F = 16-pin SOIC 300-mil

P = 8-contact MLP 6x5mm*

E = 8-contact MLP 8x6mm*

Temperature Range

I

= Industrial (–40˚C to +85˚C)

Special Options

(Blank) Standard

G = Green Package (Pb-Free plating, die attach and molding)

C = Customer Specification (For factory programming and other custom specifications)

T = Tape and Reel

*

Contact Nexflash for availability of this package

NexFlashTechnologies, Inc.

33

PRELIMINARY MKP-0010 Rev5 NXSF044G-0405

04/22/05 ©

8M, 16M AND 32M-BIT SERIAL FLASH MEMORY

NX25P80,NX25P16ANDNX25P32

Document Revision History

Date

Rev

DescriptionofRevision

03/05/04

03/24/04

A

DocumentWritten

B

MLP metal die pad notification; Under "Package Types," figure 3 and

packaginginformation.

04/19/04

C

Corrected timing diagrams for figure 16 (Read Manufacturer / Device

ID Diagram) and figure 17 (Read JEDEC ID). Added 8x6mm MLP

PackageforNX25P16/32.

05/06/04

06/28/04

D

E

Corrected dimensions in Packaging Information section for 6x5mm and

8x6mm MLP.

Changed 200-mil SOIC reference to 208-mil SOIC. Updated dimen-

sional table for the 208-mil SOIC in the packaging information. Added

208-mil SOIC and removed 5x6mm MLP for NX25P16.

10/07/04

04/22/05

F

Added Parameter Page data to Features, Block Diagram (Figure1),

Status Register Memory Protection(Table 2) and Instruction Set (Table

3) Added Parameter Page timing diagrams (Figures 20, 21, 22 and 23).

Updated FR, tCH AND tPE data in AC Electrical Characteristics (Table 10).

G

Updated AC and DC parameters and package type descriptions.

Removed 8-contact 6x5 and 8x6 MLP packages from document.

Corrected data in Table 3. Updated package dimension symbols for

compliance.

34

NexFlashTechnologies, Inc.

PRELIMINARYMKP-0010 Rev5 NXSF044G-0405

04/22/05 ©

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