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8R45252AKILF

型号：

8R45252AKILF

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

20 页

PDF大小：

274 K

下载PDF手册
FemtoClock® Crystal-to-CML Clock  
Generator  
8R45252I  
Data Sheet  
General Description  
Features  
The 8R45252I is a 3.3V,2.5V CML clock generator designed for  
Ethernet applications. The device synthesizes either a 50MHz,  
62.5MHz, 100MHz, 125MHz, 156.25MHz, 250MHz or 312.5MHz  
clock signal with excellent phase jitter performance. The clock signal  
is distributed to two low-skew differential CML outputs. The device is  
suitable for driving the reference clocks of Ethernet PHYs. The  
device supports 3.3V and 2.5V voltage supply and is packaged in a  
small, lead-free (RoHS 6) 32-lead VFQFN package. The extended  
temperature range supports telecommunication, wireless  
infrastructure and networking end equipment requirements. The  
device is a member of the family of High Performance Clock  
Solutions from IDT.  
• Clock generation of: 50MHz, 62.5MHz, 100MHz, 125MHz,  
156.25MHz, 250MHz and 312.5MHz  
• Two differential CML clock output pairs  
• Crystal interface designed for 25MHz,  
18pF parallel resonant crystal  
• RMS phase jitter @ 125MHz, using a 25MHz crystal  
(1.875MHz – 20MHz): 400fs (typical), 3.3V  
Offset  
Noise Power  
100Hz.................... -102.4 dBc/Hz  
1kHz.................... -119.4 dBc/Hz  
10kHz................... -124.8 dBc/Hz  
100kHz................... -125.7 dBc/Hz  
• LVCMOS interface levels for the control inputs  
• Full 3.3V and 2.5V supply voltage  
• Available in lead-free (RoHS 6) 32 VFQFN package  
• -40°C to 85°C ambient operating temperature  
Block Diagram  
Pin Assignment  
XTAL_IN  
Q0  
nQ0  
0
32 31 30 29 28 27 26 25  
0
OSC  
÷2 (default),  
1
2
3
4
5
6
7
8
nQ0  
nc  
24  
23  
22  
21  
VCO  
490-680  
÷4,  
÷5,  
Phase  
1
Q0  
nc  
f
REF  
Pulldown  
VDD  
REF_SEL  
XTAL_OUT  
REF_CLK  
REF_SEL  
1
nOE  
nc  
FSEL1  
Pulldown  
÷20,  
÷25 (default)  
20 FSEL0  
nc  
19  
nc  
nc  
nc  
Pulldown  
Pullup  
VDD  
nc  
18  
17  
Pulldown, Pulldown  
Pulldown  
9
10 11 12 13 14 15 16  
8R45252I  
32 lead VFQFN  
5.0mm x 5.0mm x 0.925mm package body  
K Package  
Top View  
©2016 Integrated Device Technology, Inc  
1
Revision A January 29, 2016  
8R45252I Data Sheet  
Table 1. Pin Descriptions  
Number  
1, 2  
Name  
nQ0, Q0  
VDD  
Type  
Description  
Output  
Power  
Differential clock output pair. CML interface levels.  
Core supply pins.  
3, 18  
Output enable pin. See Table 3E for function.  
LVCMOS/LVTTL interface levels.  
4
nOE  
nc  
Input  
Pulldown  
5, 6, 7, 8, 9, 16,  
17, 19, 23, 24,  
25, 30, 31, 32  
Unused  
Do not connect.  
10  
11  
VDDA  
Power  
Input  
Analog supply pin.  
PLL bypass pin. See Table 3D for function.  
LVCMOS/LVTTL interface levels.  
nBYPASS  
Pullup  
12  
REF_CLK  
GND  
Input  
Pulldown  
Single-ended reference clock input. LVCMOS/LVTTL interface levels.  
Power supply ground.  
13, 29  
Power  
14,  
15  
XTAL_OUT,  
XTAL_IN  
Input  
Input  
Input  
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.  
Output frequency divider select enable pins. See Table 3C for function.  
LVCMOS/LVTTL interface levels.  
20, 21  
22  
FSEL0, FSEL1  
REF_SEL  
Pulldown  
Pulldown  
Pulldown  
PLL reference clock select pin. See Table 3A for function.  
LVCMOS/LVTTL interface levels.  
PLL feedback divider select pin. See Table 3B for function.  
LVCMOS/LVTTL interface levels.  
26  
FBSEL  
Input  
27, 28  
nQ1, Q1  
Output  
Differential clock output pair. CML interface levels.  
NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.  
Table 2. Pin Characteristics  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
pF  
CIN  
Input Capacitance  
4
RPULLDOWN Input Pulldown Resistor  
RPULLUP Input Pullup Resistor  
51  
51  
k  
k  
©2016 Integrated Device Technology, Inc  
2
Revision A January 29, 2016  
8R45252I Data Sheet  
Function Tables  
Table 3A. PLL Reference Clock Select Function Table  
Input  
REF_SEL  
0 (default)  
1
Operation  
The crystal interface is the selected.  
The REF_CLK input is the selected.  
NOTE: REF_SEL is an asynchronous control.  
Table 3B. PLL Feedback Select Function Table  
Input  
FBSEL  
0 (default)  
1
Operation  
VCO = fREF * 25  
fVCO = fREF * 20  
f
NOTE: FBSEL is an asynchronous control.  
Table 3C. Output Divider Select Function Table  
Input  
Output Frequency fOUT with fREF = 25MHz  
FSEL1  
FSEL0  
Operation  
FBSEL = 0  
312.5MHz  
156.25MHz  
125MHz  
FBSEL = 1  
250MHz  
125MHz  
100MHz  
50MHz  
0 (default)  
0 (default) fOUT = fVCO ÷ 2  
0
1
1
1
0
1
fOUT = fVCO ÷ 4  
fOUT = fVCO ÷ 5  
fOUT = fVCO ÷ 10  
62.5MHz  
NOTE: FSEL[1:0] are asynchronous controls.  
Table 3D. PLL nBYPASS Function Table  
Input  
nBYPASS  
Operation  
PLL is bypassed. The reference frequency fREF is divided by the selected  
output divider. AC specifications do not apply in PLL bypass mode.  
0
PLL is enabled. The reference frequency fREF is multiplied by the selected  
feedback divider and then divided by the selected output divider.  
1 (default)  
NOTE: nBYPASS is an asynchronous control.  
Table 3E. Output Enable Function Table  
Input  
nOE  
0 (default)  
1
Operation  
Outputs enabled.  
Outputs disabled (high-impedance).  
NOTE: nOE is an asynchronous control.  
©2016 Integrated Device Technology, Inc  
3
Revision A January 29, 2016  
8R45252I Data Sheet  
Absolute Maximum Ratings  
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.  
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond  
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for  
extended periods may affect product reliability.  
Item  
Rating  
Supply Voltage, VDD  
Inputs, VI  
4.6V  
-0.5V to VDD + 0.5V  
Outputs, IO  
Continuous Current  
Surge Current  
10mA  
15mA  
Package Thermal Impedance, JA  
43.4°C/W (0 mps)  
Storage Temperature, TSTG  
-65C to 150C  
DC Electrical Characteristics  
Table 4A. Power Supply DC Characteristics, VDD = 3.3V 5%, TA = -40°C to 85°C  
Symbol Parameter  
Test Conditions  
Minimum  
3.135  
Typical  
3.3  
Maximum  
3.465  
VDD  
Units  
V
VDD  
VDDA  
IDD  
Core Supply Voltage  
Analog Supply Voltage  
Power Supply Current  
Analog Supply Current  
VDD – 0.12  
3.3  
V
88  
mA  
mA  
IDDA  
12  
Table 4B. Power Supply DC Characteristics, VDD = 2.5V 5%, TA = -40°C to 85°C  
Symbol Parameter  
Test Conditions  
Minimum  
2.375  
Typical  
2.5  
Maximum  
2.625  
VDD  
Units  
V
VDD  
VDDA  
IDD  
Core Supply Voltage  
Analog Supply Voltage  
Power Supply Current  
Analog Supply Current  
VDD – 0.11  
2.5  
V
84  
mA  
mA  
IDDA  
11  
©2016 Integrated Device Technology, Inc  
4
Revision A January 29, 2016  
8R45252I Data Sheet  
Table 4C. LVCMOS/LVTTL Input DC Characteristics, VDD = 3.3V 5% or 2.5V 5%, TA = -40°C to 85°C  
Symbol Parameter  
Test Conditions  
VDD = 3.3V  
VDD = 2.5V  
VDD = 3.3V  
VDD = 2.5V  
Minimum  
Typical  
Maximum  
VDD + 0.3  
VDD + 0.3  
0.8  
Units  
2
V
V
V
V
VIH Input High Voltage  
1.7  
-0.3  
-0.3  
VIL  
Input Low Voltage  
FBSEL, nOE, FSEL[1:0],  
0.7  
VDD = VIN = 3.465V  
VDD = VIN = 3.465V  
150  
5
µA  
µA  
µA  
Input  
High Current  
REF_SEL, REF_CLK  
IIH  
nBYPASS  
FBSEL, nOE, FSEL[1:0],  
REF_SEL, REF_CLK  
VDD = 3.465V or 2.625V,  
VIN = 0V  
-5  
Input  
Low Current  
IIL  
VDD = 3.465V or 2.625V,  
VIN = 0V  
nBYPASS  
-150  
µA  
Table 4D. CML DC Characteristics, VDD = 3.3V 5% or 2.5V 5%, TA = -40°C to 85°C  
Symbol  
VOH  
Parameter  
Test Conditions  
Minimum  
VDD - 0.02  
325  
Typical  
VDD - 0.01  
400  
Maximum  
VDD  
Units  
V
Output High Voltage  
Output Voltage Swing  
VOUT  
600  
mV  
mV  
VDIFF_OUT Differential Output Voltage Swing  
650  
800  
1200  
Table 5. Crystal Characteristics  
Parameter  
Test Conditions  
Minimum  
Typical  
Fundamental  
25  
Maximum  
Units  
Mode of Oscillation  
Frequency  
MHz  
Equivalent Series Resistance (ESR)  
Shunt Capacitance  
50  
7
pF  
©2016 Integrated Device Technology, Inc  
5
Revision A January 29, 2016  
8R45252I Data Sheet  
AC Characteristics  
Table 6A. AC Characteristics, VDD = 3.3V 5%, TA = -40°C to 85°C  
Symbol Parameter  
Test Conditions  
Minimum  
Typical  
312.5  
156.25  
125  
Maximum  
Units  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
ps  
FBSEL = 0, FSEL[1:0] = 00  
FBSEL = 0, FSEL[1:0] = 01  
FBSEL = 0, FSEL[1:0] = 10  
FBSEL = 0, FSEL[1:0] = 11  
FBSEL = 1, FSEL[1:0] = 00  
FBSEL = 1, FSEL[1:0] = 01  
FBSEL = 1, FSEL[1:0] = 10  
FBSEL = 1, FSEL[1:0] = 11  
62.5  
250  
fOUT  
Output Frequency; NOTE 1  
125  
100  
50  
tsk(o)  
Output Skew; NOTE 1, 2, 3  
60  
FSEL = 0, 125MHz,  
Integration Range: 1.875MHz – 20MHz  
400  
408  
fs  
fs  
RMS Phase Jitter (Random);  
NOTE 4  
tjit(Ø)  
FSEL = 0, 156.25MHz,  
Integration Range: 1.875MHz – 20MHz  
tR / tF  
odc  
Output Rise/Fall Time  
Output Duty Cycle  
20% to 80%  
300  
48  
850  
52  
ps  
%
%
FBSEL[1:0] 10  
FBSEL[1:0] = 10  
46  
54  
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device  
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal  
equilibrium has been reached under these conditions.  
NOTE 1: fREF = 25 MHz.  
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential  
cross points.  
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.  
NOTE 4: Please refer to the phase noise plots.  
Table 6B. AC Characteristics, VDD = 2.5V 5%, TA = -40°C to 85°C  
Symbol Parameter  
Test Conditions  
Minimum  
Typical  
312.5  
156.25  
125  
Maximum  
Units  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
ps  
FBSEL = 0, FSEL[1:0] = 00  
FBSEL = 0, FSEL[1:0] = 01  
FBSEL = 0, FSEL[1:0] = 10  
FBSEL = 0, FSEL[1:0] = 11  
FBSEL = 1, FSEL[1:0] = 00  
FBSEL = 1, FSEL[1:0] = 01  
FBSEL = 1, FSEL[1:0] = 10  
FBSEL = 1, FSEL[1:0] = 11  
62.5  
250  
fOUT  
Output Frequency; NOTE 1  
125  
100  
50  
tsk(o)  
Output Skew; NOTE 1, 2, 3  
60  
FSEL = 0, 125MHz,  
Integration Range: 1.875MHz – 20MHz  
406  
441  
fs  
fs  
RMS Phase Jitter (Random);  
NOTE 4  
tjit(Ø)  
FSEL = 0, 156.25MHz,  
Integration Range: 1.875MHz – 20MHz  
tR / tF  
odc  
Output Rise/Fall Time  
Output Duty Cycle  
20% to 80%  
300  
48  
850  
52  
ps  
%
%
FBSEL[1:0] 10  
FBSEL[1:0] = 10  
46  
54  
For NOTES see Table 6A above.  
©2016 Integrated Device Technology, Inc  
6
Revision A January 29, 2016  
8R45252I Data Sheet  
Typical Phase Noise at 125MHz (3.3V)  
Offset Frequency (Hz)  
©2016 Integrated Device Technology, Inc  
7
Revision A January 29, 2016  
8R45252I Data Sheet  
Typical Phase Noise at 125MHz (2.5V)  
Offset Frequency (Hz)  
©2016 Integrated Device Technology, Inc  
8
Revision A January 29, 2016  
8R45252I Data Sheet  
Parameter Measurement Information  
0V  
SCOPE  
SCOPE  
0V  
Qx  
Qx  
VDD  
Power  
Supply  
Power  
Supply  
VDD  
CML Driver  
CML Driver  
GND  
GND  
-2.5V 5%  
nQx  
-3.3V 5%  
3.3V CML Output Load AC Test Circuit  
2.5V CML Output Load AC Test Circuit  
nQx  
Qx  
nQy  
Qy  
Output Skew  
RMS Phase Jitter  
nQ0, nQ1  
Q0, Q1  
tPW  
VDIFF_OUT  
VOUT  
tPERIOD  
tPW  
odc =  
x 100%  
Differential Voltage Swing = 2 x Single-ended VIN  
tPERIOD  
Differential Output Voltage Swing  
Output Duty Cycle/Pulse Width/Period  
©2016 Integrated Device Technology, Inc  
9
Revision A January 29, 2016  
8R45252I Data Sheet  
Application Information  
Recommendations for Unused Input and Output Pins  
Inputs:  
Outputs:  
LVCMOS Control Pins  
CML Outputs  
All control pins have internal pullups and pulldowns; additional  
resistance is not required but can be added for additional  
protection. A 1kresistor can be used.  
All unused CML outputs can be left floating. We recommend that  
there is no trace attached. Both sides of the differential output pair  
should either be left floating or terminated.  
Crystal Inputs  
For applications not requiring the use of the crystal oscillator input,  
both XTAL_IN and XTAL_OUT can be left floating. Though not  
required, but for additional protection, a 1kresistor can be tied  
from XTAL_IN to ground.  
REF_CLK Input  
For applications not requiring the use of the reference clock,  
it can be left floating. Though not required, but for additional  
protection, a 1kresistor can be tied from the REF_CLK to ground.  
©2016 Integrated Device Technology, Inc  
10  
Revision A January 29, 2016  
8R45252I Data Sheet  
Schematic Example  
Figure 1 shows an example 8R45252I application schematic. Refer  
to the pin description and functional tables in the data sheet to  
ensure the logic control inputs are properly set. Input and output  
terminations shown are intended as examples only and may not  
represent the exact user configuration. Resistor R11 is the specific  
resistor value used to match the 17 ohm output impedance  
LVCMOS driver to the 50 ohm transmission line driving REF_CLK.  
Load caps C1 and C2 are required for frequency accuracy, but  
these may be adjusted for different board layouts. As with any high  
speed analog circuitry, the power supply pins are vulnerable to  
random noise. To achieve optimum jitter performance, power supply  
isolation is required.  
recommended that the 0.1uF capacitors be placed on the device  
side of the PCB as close to the power pins as possible. This is  
represented by the placement of these capacitors in the schematic.  
If space is limited, the ferrite bead, 10uf and 0.1uF capacitors  
connected to 3.3V can be placed on the opposite side of the PCB. If  
space permits, place all filter components on the device side of the  
board. Power supply filter recommendations are a general guideline  
to be used for reducing external noise from coupling into the  
devices. The filter performance is designed for a wide range of  
noise frequencies. This low-pass filter starts to attenuate noise at  
approximately 10kHz. If a specific frequency noise component is  
known, such as switching power supplies frequencies, it is  
recommended that component values be adjusted and if required,  
additional filtering be added. Additionally, good general design  
practices for power plane voltage stability suggests adding bulk  
capacitance in the local area of all devices.  
The 8R45252I provides separate VDD and VDDA power supplies to  
isolate any high switching noise from coupling into the internal PLL.  
In order to achieve the best possible filtering, it is highly  
3. 3V  
10 uF  
C6  
FB 2  
2
1
0. 1u F  
C3  
VDD_3  
R1 1 0  
3 .3 V  
C10  
BLM1 8BB2 21S N1  
FB1  
C4  
0 .1u F  
C9  
0 .1 uF  
1
2
VDD_ 18  
U1  
1 0uF  
BLM1 8BB2 21S N1  
C8  
C7  
C5  
0. 1uF  
10 uF  
0. 1uF  
4
5
6
7
8
9
16  
17  
19  
23  
24  
25  
30  
31  
nOE  
nBY PA SS  
FSEL0  
FSEL1  
REF_S EL  
FBSEL  
nOE  
nBY PA SS  
FSEL0  
FSEL1  
REF_S EL  
FBSEL  
nc  
nc  
nc  
nc  
nc  
nc  
nc  
nc  
nc  
nc  
nc  
1 1  
2 0  
2 1  
2 2  
2 6  
+3. 3V  
R6  
5 0  
R7  
50  
1 5  
1 4  
Zo  
Zo  
=
=
5 0 Ohm  
5 0 Ohm  
XTAL _I N  
+
-
2 5MHz (18 pf)  
X1  
XTAL _O U T  
nc  
nc  
nc  
32  
C1  
27 pF  
C2  
27 pF  
2
1
Q0  
3 .3 V  
+3 .3 V C ML Rece iv er  
nQ0  
1 2  
REF_CL K  
28  
27  
R11  
Zo  
=
5 0 O hm  
+3. 3V  
Q1  
nQ1  
33  
L VCMOS, Ro=1 7 ohm s  
R4  
5 0  
R5  
50  
Zo  
Zo  
=
=
5 0 Ohm  
5 0 Ohm  
+
Logic Control Input Examples  
-
Set Logic  
Input to '1'  
Set Logic  
V CC  
VCC  
Input to '0'  
+3 .3 V C ML Rece iv er  
RU 1  
1 K  
RU2  
Not Ins ta ll  
To Logic  
Input  
pins  
To Logic  
Input  
pins  
RD 1  
No t I nst all  
RD2  
1K  
Figure 1. 8R45252I Application Schematic  
©2016 Integrated Device Technology, Inc  
11  
Revision A January 29, 2016  
8R45252I Data Sheet  
Overdriving the XTAL Interface  
The XTAL_IN input can be overdriven by an LVCMOS driver or by  
one side of a differential driver through an AC coupling capacitor.  
The XTAL_OUT pin can be left floating. The amplitude of the input  
signal should be between 500mV and 1.8V and the slew rate should  
not be less than 0.2V/nS. For 3.3V LVCMOS inputs, the amplitude  
must be reduced from full swing to at least half the swing in order to  
prevent signal interference with the power rail and to reduce internal  
noise. Figure 2A shows an example of the interface diagram for a  
high speed 3.3V LVCMOS driver. This configuration requires that  
the sum of the output impedance of the driver (Ro) and the series  
resistance (Rs) equals the transmission line impedance. In addition,  
matched termination at the crystal input will attenuate the signal in  
half. This can be done in one of two ways. First, R1 and R2 in  
parallel should equal the transmission line impedance. For most  
50applications, R1 and R2 can be 100. This can also be  
accomplished by removing R1 and changing R2 to 50. The values  
of the resistors can be increased to reduce the loading for a slower  
and weaker LVCMOS driver. Figure 2B shows an example of the  
interface diagram for an LVPECL driver. This is a standard LVPECL  
termination with one side of the driver feeding the XTAL_IN input. It  
is recommended that all components in the schematics be placed in  
the layout. Though some components might not be used, they can  
be utilized for debugging purposes. The datasheet specifications  
are characterized and guaranteed by using a quartz crystal as the  
input.  
VCC  
XTAL_OUT  
R1  
100  
C1  
Rs  
Zo = 50 ohms  
Ro  
XTAL_IN  
.1uf  
R2  
100  
Zo = Ro + Rs  
LVCMOS Driver  
Figure 2A. General Diagram for LVCMOS Driver to XTAL Input Interface  
XTAL_OUT  
C2  
Zo = 50 ohms  
XTAL_I N  
.1uf  
Zo = 50 ohms  
R1  
50  
R2  
50  
LVPECL Driver  
R3  
50  
Figure 2B. General Diagram for LVPECL Driver to XTAL Input Interface  
©2016 Integrated Device Technology, Inc  
12  
Revision A January 29, 2016  
8R45252I Data Sheet  
VFQFN EPAD Thermal Release Path  
In order to maximize both the removal of heat from the package and  
the electrical performance, a land pattern must be incorporated on  
the Printed Circuit Board (PCB) within the footprint of the package  
corresponding to the exposed metal pad or exposed heat slug on the  
package, as shown in Figure 3. The solderable area on the PCB, as  
defined by the solder mask, should be at least the same size/shape  
as the exposed pad/slug area on the package to maximize the  
thermal/electrical performance. Sufficient clearance should be  
designed on the PCB between the outer edges of the land pattern  
and the inner edges of pad pattern for the leads to avoid any shorts.  
electrical conductivity requirements. Thus, thermal and electrical  
analysis and/or testing are recommended to determine the minimum  
number needed. Maximum thermal and electrical performance is  
achieved when an array of vias is incorporated in the land pattern. It  
is recommended to use as many vias connected to ground as  
possible. It is also recommended that the via diameter should be 12  
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is  
desirable to avoid any solder wicking inside the via during the  
soldering process which may result in voids in solder between the  
exposed pad/slug and the thermal land. Precautions should be taken  
to eliminate any solder voids between the exposed heat slug and the  
land pattern. Note: These recommendations are to be used as a  
guideline only. For further information, please refer to the Application  
Note on the Surface Mount Assembly of Amkor’s  
While the land pattern on the PCB provides a means of heat transfer  
and electrical grounding from the package to the board through a  
solder joint, thermal vias are necessary to effectively conduct from  
the surface of the PCB to the ground plane(s). The land pattern must  
be connected to ground through these vias. The vias act as “heat  
pipes”. The number of vias (i.e. “heat pipes”) are application specific  
and dependent upon the package power dissipation as well as  
Thermally/Electrically Enhance Leadframe Base Package, Amkor  
Technology.  
SOLDER  
PIN  
SOLDER  
EXPOSED HEAT SLUG  
PIN  
PIN PAD  
GROUND PLANE  
LAND PATTERN  
(GROUND PAD)  
PIN PAD  
THERMAL VIA  
Figure 3. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)  
©2016 Integrated Device Technology, Inc  
13  
Revision A January 29, 2016  
8R45252I Data Sheet  
Power Considerations  
This section provides information on power dissipation and junction temperature for the 8R45252I.  
Equations and example calculations are also provided.  
1. Power Dissipation.  
The total power dissipation for the 8R45252I is the sum of the core power plus the power dissipated in the load(s).  
The following is the power dissipation for VDD= 3.3V + 5% = 3.465V, which gives worst case results.  
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.  
•
•
Power (core)MAX = VDD_MAX * (IDD + IDDA) = 3.465V * (88mA + 12mA) = 346.5mW  
Power (outputs)MAX = 35.76mW/Loaded Output pair  
If all outputs are loaded, the total power is 2 * 35.76mW = 71.52mW  
Total Power_MAX (3.465V, with all outputs switching) = 346.5mW + 71.52mW = 418.02mW  
2. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The  
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond  
wire and bond pad temperature remains below 125°C.  
The equation for Tj is as follows: Tj = JA * Pd_total + TA  
Tj = Junction Temperature  
JA = Junction-to-Ambient Thermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = Ambient Temperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and  
a multi-layer board, the appropriate value is 43.4°C/W per Table 7 below.  
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:  
85°C + 0.418W * 43.4°C/W = 103°C. This is well below the limit of 125°C.  
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of  
board (multi-layer).  
Table 7. Thermal Resistance JA for 32 Lead VFQFN, Forced Convection  
JA by Velocity  
Meters per Second  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard Test Boards  
43.4°C/W  
37.9°C/W  
34.0°C/W  
©2016 Integrated Device Technology, Inc  
14  
Revision A January 29, 2016  
8R45252I Data Sheet  
3. Calculations and Equations.  
The purpose of this section is to calculate the power dissipation for the CML driver output pair. The CML output circuit and termination are  
shown in Figure 4.  
VDD  
RL1  
50  
RL2  
50  
Q
nQ  
V_output  
Q1  
Q2  
I_load  
IC  
Figure 4. CML Driver (without built-in 50pullup) Circuit and Termination  
To calculate worst case power dissipation into the load, use the following equations:  
Power dissipation when the output driver is logic LOW:  
Pd_L = I Load * V Output  
= (VOUT_MAX /RL) * (VDD_MAX – VOUT_MAX  
= (600mV/50) * (3.465V – 600mV)  
= 34.38mW  
)
Power dissipation when the output driver is logic HIGH:  
Pd_H = I Load * V Output  
= (0.02V/50) * (3.465V – 0.02V)  
= 1.38mW  
Total Power Dissipation per output pair = Pd_H + Pd_L = 35.76mW  
©2016 Integrated Device Technology, Inc  
15  
Revision A January 29, 2016  
8R45252I Data Sheet  
Reliability Information  
Table 8. JA vs. Air Flow Table for a 32 VFQFN  
JA vs. Air Flow  
Meters per Second  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard Test Boards  
43.4°C/W  
37.9°C/W  
34.0°C/W  
Transistor Count  
The transistor count for the 8R45252I is: 3064  
©2016 Integrated Device Technology, Inc  
16  
Revision A January 29, 2016  
8R45252I Data Sheet  
Package Outline and Package Dimensions  
Package Outline - K Suffix for VFQFN Packages  
(Ref.)  
N & N  
Seating Plane  
(N -1)x e  
(Ref.)  
Even  
A1  
IndexArea  
L
A3  
E2  
e
2
N
N
(Ty p.)  
If N & N  
are Even  
Anvil  
Singulation  
1
2
(N -1)x e  
(Re f.)  
E2  
2
TopView  
b
e
Thermal  
Base  
A
(Ref.)  
D2  
2
D
N & N  
Odd  
0. 08  
C
Chamfer 4x  
0.6 x 0.6 max  
OPTIONAL  
D2  
C
NOTE: The following package mechanical drawing is a generic  
drawing that applies to any pin count VFQFN package. This drawing  
is not intended to convey the actual pin count or pin layout of this  
device. The pin count and pinout are shown on the front page. The  
package dimensions are in Table 9.  
Table 9. Package Dimensions  
JEDEC Variation: VHHD-2/-4  
All Dimensions in Millimeters  
Symbol  
Minimum  
Nominal  
Maximum  
N
32  
A
0.80  
0
1.00  
0.05  
A1  
A3  
0.25 Ref.  
0.25  
b
ND & NE  
D & E  
D2 & E2  
e
0.18  
0.30  
8
5.00 Basic  
3.0  
3.3  
0.50 Basic  
0.40  
L
0.30  
0.50  
Reference Document: JEDEC Publication 95, MO-220  
©2016 Integrated Device Technology, Inc  
17  
Revision A January 29, 2016  
8R45252I Data Sheet  
Table 10. Ordering Information  
Part/Order Number  
8R45252AKILF  
Marking  
Package  
Shipping Packaging  
Tray  
Temperature  
-40C to 85C  
-40C to 85C  
ICSR5252AIL  
ICSR5252AIL  
Lead-Free, 32 Lead VFQFN  
Lead-Free, 32 Lead VFQFN  
8R45252AKILFT  
2500 Tape & Reel  
©2016 Integrated Device Technology, Inc  
18  
Revision A January 29, 2016  
8R45252I Data Sheet  
Revision History  
Revision Date  
Description of Change  
▪ Removed ICS from part numbers where needed.  
January 29, 2016  
▪ Ordering Information - removed ICS from Part/Order number. Deleted LF note below table.  
▪ Updated header and footer.  
©2016 Integrated Device Technology, Inc  
19  
Revision A January 29, 2016  
8R45252I Data Sheet  
Corporate Headquarters  
6024 Silver Creek Valley Road  
San Jose, CA 95138 USA  
www.IDT.com  
Sales  
Tech Support  
1-800-345-7015 or 408-284-8200  
Fax: 408-284-2775  
www.IDT.com/go/sales  
www.idt.com/go/support  
DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications  
and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein  
is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability,  
or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.  
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably  
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of  
IDT or their respective third party owners.  
For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary.  
Copyright ©2016 Integrated Device Technology, Inc. All rights reserved.  
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