IX2204
INTEGRATED
C
IRCUITS
D
IVISION
3 Functional Description
3.1 Input
This blanking time starts when INA transitions from
low to high.
The INA and INB inputs are TTL compatible and must
be referenced to GND.
The desaturation two-step turn off is slightly different
when MODE is connected to VHA for stack-mode
IGBT drive. When the DESAT voltage exceeds 1.4V,
OUTHA and OUTLB are turned on, tristating the IGBT.
3.2 Mode
The MODE input determines how the desaturation
protection and Under-Voltage Lock Out (UVLO)
protection circuitry controls the OUTHA, OUTLA,
OUTHB and OUTLB outputs. For parallel-mode IGBT
drive, MODE should be connected to GND (see 4.1).
For driving IGBTs that require higher gate drive
current than the IX2204 can provide, the IX2204 can
be used to control external drive transistors. In this
stacked configuration, the external drive transistors
constitute an inverting stage, and MODE should be
connected to VHA for proper desaturation protection
and UVLO operation (see 4.3).
After the t
time, OUTHA and OUTLB are
TRISTATE
turned off, and OUTHB is turned on, which in
conjunction with the external drive transistor quickly
turns off the IGBT. When MODE is connected to VHA,
the blanking time starts when INA transitions from
high to low.
The desaturation protection circuit cannot be used
when the IX2204 is used to drive two separate IGBTs
(direct IGBT drive, see 4.2). When driving two
separate IGBTs, the DESAT, TRISTATE, MODE, and
BLANK pins should all be connected to GND.
3.3 Desaturation Protection
3.4 Under-Voltage Protection
The desaturation protection circuit ensures the
protection of an external IGBT in the event of an
over-current situation. When the voltage at DESAT
exceeds 1.4V (typically) and MODE is connected to
GND, OUTLA and OUTLB are driven low in a two-step
process. First OUTLA, OUTHA, OUTLB and OUTHB
are all turned off (high impedance). Then after a
The Under Voltage Lock Out (UVLO) circuit protects
the IGBT from insufficient gate voltage. The UVLO
circuit monitors the VHA supply voltage. If MODE is
connected to GND and VHA is below the UVLO+
threshold, OUTHA and OUTHB are both turned-off
(high impedance), and both OUTLA and OUTLB are
both turned on (pulled low). If VHA is below the
UVLO+ threshold and MODE is connected to VHA,
OUTHA and OUTHB are both are turned on, and
OUTLA and OUTLB are both turned off.
programmable time (t
), both OUTLA and
TRISTATE
OUTLB are turned on (driven low), which quickly turns
off the IGBT. This two-step action avoids both
dangerous over-voltages across the IGBT and
reverse-bias SOA problems, especially during a short
circuit turn-off. The time that all the outputs are in
tristate is set by an internal current source and an
external capacitor (CTRISTATE ) that is connected to
the TRISTATE pin. The tristate time is approximately:
Table 2: Output States with VHA < UVLO+
Mode
OUTHA
OUTLA
OUTHB
OUTLB
GND
VHA
Z
1
0
Z
Z
1
0
Z
t
= 8750 • C
TRISTATE
3.5 Fault Output
TRISTATE
The FAULT output is pulled low during a desaturation
event, or when VHA is below UVLO+.
The desaturation circuit is disabled for a fixed blanking
time to avoid detecting a false desaturation event
during IGBT turn-on, thus allowing enough time for
IGBT saturation. This blanking time is set by an
internal current source and an external capacitor,
3.6 Outputs
The output stages are able to source 2A, and sink 4A.
Separated sink and source outputs allow independent
gate charge and discharge control. For higher gate
drive applications, the source and sink outputs can be
paralleled to source 4A, and sink 8A.
C
. The blanking time is approximately:
BLK
t
= 8750 • C
BLK
BLK
R03
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