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XWM8728EDS

型号:

XWM8728EDS

描述:

24位, 192kHz的立体声DAC,具有音量控制和DSD支持[ 24-bit, 192kHz Stereo DAC with Volume Control and DSD Support ]

品牌:

WOLFSON[ WOLFSON MICROELECTRONICS PLC ]

页数:

28 页

PDF大小:

267 K

WM8728  
24-bit, 192kHz Stereo DAC  
with Volume Control and DSD Support  
Product Preview, Rev 1.2, April 2001  
DESCRIPTION  
FEATURES  
Stereo DAC with 24 bit PCM or single bit DSD operation  
Audio Performance  
The WM8728 is a high performance stereo DAC designed  
for audio applications such as DVD, home theatre systems,  
and digital TV. The WM8728 supports PCM data input word  
lengths from 16 to 32-bits and sampling rates up to 192kHz.  
Alternatively the WM8728 can operate in DSD compatible  
mode where a 64x bitstream is input for each channel. The  
-
106dB SNR (‘A’ weighted @ 48kHz) DAC  
-97dB THD  
-
DAC Sampling Frequency: 8kHz - 192kHz  
2 or 3-Wire Serial Control Interface or Hardware Control  
Programmable Audio Data Interface Modes  
WM8728 consists of  
a serial interface port, digital  
interpolation filters, multi-bit sigma delta modulators and  
stereo DAC in a small 20-pin SSOP package. The WM8728  
also includes a digitally controllable mute and attenuate  
function for each channel.  
-
I2S, Left, Right Justified, DSP  
-
16/20/24/32 bit Word Lengths  
Independent Digital Volume Control on Each Channel with  
127.5dB Range in 0.5dB Steps  
The WM8728 supports a variety of connection schemes for  
audio DAC control. The 2 or 3-wire MPU serial port provides  
access to a wide range of features including on-chip mute,  
attenuation and phase reversal. A hardware controllable  
interface is also available (DSD operation is only possible in  
hardware mode).  
3.0V - 5.5V Supply Operation  
20-pin SSOP Package  
Exceeds Dolby Class A Performance Requirements  
APPLICATIONS  
The WM8728 is an ideal device to interface to AC-3 ,  
DTS , and MPEG audio decoders for surround sound  
applications, or for use in DVD players supporting DVD-A.  
DVD-Audio and DVD ‘Universal’ Players  
Home theatre systems  
Digital TV  
Digital broadcast receivers  
BLOCK DIAGRAM  
LATI2S  
MUTEB CSBIWL ZERO  
SCKDSD SDIDEM  
MODE  
CONTROL INTERFACE  
WM8728  
PCM/DSD  
MUX  
LOW  
PASS  
FILTER  
SIGMA  
DELTA  
MODULATOR  
MUTE/  
ATTEN  
RIGHT  
DAC  
VOUTR  
VOUTL  
BCKIN  
LRCIN  
DIN  
SERIAL  
INTERFACE  
DIGITAL FILTERS  
LOW  
PASS  
FILTER  
SIGMA  
DELTA  
MODULATOR  
LEFT  
DAC  
MUX  
MUTE/  
ATTEN  
VMID  
VREFP VREFN AGND DGND  
MCLK  
AVDD DVDD  
WOLFSON MICROELECTRONICS LTD  
Product Preview data sheets contain  
specifications for products in the  
formative phase of development. These  
products may be changed or discontinued  
without notice.  
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK  
Tel: +44 (0) 131 667 9386  
Fax: +44 (0) 131 667 5176  
Email: sales@wolfson.co.uk  
2001 Wolfson Microelectronics Ltd.  
www.wolfsonmicro.com  
WM8728  
Product Preview  
PIN CONFIGURATION  
ORDERING INFORMATION  
DEVICE  
TEMP. RANGE  
PACKAGE  
LRCIN  
DIN  
1
2
3
4
5
6
7
20  
19  
18  
17  
16  
15  
14  
LATI2S  
XWM8728EDS  
-25 to +85oC  
20-pin SSOP  
SCKDSD  
SDIDEM  
MUTEB  
MODE  
BCKIN  
MCLK  
ZERO  
DGND  
DVDD  
WM8728  
CSBIWL  
VREFP  
VOUTR  
AGND  
AVDD  
8
13  
12  
11  
VREFN  
VMID  
9
10  
VOUTL  
PIN DESCRIPTION  
PIN  
NAME  
TYPE  
DESCRIPTION  
1
LRCIN  
Digital Input  
DAC Sample Rate Clock Input: PCM Input Mode  
Right Channel DSD Bitstream Input: DSD Input Mode  
Serial Audio Data Input: PCM Input Mode  
Left Channel DSD Bitstream Input: DSD Input Mode  
Audio Data Bit Clock Input  
2
DIN  
Digital Input  
3
4
BCKIN  
MCLK  
Digital Input  
Digital Input  
Digital Output (Open drain)  
Supply  
Master Clock Input  
5
ZERO  
Infinite ZERO Detect Flag  
6
DGND  
DVDD  
VOUTR  
AGND  
AVDD  
Digital Ground Supply  
7
Supply  
Digital Positive Supply  
8
Analogue Output  
Supply  
Right Channel DAC Output  
9
Analogue Ground Supply  
10  
11  
12  
13  
14  
15  
Supply  
Analogue Positive Supply  
VOUTL  
VMID  
Analogue Output  
Analogue Output  
Supply  
Left Channel DAC Output  
Mid Rail Decoupling Point  
VREFN  
VREFP  
CSBIWL  
DAC Negative Reference normally AGND, must not be below AGND  
DAC Positive Reference normally AVDD, must not be above AVDD  
Software Mode: 3-Wire Serial Control Chip Select  
Hardware Mode: Input Word Length  
Supply  
Digital Input  
(pull-up)  
16  
17  
18  
MODE  
MUTEB  
SDIDEM  
Digital Input (pull-down)  
Digital Bi-directional  
Digital Bi-directional  
Control Mode Selection (L = Hardware, H = Software)  
Mute Control (L = Mute on, H = Mute off, Z = Automute Enabled)  
Software Mode: 3 or 2-Wire Serial Control Data Input:  
Hardware Mode: De-Emphasis Select  
19  
20  
SCKDSD  
LATI2S  
Digital Input  
(pull-down)  
Software Mode: 3 or 2-Wire Serial Control Clock Input  
Hardware Mode: DSD Bitstream Operation Select  
Software Mode 3-Wire Serial Control Load Input  
Hardware Mode: Input Data Format Selection  
Digital Input  
(pull-up)  
Note:  
Digital input pins have Schmitt trigger input buffers.  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.2 April 2001  
2
WM8728  
Product Preview  
ABSOLUTE MAXIMUM RATINGS  
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at  
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical  
Characteristics at the test conditions specified.  
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible  
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage  
of this device.  
CONDITION  
MIN  
-0.3V  
MAX  
+7V  
Digital supply voltage  
Analogue supply voltage  
-0.3V  
+7V  
Voltage range digital inputs  
Voltage range analogue inputs  
Master Clock Frequency  
DGND -0.3V  
AGND -0.3V  
DVDD +0.3V  
AVDD +0.3V  
50MHz  
Operating temperature range, TA  
Storage temperature  
-25°C  
-65°C  
+85°C  
+150°C  
+240°C  
+183°C  
Package body temperature (soldering 10 seconds)  
Package body temperature (soldering 2 minutes)  
Note:  
Analogue and digital grounds must always be within 0.3V of each other.  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.2 April 2001  
3
WM8728  
Product Preview  
DC ELECTRICAL CHARACTERISTICS  
PARAMETER  
SYMBOL  
DVDD  
TEST CONDITIONS  
MIN  
3.0  
TYP  
MAX  
UNIT  
V
Digital supply range  
Analogue supply range  
Ground  
5.5  
5.5  
AVDD  
3.0  
V
AGND, DGND  
0
0
V
Difference DGND to AGND  
Analogue supply current  
Digital supply current  
Analogue supply current  
Digital supply current  
-0.3  
+0.3  
V
AVDD = 5V  
DVDD = 5V  
AVDD = 3.3V  
DVDD = 3.3V  
19  
8
mA  
mA  
mA  
mA  
18  
4
ELECTRICAL CHARACTERISTICS  
Test Conditions  
AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Digital Logic Levels (TTL Levels)  
Input LOW level  
VIL  
VIH  
0.8  
V
V
V
V
Input HIGH level  
2.0  
Output LOW  
VOL  
VOH  
IOL = 1mA  
IOH = 1mA  
AGND + 0.3V  
Output HIGH  
AVDD 0.3V  
(VREFP -  
Analogue Reference Levels  
Reference voltage  
VMID  
(VREFP -  
(VREFP -  
V
VREFN)/2 - VREFN)/2 VREFN)/2 +  
50mV  
50mV  
Potential divider resistance  
RVMID  
12k  
ohms  
DAC Output (Load = 10k ohms. 50pF)  
0dBFs Full scale output voltage  
At DAC outputs  
1.1 x  
AVDD/5  
106  
Vrms  
dB  
SNR (Note 1,2,3)  
SNR (Note 1,2,3)  
SNR (Note 1,2,3)  
SNR (Note 1,2,3)  
A-weighted,  
@ fs = 48kHz  
A-weighted  
@ fs = 96kHz  
A-weighted  
100  
106  
106  
105  
dB  
dB  
@ fs = 192kHz  
A-weighted,  
dB  
@ fs = 48kHz  
AVDD, DVDD = 3.3V  
A-weighted  
@ fs = 96kHz  
AVDD, DVDD = 3.3V  
SNR (Note 1,2,3)  
SNR (Note 1,2,3)  
103  
106  
dB  
dB  
Non Aweighted @ fs  
= 48kHz  
THD (Note 1,2,3)  
1kHz, 0dBFs  
-97  
106  
100  
dB  
dB  
dB  
THD+N (Dynamic range, Note 2)  
DAC channel separation  
Analogue Output Levels  
Output level  
1kHz, -60dBFs  
100  
Load = 10k Ohms,  
0dBFS  
1.1  
VRMS  
VRMS  
Load = 10k Ohms,  
0dBFS,  
0.726  
(AVDD = 3.3V)  
Gain mismatch  
±1  
%FSR  
channel-to-channel  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.2 April 2001  
4
WM8728  
Product Preview  
Test Conditions  
AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Minimum resistance load  
To midrail or a.c.  
coupled  
1
kohms  
To midrail or a.c.  
coupled  
600  
ohms  
(AVDD = 3.3V)  
Maximum capacitance load  
Output d.c. level  
5V or 3.3V  
100  
pF  
V
(VREFP -  
VREFN)/2  
Power On Reset (POR)  
POR threshold  
2.4  
V
Notes:  
1. Ratio of output level with 1kHz full scale input, to the output level with all ZEROS into the digital input, over a 20Hz to  
20kHz bandwidth.  
2. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a  
filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical  
Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification  
values.  
3. VMID decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance).  
TERMINOLOGY  
1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full-scale output and the output with a  
ZERO signal applied. (No Auto-ZERO or Automute function is employed in achieving these results).  
2. Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal. Normally a  
THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g.  
THD+N @ -60dB= -32dB, DR= 92dB).  
3. THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.  
4. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band).  
5. Channel Separation (dB) - Also known as Cross Talk. This is a measure of the amount one channel is isolated from the  
other. Normally measured by sending a full-scale signal down one channel and measuring the other.  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.2 April 2001  
5
WM8728  
Product Preview  
MASTER CLOCK TIMING  
tMCLKL  
MCLK  
tMCLKH  
tMCLKY  
Figure 1 Master Clock Timing Requirements  
Test Conditions  
AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Master Clock Timing Information  
MCLK Master clock pulse width high  
MCLK Master clock pulse width low  
MCLK Master clock cycle time  
MCLK Duty cycle  
tMCLKH  
tMCLKL  
tMCLKY  
13  
13  
ns  
ns  
ns  
26  
40:60  
60:40  
DIGITAL AUDIO INTERFACE  
tBCH  
tBCL  
BCKIN  
LRCIN  
DIN  
tBCY  
tLRSU  
tDS  
tLRH  
tDH  
Figure 2 Digital Audio Data Timing  
Test Conditions  
AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Audio Data Input Timing Information  
BCKIN cycle time  
tBCY  
tBCH  
tBCL  
40  
16  
16  
8
ns  
ns  
ns  
ns  
BCKIN pulse width high  
BCKIN pulse width low  
LRCIN set-up time to  
BCKIN rising edge  
tLRSU  
LRCIN hold time from  
BCKIN rising edge  
tLRH  
tDS  
8
8
8
ns  
ns  
ns  
DIN set-up time to BCKIN  
rising edge  
DIN hold time from BCKIN  
rising edge  
tDH  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.2 April 2001  
6
WM8728  
Product Preview  
DSD AUDIO MONOPHASE INTERFACE  
tBCH  
tBCL  
MCLK  
tBCY  
DIN/LRCIN  
tDS  
tDH  
Figure 3 Normal DSD timing requirements  
Test Conditions  
AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Audio Data Input Timing Information  
MCLK cycle time  
tBCY  
tBCH  
tBCL  
tDS  
344  
ns  
ns  
ns  
ns  
MCLK pulse width high  
MCLK pulse width low  
160  
160  
10  
DIN/LRCIN set-up time to  
MCLK rising edge  
DIN/LRCIN hold time from  
MCLK rising edge  
tDH  
10  
ns  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.2 April 2001  
7
WM8728  
Product Preview  
DSD AUDIO BIPHASE INTERFACE  
tPH  
tBCY  
BCKIN  
tBCH  
tBCL  
tMCL  
tMCH  
MCLK  
tMCY  
tSU  
tHD  
D0  
D1  
D1  
D2  
D2  
DIN/LRCIN  
Figure 4 Biphase DSD Timing Requirements  
Test Conditions  
AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Audio Data Input Timing Information  
BCKIN cycle time  
tBCY  
tBCH  
tBCL  
tMCY  
tMCH  
tMCL  
tPH  
162.8  
81.4  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
BCKIN pulse width high  
BCKIN pulse width low  
MCLK cycle time  
80  
80  
81.4  
325.5  
162.8  
162.8  
MCLK pulse width high  
MCLK pulse width low  
160  
160  
Phase shift between BCKIN  
and MCLK  
20  
Data setup time to BCKIN  
falling edge  
tSU  
tHD  
10  
10  
ns  
ns  
Data hold time to BCKIN  
rising edge  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.2 April 2001  
8
WM8728  
Product Preview  
MPU 3-WIRE INTERFACE TIMING  
CSBIWL  
LATI2S  
tCSSU  
tCSSH  
tCSL  
tCSH  
tSCY  
tCSS  
tSCS  
tSCH  
tSCL  
SCKDSD  
SDIDEM  
LSB  
tDSU  
tDHO  
Figure 5 Program Register Input Timing - 3-Wire Serial Control Mode  
Test Conditions  
AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Program Register Input Information  
SCKDSD rising edge to LATI2S  
rising edge  
tSCS  
40  
ns  
SCKDSD pulse cycle time  
SCKDSD pulse width low  
SCKDSD pulse width high  
tSCY  
tSCL  
tSCH  
tDSU  
80  
20  
20  
20  
ns  
ns  
ns  
ns  
SDIDEM to SCKDSD set-up  
time  
SCKDSD to SDIDEM hold time  
LATI2S pulse width low  
tDHO  
tCSL  
tCSH  
tCSS  
tCSSU  
tCSSH  
20  
20  
20  
20  
20  
20  
ns  
ns  
ns  
ns  
ns  
ns  
LATI2S pulse width high  
LATI2S rising to SCKDSD rising  
CSBIWL to LATI2S set-up time  
LATI2S to CSBIWL hold time  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.2 April 2001  
9
WM8728  
Product Preview  
MPU 2-WIRE INTERFACE TIMING  
tSCF  
tSCY  
SCKDSD  
tSSU tSHD  
tSCH  
tDHD tDSU  
tDR  
tESU  
tSCL  
tSCR  
SDIDEM  
tDF  
Figure 6 Program Register Input Timing - 2-Wire Serial Control Mode  
Test Conditions  
AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Program Register Input Information  
SCKDSD pulse cycle time  
tSCY  
tSCL  
tSCH  
tSSU  
80  
20  
20  
10  
ns  
ns  
ns  
ns  
SCKDSD pulse width low  
SCKDSD pulse width high  
SDIDEM to SCKDSD data set-  
up time for start signal  
SDIDEM from SCKDSD data  
hold time for start signal  
tSHD  
tDSU  
tDHD  
10  
20  
20  
ns  
ns  
ns  
SDIDEM to SCKDSD data set-  
up time  
SCKDSD to SDIDEM data hold  
time  
SCKDSD rise time  
SCKDSD fall time  
SDIDEM rise time  
SDIDEM fall time  
tSCR  
tSCF  
tDR  
5
5
ns  
ns  
ns  
ns  
ns  
5
tDF  
5
SDIDEM to SCKDSD data set-  
up time for stop signal  
tESU  
10  
Notes:  
1. The address for the device in the 2-wire mode is 001101X (binary) with the last bit selectable.  
2. In the two-wire interface mode, the CSBIWL pin indicates the final bit of the chip address.  
3. In 2-wire mode the LATI2S pin should be tied to either DGND or DVSS to avoid noise toggling the interface into 3-wire  
mode.  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.2 April 2001  
10  
WM8728  
Product Preview  
DEVICE DESCRIPTION  
INTRODUCTION  
The WM8728 is a high performance DAC designed for digital consumer audio applications. Its  
range of features makes it ideally suited for use in DVD players, AV receivers and other high-end  
consumer audio equipment.  
WM8728 is a complete 2-channel stereo audio digital-to-analogue converter, including digital  
interpolation filter, multi-bit sigma delta with dither, switched capacitor multi-bit stereo DAC and  
output smoothing filters. The WM8728 includes an on-chip digital volume control, configurable  
digital audio interface and a 2 or 3 wire MPU control interface. It is fully compatible and an ideal  
partner for a range of industry standard microprocessors, controllers and DSPs.  
Control of internal functionality of the device is by either hardware control (pin programmed) or  
software control (2 or 3-wire serial control interface). The MODE pin selects between hardware  
and software control. The software control interface may be asynchronous to the audio data  
interface. In which case control data will be re-synchronised to the audio processing internally.  
Operation using a master clock of 256fs, 384fs, 512fs or 768fs is provided, selection between  
clock rates being automatically controlled in hardware mode, or serial controlled when in software  
mode. Sample rates (fs) from less than 8ks/s to 96ks/s are allowed, provided the appropriate  
master clock is input. Support is also provided for up to 192ks/s using a master clock of 128fs or  
192fs.  
The audio data interface supports right justified, left justified and I2S (Philips left justified, one bit  
delayed) interface formats along with a highly flexible DSP serial port interface. When in hardware  
mode, the three serial interface pins become control pins to allow selection of, input data format  
type (I2S or right justified), input word length (20 or 24 bit) and de-emphasis functions.  
In DSD mode, a separate bitstream data input pin is required for each of the channels, plus a 64fs  
dataclock MCLK. These signals are applied via pins DIN and LRCIN and the signals routed  
internally into the DAC circuits, under control of the SCKDSD mode select pin (19) See Figure 3.  
Additionally a Phase Modulation scheme is supported, whereby the audio data is transmitted as a  
Manchester encoded bitstream. This has the advantage of removing the significant spectral audio  
energy from the datastream, minimising digital signal corruption of the analogue outputs. In order  
to simplify decoding of this Phase modulated data, a 2x speed clock (BCKIN) is used to sample  
the incoming data. See Figure 4.  
The device is packaged in a small 20-pin SSOP.  
CLOCKING SCHEMES  
In a typical digital audio system there is only one central clock source producing a reference clock  
to which all audio data processing is synchronised. This clock is often referred to as the audio  
systems Master Clock. The external master system clock can be applied directly through the  
MCLK input pin with no software configuration necessary for sample rate selection.  
Note that on the WM8728, MCLK is used to derive clocks for the DAC path. The DAC path  
consists of DAC sampling clock, DAC digital filter clock and DAC digital audio interface timing. In  
a system where there are a number of possible sources for the reference clock it is recommended  
that the clock source with the lowest jitter be used to optimise the performance of the DAC.  
WM8728 always acts as a slave and requires clocks to be inputs.  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.2 April 2001  
11  
WM8728  
Product Preview  
DIGITAL AUDIO INTERFACE  
Audio data is applied to the internal DAC filters via the Digital Audio Interface. Five popular  
interface formats are supported:  
Left Justified mode  
Right Justified mode  
I2S mode  
DSP Early mode  
DSP Late mode  
All five formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits with the  
exception that 32 bit data is not supported in right justified mode. DIN and LRCIN maybe  
configured to be sampled on the rising or falling edge of BCKIN.  
In left justified, right justified and I2S modes, the digital audio interface receives data on the DIN  
input. Audio Data is time multiplexed with LRCIN indicating whether the left or right channel is  
present. LRCIN is also used as a timing reference to indicate the beginning or end of the data  
words. The minimum number of BCKINs per LRCIN period is 2 times the selected word length.  
LRCIN must be high for a minimum of word length BCKINs and low for a minimum of word length  
BCKINs. Any mark to space ratio on LRCIN is acceptable provided the above requirements are  
met  
The WM8728 will automatically detect when data with a LRCIN period of exactly 32 BCKINs is  
sent, and select 16-bit mode - overriding any previously programmed word length. Word length  
will revert to a programmed value only if a LRCIN period other than 32 BCKINs is detected.  
In DSP early or DSP late mode, the data is time multiplexed onto DIN. LRCIN is used as a frame  
sync signal to identify the MSB of the first word. The minimum number of BCKINs per LRCIN  
period is 2 times the selected word length. Any mark to space ratio is acceptable on LRCIN  
provided the rising edge is correctly positioned. (See Figure 10 and Figure 11)  
LEFT JUSTIFIED MODE  
In left justified mode, the MSB is sampled on the first rising edge of BCKIN following a LRCIN  
transition. LRCIN is high during the left data word and low during the right data word.  
1/fs  
LEFT CHANNEL  
RIGHT CHANNEL  
LRCIN  
BCKIN  
DIN  
1
2
3
n
n-2 n-1  
1
2
3
n
n-2 n-1  
MSB  
LSB  
MSB  
LSB  
Figure 7 Left Justified Mode Timing Diagram  
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RIGHT JUSTIFIED MODE  
In right justified mode, the LSB is sampled on the rising edge of BCKIN preceding a LRCIN  
transition. LRCIN is high during the left data word and low during the right data word.  
1/fs  
LEFT CHANNEL  
RIGHT CHANNEL  
LRCIN  
BCKIN  
DIN  
1
2
3
n
1
2
3
n
n-2 n-1  
n-2 n-1  
MSB  
LSB  
MSB  
LSB  
Figure 8 Right Justified Mode Timing Diagram  
I2S MODE  
In I2S mode, the MSB is sampled on the second rising edge of BCKIN following a LRCIN  
transition. LRCIN is low during the left data word and high during the right data word.  
1/fs  
LEFT CHANNEL  
RIGHT CHANNEL  
LRCIN  
BCKIN  
1 BCKIN  
1 BCKIN  
DIN  
1
2
3
n
1
2
3
n
n-2 n-1  
n-2 n-1  
LSB  
LSB  
MSB  
MSB  
Figure 9 I2S Mode Timing Diagram  
DSP EARLY MODE  
In DSP early mode, the first bit is sampled on the BCKIN rising edge following the one that  
detects a low to high transition on LRCIN. No BCKIN edges are allowed between the data words.  
The word order is DIN left, DIN right.  
1 BCKIN  
1 BCKIN  
1/fs  
LRCIN  
BCKIN  
LEFT CHANNEL  
RIGHT CHANNEL  
NO VALID DATA  
DIN  
1
2
n
1
2
n
n-1  
n-1  
MSB  
LSB  
Input Word Length (IWL)  
Figure 10 DSP Early Mode Timing Diagram  
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DSP LATE MODE  
In DSP late mode, the first bit is sampled on the BCKIN rising edge, which detects a low to high  
transition on LRCIN. No BCKIN edges are allowed between the data words. The word order is  
DIN left, DIN right.  
1/fs  
LRCIN  
BCKIN  
LEFT CHANNEL  
RIGHT CHANNEL  
NO VALID DATA  
DIN  
1
2
n
1
2
n
1
n-1  
n-1  
MSB  
LSB  
Input Word Length (IWL)  
Figure 11 DSP Late Mode Timing Diagram  
AUDIO DATA SAMPLING RATES  
The master clock for WM8728 can range from 128fs to 768fs, where fs is the audio sampling  
frequency (LRCIN) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The master clock is used  
to operate the digital filters and the noise shaping circuits.  
The WM8728 has a master clock detection circuit that automatically determines the relationship  
between the master clock frequency and the sampling rate (to within +/- 32 system clocks). If  
there is a greater than 32 clocks error, the interface shuts down the DAC and mutes the output.  
The master clock should be synchronised with LRCIN, although the WM8728 is tolerant of phase  
differences or jitter on this clock. See Table 1  
SAMPLING  
RATE  
MASTER CLOCK FREQUENCY (MHZ) (MCLK)  
128fs  
192fs  
256fs  
384fs  
512fs  
768fs  
(LRCIN)  
32kHz  
44.1kHz  
48kHz  
4.096  
5.6448  
6.114  
6.144  
8.467  
8.192  
11.2896  
12.288  
24.576  
12.288  
16.9340  
18.432  
36.864  
16.384  
22.5792  
24.576  
24.576  
33.8688  
36.864  
9.216  
96kHz  
12.288  
24.576  
18.432  
36.864  
Unavailable Unavailable  
192kHz  
Unavailable Unavailable Unavailable Unavailable  
Table 1 Typical Relationships Between Master Clock Frequency and Sampling Rate  
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HARDWARE DSD MODE  
DSD mode is selected by taking the SCKDSD pin high whilst the MODE pin is low. In this mode  
the internal digital filters are bypassed, and the already modulated bitstream data is applied  
directly to the Switched Capacitor DAC filter where it is converted and lowpass filtered, see Figure  
26 to Figure 29.  
Two formats are supported for data transfer, MONOPHASE or BIPHASE MODULATED.  
In Monophase mode, DSD data is simply clocked into the device using the rising edge of the 64fs  
MCLK signal.  
In Biphase mode, the data is supplied in Manchester encoded form (a bit transition occurs during  
every data bit, which shapes the spectral energy minimising corruption of the analogue outputs).  
A secondary clock BCKIN, at 128fs is used to simplify data recovery, the data simply being  
clocked with the falling edge of BCKIN when MCLK is at logic low (0V).  
See Figure 3 and Figure 4 for details of DSD interface timing.  
HARDWARE CONTROL MODES  
When the MODE pin is held low, the following hardware modes of operation are available.  
MUTE AND AUTOMUTE OPERATION  
In both hardware and software modes, pin 17 (MUTEB) controls the selection of MUTE directly,  
and can be used to enable and disable the automute function. This pin becomes an output when  
left floating and indicates infinite ZERO detect (IZD) see also pin 5 (ZERO).  
MUTEB PIN  
DESCRIPTION  
0
1
Mute DAC channels  
Normal Operation  
Floating  
Enable IZD, MUTEB becomes an output to indicate when IZD occurs.  
L=IZD detected, H=IZD not detected.  
Table 2 Mute and Automute Control  
Figure 12 shows the application and release of MUTE whilst a full amplitude sinusoid is being  
played at 48kHz sampling rate. When MUTE (lower trace) is asserted, the output (upper trace)  
begins to decay exponentially from the DC level of the last input sample. The output will decay  
towards VMID with a time constant of approximately 64 input samples. When MUTE is de-  
asserted, the output will restart almost immediately from the current input sample.  
1.5  
1
0.5  
0
-0.5  
-1  
-1.5  
-2  
-2.5  
0
0.001  
0.002  
0.003  
0.004  
0.005  
0.006  
Time(s)  
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Figure 12 Application and Release of Soft Mute  
The MUTEB pin is an input to select mute or not mute. MUTEB is active low; taking the pin low  
causes the filters to soft mute, ramping down the audio signal over a few milliseconds. Taking  
MUTEB high again allows data into the filter.  
The automute function detects a series of ZERO value audio samples of 1024 samples long  
being applied to both channels. After such an event, a latch is set whose output (AUTOMUTED)  
is wire ORed through a 10kohm resistor to the MUTEB pin. Thus if the MUTEB pin is not being  
driven, the automute function will assert mute.  
If MUTEB is tied high, AUTOMUTED is overridden and will not mute unless the IZD register bit is  
set. If MUTEB is driven from a bi-directional source, then both MUTE and automute functions are  
available. If MUTEB is not driven, AUTOMUTED appears as a weak output (10kOhm-source  
impedance) so can be used to drive external mute circuits. AUTOMUTED will be removed as  
soon as any channel receives a non-ZERO input.  
A diagram showing how the various Mute modes interact is shown below Figure 13.  
IZD (Register Bit)  
AUTOMUTED  
(Internal Signal)  
10k  
SOFTMUTE  
(Internal  
Signal)  
MUTEB  
PIN  
MUT (Register Bit)  
Figure 13 Selection Logic for MUTE Modes  
INPUT FORMAT SELECTION  
In hardware mode, LATI2S (pin 20) and CSBIWL (pin 15) become input controls for selection of  
input data format type and input data word length.  
LATI2S  
CSBIWL  
INPUT DATA MODE  
24-bit right justified  
0
0
1
0
1
0
20-bit right justified  
16-bit I2S  
24-bit I2S  
1
1
Table 3 Input Format Selection  
Note:  
In 24 bit I2S mode, any width of 24 bits or less is supported provided that LRCIN is high for a  
minimum of 24 BCKINs and low for a minimum of 24 BCKINs. If exactly 32 BCKINs occur in one  
LRCIN (16 high, 16 low) the chip will auto detect and run a 16 bit data mode.  
DE-EMPHASIS CONTROL  
In hardware mode, SDIDEM (pin 18) becomes an input control for selection of de-emphasis  
filtering to be applied.  
SDIDEM  
DE-EMPHASIS  
0
Off  
On  
1
Table 4 De-emphasis Control  
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SOFTWARE CONTROL INTERFACE  
The software control interface may be operated using a 2-wire interface compatible or 3-wire (SPI-  
compatible) interface.  
SELECTION OF CONTROL MODE  
The WM8728 may be programmed to operate in hardware or software control modes. This is  
achieved by setting the state of the MODE pin.  
MODE  
INTERFACE FORMAT  
Hardware Control Mode  
Software Control Mode  
0
1
Table 5 Control Interface Mode Selection  
3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE  
In this mode, SDIDEM is used for the program data, SCKDSD is used to clock in the program  
data and LATI2S is used to latch in the program data. The 3-wire interface protocol is shown in  
Figure 14.  
LATI2S  
SCKDSD  
B15  
B14  
B13  
B12  
B11  
B10  
B9  
B8  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
SDIDEM  
Figure 14 3-Wire Serial Interface  
Notes:  
1. B[15:9] are Control Address Bits  
2. B[8:0] are Control Data Bits  
3. CSBIWL needs to be low during writes see Figure 5  
2-WIRE SERIAL CONTROL MODE  
In 2-wire mode, which is the default, SDIDEM is used for the program data and SCKDSD is used  
to clock in the program data see Figure 15.  
WM8728 has an address of 001101X (binary) which represents an audio device. The final  
address digit is dependent on pin CSBIWL, which should be tied to either DVDD or DGND. This  
allows the device to have a choice of two identification header addresses used in the 2 wire  
interface word. This feature allows more than one WM8728 device to be present on the interface  
bus.  
LATI2S should be tied to either DVDD or DGND, as it is unused. This pin if toggled from low to  
high and high to low, will cause the device to enter the 3-wire interface mode and cannot be  
placed back into 2-wire mode except by toggling the MODE pin, or powering off the device.  
ACK  
ACK  
ACK  
DATA B15-8  
R ADDR  
R/W  
DATA B7-0  
SDIDEM  
SCKDSD  
START  
STOP  
Figure 15 2-Wire Serial Interface  
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REGISTER MAP  
WM8728 uses a total of 4 program registers, which are 16-bits long. These registers are all loaded through input pin SDIDEM.  
Using either 2-wire or 3-wire serial control mode as shown in Figure 14 and Figure 15.  
B15  
B14  
B13  
B12  
B11  
B10  
B9  
0
B8  
B7  
B6  
LAT6  
RAT6  
0
B5  
LAT5  
RAT5  
IW2  
B4  
B3  
LAT3  
RAT3  
IW0  
0
B2  
LAT2  
RAT2  
PWDN  
ATC  
B1  
LAT1  
RAT1  
B0  
LAT0  
RAT0  
M0  
M1  
M2  
M3  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
UPDATEL LAT7  
UPDATER RAT7  
LAT4  
RAT4  
IW1  
0
1
0
0
0
0
0
EEMPH MUT  
I2S  
0
1
IZD  
0
BCP  
REV  
LRP  
ADDRESS  
DATA  
Table 6 Mapping of Program Registers  
REGISTER  
ADDRESS  
(A3,A2,A1,A0)  
0000  
BITS  
NAME  
DEFAULT  
DESCRIPTION  
[7:0]  
8
LAT[7:0] 11111111 (0dB) Attenuation data for left channel in 0.5dB steps, see Table 9  
DACL  
UPDATEL  
0
Attenuation data load control for left channel.  
Attenuation  
0: Store DACL in intermediate latch (no change to output)  
1: Store DACL and update attenuation on both channels.  
0001  
[7:0]  
8
RAT[7:0] 11111111 (0dB) Attenuation data for right channel in 0.5dB steps, see Table 9  
DACR  
Attenuation  
UPDATER  
0
0
0
0
Attenuation data load control for right channel.  
0: Store DACR in intermediate latch (no change to output)  
1: Store DACR and update attenuation on both channels.  
Left and right DACs soft mute control.  
0: No mute  
0010  
0
1
2
MUT  
DAC Control  
1: Mute  
DEEMPH  
PWDN  
De-emphasis control.  
0: De-emphasis off  
1: De-emphasis on  
Left and Right DACs Power-down Control  
0: All DACs running, output is active  
1: All DACs in power saving mode, output muted  
Audio data format select, see Table 14  
Audio data format select, see Table 14  
Polarity select for LRCIN/DSP mode select.  
0: normal LRCIN polarity/DSP late mode  
1: inverted LRCIN polarity/DSP early mode  
Attenuator Control.  
[5:3]  
0
IW[2:0]  
I2S  
0
0
0
0011  
Interface  
Control  
1
LRP  
2
ATC  
0
0: All DACs use attenuation as programmed.  
1: Right channel DACs use corresponding left DAC  
attenuation  
4
5
REV  
BCP  
0
0
Output phase reverse.  
BCKIN Polarity  
0 : normal BCKIN polarity  
1: inverted BCKIN polarity  
8
IZD  
0
Infinite ZERO detection circuit control and automute control  
0: Infinite ZERO detect disabled  
1: Infinite ZERO detect enabled  
Table 7 Register Bit Descriptions  
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ATTENUATION CONTROL  
Each DAC channel can be attenuated digitally before being applied to the digital filter. Attenuation  
is 0dB by default but can be set between 0 and 127.5dB in 0.5dB steps using the 8 Attenuation  
control bits. All attenuation registers are double latched allowing new values to be pre-latched to  
both channels before being updated synchronously. Setting the UPDATE bit on any attenuation  
write will cause all pre-latched values to be immediately applied to the DAC channels.  
REGISTER  
ADDRESS  
BITS  
LABEL  
DEFAULT  
DESCRIPTION  
0000  
[7:0]  
LAT[7:0]  
11111111 (0dB)  
Attenuation data for Left channel DACL in 0.5dB steps.  
Attenuation  
DACL  
8
UPDATEL  
0
Controls simultaneous update of all Attenuation Latches  
0: Store DACL in intermediate latch (no change to output)  
1: Store DACL and update attenuation on all channels.  
Attenuation data for Right channel DACR in 0.5dB steps.  
0001  
[7:0]  
8
RAT[7:0]  
11111111 (0dB)  
0
Attenuation  
DACR  
UPDATER  
Controls simultaneous update of all Attenuation Latches  
0: Store DACR in intermediate latch (no change to output)  
1: Store DACR and update attenuation on all channels.  
Table 8 Attenuation Register Map  
Note:  
1. The UPDATE bit is not latched. If UPDATE=0, the Attenuation value will be written to the pre-latch but not applied to the  
relevant DAC. If UPDATE=1, all pre-latched values and the current value being written will be applied on the next input  
sample.  
2. Care should be used in reducing the attenuation as rapid large volume changes can introduce zipper noise.  
DAC OUTPUT ATTENUATION  
Registers LAT and RAT control the left and right channel attenuation. Table 9 shows how the  
attenuation levels are selected from the 8-bit words.  
XAT[7:0]  
ATTENUATION LEVEL  
00(hex)  
dB (mute)  
01(hex)  
127.5dB  
:
:
:
:
:
:
FE(hex)  
FF(hex)  
0.5dB  
0dB  
Table 9 Attenuation Control Levels  
MUTE MODES  
Setting the MUT register bit will apply a softmute to the input of the digital filters:  
REGISTER ADDRESS  
0010  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
Soft Mute select  
0
MUT  
0
DAC Control  
0 : Normal Operation  
1: Soft mute all channels  
Table 10 Mute control  
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DE-EMPHASIS MODE  
Setting the DEEMPH register bit puts the digital filters into de-emphasis mode:  
REGISTER ADDRESS  
0010  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
1
DEEMPH  
0
De-emphasis mode select:  
0 : De-emphasis Off  
DAC Control  
1: De-emphasis On  
Table 11 De-emphasis Control  
POWERDOWN MODE  
Setting the PWDN register bit immediately connects all outputs to VMID and selects a low power  
mode. All trace of the previous input samples is removed, and all control register settings are  
cleared. When PWDN is cleared again the first 16 input samples will be ignored, as the FIR will  
repeat its power-on initialisation sequence.  
REGISTER ADDRESS  
0010  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
Power Down Mode Select:  
0 : Normal Mode  
2
PWDN  
0
DAC Control  
1: Power Down Mode  
Table 12 Powerdown control  
DIGITAL AUDIO INTERFACE CONTROL REGISTERS  
The WM8728 has a fully featured digital audio interface that is a superset of that contained in the  
WM8716. Interface format is selected via the IWL[2:0] register bits in register M2 and the I2S  
register bit in M3.  
REGISTER ADDRESS  
0010  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
5:3  
IWL[2:0]  
000000  
Interface format Select  
DAC Control  
0011  
0
I2S  
0
Interface format Select  
Interface Control  
Table 13 Interface Format Controls  
IW2  
I2S  
IW1  
IW0  
AUDIO INTERFACE DESCRIPTION  
(NOTE 1)  
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
16 bit right justified mode  
20 bit right justified mode  
24 bit right justified mode  
24 bit left justified mode  
16 bit I2S mode  
24 bit I2S mode  
20 bit I2S mode  
20 bit left justified mode  
16 bit DSP mode  
20 bit DSP mode  
24 bit DSP mode  
32 bit DSP mode  
16 bit left justified mode  
Table 14 Audio Data Input Format  
Note:  
In all modes, the data is signed 2s complement. The digital filters always input 24-bit data. If the  
DAC is programmed to receive 16 or 20 bit data, the WM8728 pads the unused LSBs with  
ZEROS. If the DAC is programmed into 32-bit mode, the 8 LSBs are treated as zero.  
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SELECTION OF LRCIN POLARITY  
In left justified, right justified or I2S modes, the LRP register bit controls the polarity of LRCIN. If  
this bit is set high, the expected polarity of LRCIN will be the opposite of that shown in Figure 7,  
Figure 8 and Figure 9. Note that if this feature is used as a means of swapping the left and right  
channels, a 1 sample phase difference will be introduced.  
REGISTER ADDRESS  
0011  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
1
LRP  
0
LRCIN Polarity (normal)  
0 : normal LRCIN polarity  
1: inverted LRCIN polarity  
Interface Control  
Table 15 LRCIN Polarity Control  
In DSP modes, the LRCIN register bit is used to select between early and late modes (see Figure  
10 and Figure 11.  
REGISTER ADDRESS  
0011  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
1
LRP  
0
DSP Format (DSP modes)  
0 : Late DSP mode  
Interface Control  
1: Early DSP mode  
Table 16 DSP Format Control  
In DSP early mode, the first bit is sampled on the BCKIN rising edge following the one that  
detects a low to high transition on LRCIN. In DSP late mode, the first bit is sampled on the BCKIN  
rising edge, which detects a low to high transition on LRCIN. No BCKIN edges are allowed  
between the data words. The word order is DIN left, DIN right.  
ATTENUATOR CONTROL MODE  
Setting the ATC register bit causes the left channel attenuation settings to be applied to both left  
and right channel DACs from the next audio input sample. No update to the attenuation registers  
is required for ATC to take effect.  
REGISTER ADDRESS  
0011  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
2
ATC  
0
Attenuator Control Mode:  
0 : Right channels use Right  
attenuation  
Interface Control  
1: Right Channels use Left  
Attenuation  
Table 17 Attenuation Control Select  
OUTPUT PHASE REVERSAL  
The REV register bit controls the phase of the output signal. Setting the REV bit causes the  
phase of the output signal to be inverted.  
REGISTER ADDRESS  
0011  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
Analogue Output Phase  
0: Normal  
4
REV  
0
Interface Control  
1: Inverted  
Table 18 Output Phase Control  
BCKIN POLARITY  
By default, LRCIN and DIN are sampled on the rising edge of BCKIN and should ideally change  
on the falling edge. Data sources which change LRCIN and DIN on the rising edge of BCKIN can  
be supported by setting the BCP register bit. Setting BCP to 1 inverts the polarity of BCKIN to the  
inverse of that shown in Figure 7, Figure 8, Figure 9, Figure 10 and Figure 11.  
REGISTER ADDRESS  
0011  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
BCKIN Polarity  
5
BCP  
0
0 : normal BCKIN polarity  
1: inverted BCKIN polarity  
Interface Control  
Table 19 BCKIN Polarity Control  
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INFINITE ZERO DETECTION  
Setting the IZD register bit determines whether the device is automuted when a sequence of more  
than 1024 ZEROS is detected.  
REGISTER ADDRESS  
0011  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
8
IZD  
0
Infinite ZERO detection circuit  
control and automute control  
Interface Control  
0: Infinite ZERO detect disabled  
1: Infinite ZERO detect enabled  
Table 20 IZD Control  
DIGITAL FILTER CHARACTERISTICS  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
-3dB  
MIN  
TYP  
MAX  
UNIT  
Passband Edge  
Passband Ripple  
Stopband Attenuation  
0.487fs  
f < 0.444fs  
f > 0.555fs  
±0.05  
dB  
dB  
-60  
Table 21 Digital Filter Characteristics  
DAC FILTER RESPONSES  
0.2  
0.15  
0.1  
0
-20  
-40  
0.05  
0
-60  
-0.05  
-0.1  
-0.15  
-0.2  
-80  
-100  
-120  
0
0.5  
1
1.5  
2
2.5  
3
0
0.05  
0.1  
0.15  
0.2  
0.25  
0.3  
0.35  
0.4  
0.45  
0.5  
Frequency (Fs)  
Frequency (Fs)  
Figure 16 DAC Digital Filter Frequency Response  
-44.1, 48 and 96kHz  
Figure 17 DAC Digital Filter Ripple  
-44.1, 48 and 96kHz  
0.2  
0
-20  
-40  
-60  
-80  
0
-0.2  
-0.4  
-0.6  
-0.8  
-1  
0
0.2  
0.4  
0.6  
0.8  
1
0
0.05  
0.1  
0.15  
0.2  
0.25  
0.3  
0.35  
0.4  
0.45  
0.5  
Frequency (Fs)  
Frequency (Fs)  
Figure 18 DAC Digital Filter Frequency Response  
-192kHz  
Figure 19 DAC Digital Filter Ripple  
-192kHz  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.2 April 2001  
22  
WM8728  
Product Preview  
DIGITAL DE-EMPHASIS CHARACTERISTICS  
0
1
0.5  
0
-2  
-4  
-0.5  
-1  
-6  
-1.5  
-2  
-8  
-2.5  
-3  
-10  
0
2
4
6
8
10  
12  
14  
16  
0
2
4
6
8
10  
12  
14  
16  
Frequency (kHz)  
Frequency (kHz)  
Figure 20 De-Emphasis Frequency Response (32kHz)  
Figure 21 De-Emphasis Error (32kHz)  
0
0.4  
0.3  
0.2  
0.1  
0
-2  
-4  
-6  
-0.1  
-0.2  
-0.3  
-0.4  
-8  
-10  
0
5
10  
15  
20  
0
5
10  
15  
20  
Frequency (kHz)  
Frequency (kHz)  
Figure 22 De-Emphasis Frequency Response (44.1kHz)  
Figure 23 De-Emphasis Error (44.1kHz)  
0
1
0.8  
0.6  
0.4  
0.2  
0
-2  
-4  
-6  
-0.2  
-0.4  
-0.6  
-0.8  
-1  
-8  
-10  
0
5
10  
15  
20  
0
5
10  
15  
20  
Frequency (kHz)  
Frequency (kHz)  
Figure 24 De-Emphasis Frequency Response (48kHz)  
Figure 25 De-Emphasis Error (48kHz)  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.2 April 2001  
23  
WM8728  
Product Preview  
DSD MODE CHARACTERISTICS  
5
0
0
-10  
-20  
-30  
-40  
-50  
-60  
-5  
-10  
-15  
-20  
-25  
-30  
-35  
-40  
-45  
0
500  
1000  
Frequency (kHz)  
1500  
2000  
0
50  
100  
150  
200  
250  
300  
350  
400  
Frequency (kHz)  
Figure 26 DSD Frequency Response - no post filter  
Figure 27 DSD Frequency Response - no post filter  
0
-20  
0
-2  
-4  
-6  
-8  
-40  
-60  
-80  
-100  
-120  
0
50  
100  
150  
200  
250  
300  
350  
400  
0
10  
20  
30  
40  
50  
60  
Frequency (kHz)  
Frequency (kHz)  
Figure 28 DSD frequency response - 4th order post filter  
Figure 29 DSD frequency response - 4th order post filter  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.2 April 2001  
24  
WM8728  
Product Preview  
RECOMMENDED EXTERNAL COMPONENTS  
DVDD  
7
AVDD  
+
10  
14  
DVDD  
DGND  
AVDD  
+
C1  
C2  
VREFP  
6
C3  
C4  
C5  
9
AGND  
DGND  
13  
VREFN  
AGND  
15  
20  
19  
18  
17  
CSBIWL  
LATI2S  
Software I/F or  
Hardware Control  
SCKDSD  
SDIDEM  
MUTEB  
C6  
8
VOUTR  
VOUTL  
AC-Coupled  
VOUTR/L  
to External LPF  
Software/hardware  
control mode select  
16  
MODE  
WM8728  
C7  
11  
1
4
LRCIN  
MCLK  
3
2
Audio Serial Data I/F  
BCKIN  
DIN  
5
12  
ZERO  
VMID  
+
C8  
C9  
AGND  
Notes:  
1. AGND and DGND should be connected as close to the WM8728 as possible.  
2. C2, C3, C4 and C8 should be positioned as close to the WM8728 as possible.  
3. Capacitor types should be carefully chosen. Capacitors with very low ESR are  
recommended for optimum performance.  
Figure 30 External Components Diagram  
RECOMMENDED EXTERNAL COMPONENTS VALUES  
COMPONENT  
REFERENCE  
SUGGESTED  
VALUE  
DESCRIPTION  
C1 and C5  
C2 to C4  
C6 and C7  
C8  
10µF  
0.1µF  
10µF  
0.1µF  
10µF  
De-coupling for DVDD and AVDD/VREFP  
De-coupling for DVDD and AVDD/VREFP  
Output AC coupling caps to remove midrail DC level from outputs.  
Reference de-coupling capacitors for VMID pin.  
C9  
Table 22 External Components Description  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.2 April 2001  
25  
WM8728  
Product Preview  
RECOMMENDED DSD EXTERNAL COMPONENTS  
DVDD  
AVDD  
+
7
6
10  
14  
DVDD  
DGND  
AVDD  
+
C1  
C2  
VREFP  
C3  
C4  
C5  
9
AGND  
DGND  
DVDD  
13  
VREFN  
AGND  
15  
20  
19  
18  
17  
CSBIWL  
LATI2S  
SCKDSD  
SDIDEM  
MUTEB  
MUTE Control  
C6  
8
VOUTR  
VOUTL  
AC-Coupled  
VOUTR/L  
to External LPF  
16  
MODE  
WM8728  
C7  
11  
DGND  
1
4
DSD right bitstream  
DSD bit clock  
LRCIN  
MCLK  
3
2
BCKIN  
DIN  
DSD biphase mode clock  
DSD left bitstream  
5
12  
ZERO  
VMID  
+
C8  
C9  
AGND  
Notes:  
1. AGND and DGND should be connected as close to the WM8728 as possible.  
2. C2, C3, C4 and C8 should be positioned as close to the WM8728 as possible.  
3. Capacitor types should be carefully chosen. Capacitors with very low ESR are  
recommended for optimum performance.  
4. When using monophase DSD encoding pin 3 BCKIN should be tied to  
DVDD. In Biphase DSD encoding BCKIN runs at 2 cycles per bit.  
Figure 31 External Connections for DSD Applications  
RECOMMENDED EXTERNAL COMPONENTS VALUES FOR DSD  
COMPONENT  
REFERENCE  
SUGGESTED  
VALUE  
DESCRIPTION  
C1 and C5  
C2 to C4  
C6 and C7  
C8  
10µF  
0.1µF  
10µF  
0.1µF  
10µF  
De-coupling for DVDD and AVDD.  
De-coupling for DVDD and AVDD.  
Output AC coupling caps to remove midrail DC level from outputs.  
Reference de-coupling capacitors for VMID pin.  
C9  
Table 23 External Components for DSD  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.2 April 2001  
26  
WM8728  
Product Preview  
RECOMMENDED DSD CONNECTIONS  
64fs  
BCKA  
MCLK  
LRCIN  
DIN  
Right Channel Data  
DSAR  
DSAL  
CXD2751Q  
WM8728EDS  
Left Channel Data  
Figure 32 Monophase Mode Connection Diagram  
128fs  
BCKA  
BCKIN  
MCLK  
LRCIN  
DIN  
64fs  
BCKD  
CXD2751Q  
WM8728EDS  
Right Channel Data  
DSAR  
DSAL  
Left Channel Data  
Figure 33 Biphase Mode Connection Diagram  
DSD mode is selected with the WM8728 by pulling the SCKDSD pin high while the MODE pin is held low.  
DSD mode is hardware only operation.  
The CXD2751Q from Sony is a signal processor for Super Audio CD playback.  
RECOMMENDED ANALOGUE LOW PASS FILTER FOR PCM DATA FORMAT  
(OPTIONAL)  
4.7k  
4.7k  
+VS  
_
51  
10uF  
1.8k  
7.5K  
+
+
-VS  
1.0nF  
680pF  
47k  
Figure 34 Recommended Low Pass Filter (Optional)  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.2 April 2001  
27  
WM8728  
Product Preview  
PACKAGE DIMENSIONS  
DS: 20 PIN SSOP (7.2 x 5.3 x 1.75 mm)  
DM0015.A  
b
e
20  
11  
E1  
E
GAUGE  
PLANE  
Θ
1
10  
D
0.25  
c
L
A1  
A A2  
-C-  
0.10 C  
SEATING PLANE  
Dimensions  
(mm)  
NOM  
-----  
Symbols  
MIN  
-----  
MAX  
2.0  
-----  
1.85  
0.38  
0.25  
7.50  
A
A1  
A2  
b
c
D
e
E
E1  
L
0.05  
1.65  
0.22  
0.09  
6.90  
-----  
1.75  
-----  
-----  
7.20  
0.65 BSC  
7.80  
7.40  
5.00  
0.55  
0o  
8.20  
5.60  
0.95  
8o  
5.30  
0.75  
4o  
θ
REF:  
JEDEC.95, MO-150  
NOTES:  
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.  
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.  
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM.  
D. MEETS JEDEC.95 MO-150, VARIATION = AE. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.2 April 2001  
28  
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