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XWM8729ED

型号:

XWM8729ED

描述:

24位, 192kHz的立体声DAC[ 24-bit, 192kHz Stereo DAC ]

品牌:

WOLFSON[ WOLFSON MICROELECTRONICS PLC ]

页数:

15 页

PDF大小:

170 K

WM8729  
24-bit, 192kHz Stereo DAC  
Product Preview, Rev 1.2, April 2001  
DESCRIPTION  
FEATURES  
Stereo DAC  
Audio Performance  
The WM8729 is a high performance stereo DAC designed  
for audio applications such as DVD, home theatre systems,  
and digital TV. The WM8729 supports data input word  
lengths from 16 to 24-bits and sampling rates up to 192kHz.  
The WM8729 consists of a serial interface port, digital  
interpolation filters, multi-bit sigma delta modulators and  
stereo DAC in a small 16-pin SOIC package.  
-
106dB SNR (‘A’ weighted @ 48kHz) DAC  
-97dB THD  
-
DAC Sampling Frequency: 8kHz – 192kHz  
Pin Selectable Audio Data Interface Format  
-
I2S or Right Justified  
The WM8729 has a hardware control interface for selection  
of audio data interface format and de-emphasis.  
3.0V - 5.5V Supply Operation  
16-pin SOIC Package  
The WM8729 is an ideal device to interface to AC-3 ,  
DTS , and MPEG audio decoders for surround sound  
applications, or for use in DVD players, including supporting  
the implementation of 2 channels at 192kHz for high-end  
DVD-Audio applications.  
Exceeds Dolby Class A Performance Requirements  
APPLICATIONS  
DVD-Audio and DVD ‘Universal’ Players  
Home theatre systems  
Digital TV  
Digital broadcast receivers  
BLOCK DIAGRAM  
FORMAT MUTEB  
DEM  
CONTROL INTERFACE  
WM8729  
SIGMA  
DELTA  
MODULATOR  
LOW  
PASS  
FILTER  
RIGHT  
DAC  
MUTE  
MUTE  
VOUTR  
VOUTL  
BCKIN  
LRCIN  
DIN  
SERIAL  
INTERFACE  
DIGITAL FILTERS  
SIGMA  
DELTA  
MODULATOR  
LOW  
PASS  
FILTER  
LEFT  
DAC  
VMID  
MCLK  
AVDD DVDD  
VREFP VREFN AGND DGND  
WOLFSON MICROELECTRONICS LTD  
Product Preview data sheets contain  
specifications for products in the formative  
phase of development. These products may  
be changed or discontinued without notice.  
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK  
Tel: +44 (0) 131 667 9386  
Fax: +44 (0) 131 667 5176  
Email: sales@wolfson.co.uk  
www.wolfsonmicro.com  
2001 Wolfson Microelectronics Ltd.  
WM8729  
Product Preview  
PIN CONFIGURATION  
ORDERING INFORMATION  
DEVICE  
TEMP. RANGE  
PACKAGE  
LRCIN  
DIN  
1
2
3
4
5
6
7
16  
15  
14  
13  
12  
11  
10  
FORMAT  
DEM  
XWM8729ED  
-25 to +85oC  
16-pin SOIC  
BCKIN  
MCLK  
DGND  
DVDD  
VOUTR  
MUTEB  
VREFP  
VREFN  
VMID  
WM8729  
VOUTL  
AGND  
8
9
AVDD  
PIN DESCRIPTION  
PIN  
1
NAME  
LRCIN  
DIN  
TYPE  
Digital Input  
Digital Input  
Digital Input  
Analogue Input  
Supply  
DESCRIPTION  
DAC Sample Rate Clock Input  
Serial Audio Data Input  
Audio Data Bit Clock Input.  
Master Clock Input  
2
3
BCKIN  
MCLK  
DGND  
DVDD  
VOUTR  
AGND  
AVDD  
VOUTL  
VMID  
4
5
Digital Ground Supply  
6
Supply  
Digital Positive Supply  
7
Analogue Output  
Supply  
Right Channel DAC Output  
Analogue Ground Supply  
Analogue Positive Supply  
Left Channel DAC Output  
Mid Rail Decoupling Point  
8
9
Supply  
10  
11  
12  
13  
14  
Analogue Output  
Analogue Output  
Supply  
VREFN  
VREFP  
MUTEB  
DAC Negative Reference – normally AGND, must not be below AGND  
DAC Positive Reference – normally AVDD, must not be above AVDD  
Supply  
Digital Bi-directional Mute Control, (L = Mute on, H = Mute off, Z = Automute Enabled)  
15  
DEM  
Digital Input  
De-Emphasis Select  
0 = De-Emphasis Off  
1 = De-Emphasis On  
16  
FORMAT  
Digital Input  
(Pull-Up)  
Digital Audio Data Input Format Selection  
0 = Right justified Audio Data  
1 = I2S Audio Data  
Note:  
Digital input pins have Schmitt trigger input buffers.  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.2 April 2001  
2
WM8729  
Product Preview  
ABSOLUTE MAXIMUM RATINGS  
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at  
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical  
Characteristics at the test conditions specified.  
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible  
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage  
of this device.  
CONDITION  
MIN  
-0.3V  
MAX  
+7V  
Digital supply voltage  
Analogue supply voltage  
-0.3V  
+7V  
Voltage range digital inputs  
Voltage range analogue inputs  
Master Clock Frequency  
DGND -0.3V  
AGND -0.3V  
DVDD +0.3V  
AVDD +0.3V  
50MHz  
Operating temperature range, TA  
Storage temperature  
-25°C  
-65°C  
+85°C  
+150°C  
+220°C  
+183°C  
Package body temperature (soldering 10 seconds)  
Package body temperature (soldering 2 minutes)  
Note:  
Analogue and digital grounds must always be within 0.3V of each other.  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.2 April 2001  
3
WM8729  
Product Preview  
DC ELECTRICAL CHARACTERISTICS  
PARAMETER  
SYMBOL  
DVDD  
TEST CONDITIONS  
MIN  
3.0  
TYP  
MAX  
UNIT  
V
Digital supply range  
Analogue supply range  
Ground  
5.5  
5.5  
AVDD  
3.0  
V
AGND, DGND  
0
0
V
Difference DGND to AGND  
Analogue supply current  
Digital supply current  
Analogue supply current  
Digital supply current  
-0.3  
+0.3  
V
AVDD = 5V  
DVDD = 5V  
AVDD = 3.3V  
DVDD = 3.3V  
19  
8
mA  
mA  
mA  
mA  
18  
4
ELECTRICAL CHARACTERISTICS  
Test Conditions  
AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Digital Logic Levels (TTL Levels)  
Input LOW level  
VIL  
VIH  
0.8  
V
V
V
V
Input HIGH level  
2.0  
Output LOW  
VOL  
VOH  
IOL = 1mA  
IOH = 1mA  
AGND + 0.3V  
Output HIGH  
AVDD - 0.3V  
(VREFP -  
Analogue Reference Levels  
Reference voltage  
VMID  
(VREFP -  
(VREFP -  
V
VREFN)/2 - VREFN)/2 VREFN)/2 +  
50mV  
50mV  
Potential divider resistance  
RVMID  
12k  
ohms  
DAC Output (Load = 10k ohms. 50pF)  
0dBFs Full scale output voltage  
At DAC outputs  
1.1 x  
AVDD/5  
106  
Vrms  
dB  
SNR (Note 1,2,3)  
SNR (Note 1,2,3)  
SNR (Note 1,2,3)  
SNR (Note 1,2,3)  
A-weighted,  
@ fs = 48kHz  
A-weighted  
@ fs = 96kHz  
A-weighted  
100  
106  
106  
105  
dB  
dB  
@ fs = 192kHz  
A-weighted,  
dB  
@ fs = 48kHz  
AVDD, DVDD = 3.3V  
A-weighted  
@ fs = 96kHz  
AVDD, DVDD = 3.3V  
SNR (Note 1,2,3)  
SNR (Note 1,2,3)  
103  
106  
dB  
dB  
Non ‘A’ weighted @ fs  
= 48kHz  
THD (Note 1,2,3)  
1kHz, 0dBFs  
-97  
106  
100  
dB  
dB  
dB  
THD+N (Dynamic range, Note 2)  
DAC channel separation  
Analogue Output Levels  
Output level  
1kHz, -60dBFs  
100  
Load = 10k ohms,  
0dBFS  
1.1  
VRMS  
VRMS  
Load = 10k ohms,  
0dBFS,  
0.726  
(AVDD = 3.3V)  
Gain mismatch  
±1  
%FSR  
channel-to-channel  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.2 April 2001  
4
WM8729  
Product Preview  
Test Conditions  
AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Minimum resistance load  
To midrail or a.c.  
coupled  
1
kohms  
To midrail or a.c.  
coupled  
600  
ohms  
(AVDD = 3.3V)  
Maximum capacitance load  
Output d.c. level  
5V or 3.3V  
100  
pF  
V
(VREFP -  
VREFN)/2  
Power On Reset (POR)  
POR threshold  
2.4  
V
Notes:  
1. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’ weighted  
over a 20Hz to 20kHz bandwidth.  
2. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a  
filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical  
Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification  
values.  
3. VMID decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance).  
TERMINOLOGY  
1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no  
signal applied. (No Auto-zero or Automute function is employed in achieving these results).  
2. Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal. Normally a  
THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g.  
THD+N @ -60dB= -32dB, DR= 92dB).  
3. THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.  
4. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band).  
5. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the  
other. Normally measured by sending a full scale signal down one channel and measuring the other.  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.2 April 2001  
5
WM8729  
Product Preview  
MASTER CLOCK TIMING  
tMCLKL  
MCLK  
tMCLKH  
tMCLKY  
Figure 1 Master Clock Timing Requirements  
Test Conditions  
AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
System Clock Timing Information  
MCLK Master clock pulse width high  
MCLK Master clock pulse width low  
MCLK Master clock cycle time  
MCLK Duty cycle  
tMCLKH  
tMCLKL  
tMCLKY  
13  
13  
ns  
ns  
ns  
26  
40:60  
60:40  
DIGITAL AUDIO INTERFACE  
tBCH  
tBCL  
BCKIN  
LRCIN  
DIN  
tBCY  
tLRSU  
tDS  
tLRH  
tDH  
Figure 2 Digital Audio Data Timing  
Test Conditions  
AVDD, DVDD = 5V, AGND = 0V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Audio Data Input Timing Information  
BCKIN cycle time  
tBCY  
tBCH  
tBCL  
40  
16  
16  
8
ns  
ns  
ns  
ns  
BCKIN pulse width high  
BCKIN pulse width low  
LRCIN set-up time to  
BCKIN rising edge  
tLRSU  
LRCIN hold time from  
BCKIN rising edge  
tLRH  
tDS  
8
8
8
ns  
ns  
ns  
DIN set-up time to BCKIN  
rising edge  
DIN hold time from BCKIN  
rising edge  
tDH  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.2 April 2001  
6
WM8729  
Product Preview  
DEVICE DESCRIPTION  
INTRODUCTION  
The WM8729 is a high performance DAC designed for digital consumer audio applications. Its  
range of features make it ideally suited for use in DVD players, AV receivers and other high end  
consumer audio equipment.  
The WM8729 is a complete 2-channel stereo audio digital-to-analogue converter, including digital  
interpolation filter, multi-bit sigma delta with dither, and switched capacitor multi-bit stereo DAC  
and output smoothing filters. It is fully compatible and an ideal partner for a range of industry  
standard microprocessors, controllers and DSPs.  
Control of internal functionality of the device is provided by hardware control (pin programmed).  
Operation using master clocks of 256fs, 384fs, 512fs or 768fs is provided, selection between  
clock rates being automatically controlled. Sample rates (fs) from less than 8ks/s to 96ks/s are  
allowed, provided the appropriate system clock is input. Support is also provided for up to 192ks/s  
using a master clock of 128fs or 192fs.  
The audio data interface supports right justified or I2S (Philips left justified, one bit delayed)  
interface formats.  
The device is packaged in a small 16-pin SOIC.  
CLOCKING SCHEMES  
In a typical digital audio system there is only one central clock source producing a reference clock  
to which all audio data processing is synchronised. This clock is often referred to as the audio  
systems Master Clock. The external master clock can be applied directly through the MCLK input  
pin with no configuration necessary for sample rate selection.  
Note that on the WM8729, MCLK is used to derive clocks for the DAC path. The DAC path  
consists of DAC sampling clock, DAC digital filter clock and DAC digital audio interface timing. In  
a system where there are a number of possible sources for the reference clock it is recommended  
that the clock source with the lowest jitter be used to optimise the performance of the DAC.  
DIGITAL AUDIO INTERFACE  
Audio data is applied to the internal DAC filters via the Digital Audio Interface. Two popular  
interface formats are supported:  
Right Justified mode  
I2S mode  
Both formats send the MSB first. The WM8729 supports word lengths of 16 or 24 bits in I2S  
mode and 16 or 20 bits in right justified mode. In right justified and I2S modes, the digital audio  
interface receives data on the DIN input. Audio Data is time multiplexed with LRCIN indicating  
whether the left or right channel is present. LRCIN is also used as a timing reference to indicate  
the beginning or end of the data words.  
In right justified and I2S modes, the minimum number of BCKINs per LRCIN period is 2 times the  
selected word length. LRCIN must be high for a minimum of word length BCKINs and low for a  
minimum of word length BCKINs. Any mark to space ratio on LRCIN is acceptable provided the  
above requirements are met.  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.2 April 2001  
7
WM8729  
Product Preview  
RIGHT JUSTIFIED MODE  
In right justified mode, the LSB is sampled on the rising edge of BCKIN preceding a LRCIN  
transition. LRCIN is high during the left samples and low during the right samples.  
1/fs  
LEFT CHANNEL  
RIGHT CHANNEL  
LRCIN  
BCKIN  
DIN  
1
2
3
n
1
2
3
n
n-2 n-1  
n-2 n-1  
MSB  
LSB  
MSB  
LSB  
Figure 3 Right Justified Mode Timing Diagram  
I2S MODE  
In I2S mode, the MSB is sampled on the second rising edge of BCKIN following a LRCIN  
transition. LRCIN is low during the left samples and high during the right samples.  
1/fs  
LEFT CHANNEL  
RIGHT CHANNEL  
LRCIN  
BCKIN  
1 BCKIN  
1 BCKIN  
DIN  
1
2
3
n
1
2
3
n
n-2 n-1  
n-2 n-1  
LSB  
LSB  
MSB  
MSB  
Figure 4 I2S Mode Timing Diagram  
AUDIO DATA SAMPLING RATES  
The master clock for WM8729 supports audio sampling rates from 128fs to 768fs, where fs is the  
audio sampling frequency (LRCIN) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The  
master clock is used to operate the digital filters and the noise shaping circuits.  
The WM8729 has a master clock detection circuit that automatically determines the relation  
between the master clock frequency and the sampling rate (to within +/- 8 master clocks). If there  
is a greater than 8 clocks error, the interface shuts down the DAC and mutes the output. The  
master clock should be synchronised with LRCIN, although the WM8729 is tolerant of phase  
differences or jitter on this clock.  
SAMPLING  
RATE  
MASTER CLOCK FREQUENCY (MHZ) (MCLK)  
128fs  
192fs  
256fs  
384fs  
512fs  
768fs  
(LRCIN)  
32kHz  
44.1kHz  
48kHz  
4.096  
5.6448  
6.114  
6.144  
8.467  
8.192  
11.2896  
12.288  
24.576  
12.288  
16.9340  
18.432  
36.864  
16.384  
22.5792  
24.576  
24.576  
33.8688  
36.864  
9.216  
96kHz  
12.288  
24.576  
18.432  
36.864  
Unavailable Unavailable  
192kHz  
Unavailable Unavailable Unavailable Unavailable  
Table 1 Master Clock Frequencies Versus Sampling Rate  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.2 April 2001  
8
WM8729  
Product Preview  
HARDWARE CONTROL MODES  
The WM8729 is hardware programmable providing the user with options to select input audio data  
format, de-emphasis and mute.  
MUTE AND AUTOMUTE OPERATION  
Pin 14 (MUTEB) controls selection of MUTE directly, and can be used to enable and disable the  
automute function, or as an output of the automuted signal.  
MUTEB PIN  
DESCRIPTION  
0
1
Mute DAC channels  
Normal Operation  
Floating  
Enable IZD, MUTEB becomes an output to indicate when IZD occurs.  
Table 2 Mute and Automute Control  
1.5  
1
0.5  
0
-0.5  
-1  
-1.5  
-2  
-2.5  
0
0.001  
0.002  
0.003  
0.004  
0.005  
0.006  
Time(s)  
Figure 5 Application and Release of MUTEB  
The MUTEB pin is an input to select mute or not mute. MUTEB is active low; taking the pin low  
causes the filters to soft mute, ramping down the audio signal over a few milliseconds. Taking  
MUTEB high again allows data into the filter. Refer to Figure 5.  
The Infinite Zero Detect (IZD) function detects a series of zero value audio samples of 1024  
samples long being applied to both channels. After such an event, a latch is set whose output  
(AUTOMUTED) is connected through a 10kohm resistor to the MUTEB pin. Thus if the MUTEB  
pin is not being driven, the automute function will assert mute.  
If MUTEB is tied high, AUTOMUTED is overridden and will not mute. If MUTEB is driven from a  
bi-directional source, then both MUTE and automute functions are available. If MUTEB is not  
driven, AUTOMUTED appears as a weak output (10k source impedance) so can be used to drive  
external mute circuits. AUTOMUTED will be removed as soon as any channel receives a non-zero  
input.  
A diagram showing how the various Mute modes interact is shown below in Figure 6.  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.2 April 2001  
9
WM8729  
Product Preview  
AUTOMUTED  
(Internal Signal)  
10k  
MUTEB  
PIN  
SOFTMUTE  
(Internal Signal)  
Figure 6 Selection Logic for MUTE Modes  
INPUT FORMAT SELECTION  
FORMAT (pin 16) controls the data input format.  
FORMAT  
INPUT DATA MODE  
0
20-bit right justified (note 2)  
24-bit I2S (note 2)  
1
Table 3 Input Format Selection  
Notes:  
1. In 24 bit I2S mode, any width of 24 bits or more is supported provided that LRCIN is high for  
a minimum of 24 BCKINs and low for a minimum of 24 BCKINs, unless Note 2.  
2. If exactly 16 BCKIN cycles occur in both the low and high period of LRCIN the WM8729 will  
assume the data is 16 bit and accept the data accordingly.  
DE-EMPHASIS CONTROL  
DEM (pin 15) is an input control for selection of de-emphasis filtering to be applied.  
DEM  
DE-EMPHASIS  
0
Off  
On  
1
Table 4 De-emphasis Control  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.2 April 2001  
10  
WM8729  
Product Preview  
DIGITAL FILTER CHARACTERISTICS  
PARAMETER  
Passband Edge  
SYMBOL  
TEST CONDITIONS  
-3dB  
MIN  
TYP  
MAX  
UNIT  
0.487fs  
Passband Ripple  
f < 0.444fs  
f > 0.555fs  
±0.05  
dB  
dB  
Stopband Attenuation  
-60  
Table 5 Digital Filter Characteristics  
DAC FILTER RESPONSES  
0.2  
0.15  
0.1  
0
-20  
-40  
0.05  
0
-60  
-0.05  
-0.1  
-0.15  
-0.2  
-80  
-100  
-120  
0
0.5  
1
1.5  
2
2.5  
3
0
0.05  
0.1  
0.15  
0.2  
0.25  
0.3  
0.35  
0.4  
0.45  
0.5  
Frequency (Fs)  
Frequency (Fs)  
Figure 7 DAC Digital Filter Frequency Response  
-44.1, 48 and 96kHz  
Figure 8 DAC Digital Filter Ripple -44.1, 48 and 96kHz  
0.2  
0
0
-20  
-40  
-60  
-80  
-0.2  
-0.4  
-0.6  
-0.8  
-1  
0
0.2  
0.4  
0.6  
0.8  
1
0
0.05  
0.1  
0.15  
0.2  
0.25  
0.3  
0.35  
0.4  
0.45  
0.5  
Frequency (Fs)  
Frequency (Fs)  
Figure 9 DAC Digital Filter Frequency Response -192kHz  
Figure 10 DAC Digital Filter Ripple -192kHz  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.2 April 2001  
11  
WM8729  
Product Preview  
DIGITAL DE-EMPHASIS CHARACTERISTICS  
0
1
0.5  
0
-2  
-4  
-0.5  
-1  
-6  
-1.5  
-2  
-8  
-2.5  
-3  
-10  
0
2
4
6
8
10  
12  
14  
16  
0
2
4
6
8
10  
12  
14  
16  
Frequency (kHz)  
Frequency (kHz)  
Figure 11 De-Emphasis Frequency Response (32kHz)  
Figure 12 De-Emphasis Error (32kHz)  
0
0.4  
0.3  
0.2  
0.1  
0
-2  
-4  
-6  
-0.1  
-0.2  
-0.3  
-0.4  
-8  
-10  
0
5
10  
15  
20  
0
5
10  
15  
20  
Frequency (kHz)  
Frequency (kHz)  
Figure 13 De-Emphasis Frequency Response (44.1kHz)  
Figure 14 De-Emphasis Error (44.1kHz)  
0
1
0.8  
0.6  
0.4  
0.2  
0
-2  
-4  
-6  
-0.2  
-0.4  
-0.6  
-0.8  
-1  
-8  
-10  
0
5
10  
15  
20  
0
5
10  
15  
20  
Frequency (kHz)  
Frequency (kHz)  
Figure 15 De-Emphasis Frequency Response (48kHz)  
Figure 16 De-Emphasis Error (48kHz)  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.2 April 2001  
12  
WM8729  
Product Preview  
RECOMMENDED EXTERNAL COMPONENTS  
DVDD  
6
AVDD  
+
9
DVDD  
DGND  
AVDD  
+
13  
C1  
C2  
VREFP  
5
C3  
C4  
C5  
8
AGND  
DGND  
12  
VREFN  
AGND  
16  
15  
14  
FORMAT  
DEM  
Hardware Control  
MUTEB  
C6  
7
VOUTR  
VOUTL  
AC-Coupled  
VOUTR/L  
to External LPF  
WM8729  
C7  
10  
1
4
LRCIN  
MCLK  
3
2
Audio Serial Data I/F  
BCKIN  
DIN  
11  
VMID  
+
C8  
C9  
AGND  
Notes:  
1. AGND and DGND should be connected as close to the WM8729 as possible.  
2. C2, C3, C4 and C8 should be positioned as close to the WM8729 as possible.  
3. Capacitor types should be carefully chosen. Capacitors with very low ESR are  
recommended for optimum performance.  
Figure 17 External Component Diagram  
RECOMMENDED EXTERNAL COMPONENTS VALUES  
COMPONENT  
REFERENCE  
SUGGESTED  
VALUE  
DESCRIPTION  
C1 and C5  
C2 to C4  
C6 and C7  
C8  
10µF  
0.1µF  
10µF  
0.1µF  
10µF  
De-coupling for DVDD and AVDD/VREFP  
De-coupling for DVDD and AVDD/VREFP  
Output AC coupling caps to remove midrail DC level from outputs.  
Reference de-coupling capacitors for VMID pin.  
C9  
Table 6 External Components Description  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.2 April 2001  
13  
WM8729  
Product Preview  
RECOMMENDED ANALOGUE LOW PASS FILTER (OPTIONAL)  
4.7k  
4.7k  
+VS  
_
51  
10uF  
1.8k  
7.5K  
+
+
-VS  
1.0nF  
680pF  
47k  
Figure 18 Recommended Low Pass Filter (Optional)  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.2 April 2001  
14  
WM8729  
Product Preview  
PACKAGE DRAWING  
DM012.B  
D: 16 PIN SOIC 3.9mm Body  
e
B
16  
9
E
H
1
8
D
L
h x 45o  
A1  
SEATING PLANE  
-C-  
α
A
C
0.10 (0.004)  
Dimensions  
(mm)  
Dimensions  
(Inches)  
Symbols  
MIN  
1.35  
0.10  
0.33  
0.19  
9.80  
3.80  
MAX  
1.75  
0.25  
0.51  
0.25  
10.00  
4.00  
MIN  
MAX  
A
A1  
B
C
D
E
0.0532  
0.0040  
0.0130  
0.0075  
0.3859  
0.1497  
0.0688  
0.0098  
0.0200  
0.0098  
0.3937  
0.1574  
e
1.27 BSC  
0.05 BSC  
H
h
L
5.80  
0.25  
0.40  
0o  
6.20  
0.50  
1.27  
8o  
0.2284  
0.0099  
0.0160  
0o  
0.2440  
0.0196  
0.0500  
8o  
α
REF:  
JEDEC.95, MS-012  
NOTES:  
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS (INCHES).  
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.  
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM (0.010IN).  
D. MEETS JEDEC.95 MS-012, VARIATION = AC. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.2 April 2001  
15  
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