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XWM8733ED

型号：

XWM8733ED

描述：

102分贝立体声DAC[ 102dB Stereo DAC ]

品牌：

WOLFSON[ WOLFSON MICROELECTRONICS PLC ]

页数：

11 页

PDF大小：

366 K

下载PDF手册
WM8733  
102dB Stereo DAC  
Product Preview, July 2000, Rev 1.3  
DESCRIPTION  
FEATURES  
WM8733 is a high performance stereo DAC designed for use in  
portable audio equipment, video CD players and similar  
applications. It comprises selectable normal or I2S compatible  
serial data interfaces for 16 to 24-bit inputs, high performance  
digital filters, and sigma-delta output DACs, achieving an 102dB  
signal-to-noise ratio.  
•
•
•
High tolerance to clock jitter  
Compatible with PCM1733  
Distortion > 90dB, SNR > 102dB, dynamic range  
performance > 100dB  
•
•
Stereo DAC with input sampling from 8kHz to 96kHz  
Additional mute feature and high performance  
differential modes  
The device is available in a 14-pin SOIC package that offers  
selectable mute and de-emphasis functions using a minimum of  
external components.  
•
•
•
•
•
•
Normal or I2S compatible data format  
Sigma-delta design with 64x oversampling  
System clock 256fs or 384fs or 512fs  
Supply range 3V to 5V  
Low supply voltage operation and low current consumption are  
valuable features, particularly for use in portable equipment.  
Analogue voltage output to drive 2kΩ load  
14-pin SOIC package  
Additional modes consist of a powerdown option and the  
possibility of generating separate differential left and right  
outputs for applications demanding higher performance.  
APPLICATIONS  
•
High performance consumer audio  
BLOCK DIAGRAM  
SEL[0] SEL[1] MODE  
0
0
1
1
0
1
0
1
Normal stereo  
Power down  
Left only differential output  
Right only differential output  
SEL[0] (4)  
SEL[1] (11)  
WM8733  
FORMAT (13)  
SCKI (14)  
LRCIN (1)  
DIN (2)  
DIGITAL  
SIGMA-DELTA  
MODULATOR  
SWITCHED  
CAPACITOR  
DAC  
(6) VOUTR  
(9) VOUTL  
SERIAL  
INTERFACE  
DIGITAL  
FILTERS  
DIGITAL  
SIGMA-DELTA  
MODULATOR  
SWITCHED  
CAPACITOR  
DAC  
BCKIN (3)  
10k  
INFINITE  
ZERO  
DETECT  
DIGITAL  
VDD  
DIGITAL  
GND  
Wired  
OR  
(8)  
VDD  
(5)  
CAP  
(7)  
GND  
(12) (10)  
DEEMPH MUTE  
WOLFSON MICROELECTRONICS LTD.  
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK  
Tel: +44 (0) 131 667 9386  
Product Preview data sheets contain  
specifications for products in the formative  
phase of development. These products may  
be changed or discontinued without notice.  
Fax: +44 (0) 131 667 5176  
Email: sales@wolfson.co.uk  
http://www.wolfson.co.uk  
2000 Wolfson Microelectronics Ltd.  
WM8733  
Product Preview  
PIN CONFIGURATION  
ORDERING INFORMATION  
DEVICE  
TEMP. RANGE  
PACKAGE  
LRCIN  
DIN  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
SCKI  
XWM8733ED  
-25 to +85oC  
14-pin SOIC  
FORMAT  
DEEMPH  
SEL1  
BCKIN  
SEL0  
CAP  
WM8733  
MUTE  
VOUTL  
VDD  
VOUTR  
GND  
8
ABSOLUTE MAXIMUM RATINGS  
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating  
at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical  
Characteristics at the test conditions specified  
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible  
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage  
of this device.  
CONDITION  
MIN  
MAX  
Supply voltage  
Reference input  
-0.3V  
+7.0V  
VDD+0.3V  
-25oC  
-65oC  
+85oC  
+150oC  
+260oC  
+183oC  
Operating temperature range, TA  
Storage temperature  
Lead temperature (soldering, 10 seconds)  
Lead temperature (soldering, 2 minutes)  
RECOMMENDED OPERATING CONDITIONS  
PARAMETER  
Supply range  
SYMBOL  
VDD  
TEST CONDITIONS  
MIN  
TYP  
MAX  
+10%  
UNIT  
V
-10%  
3.0 to 5.0  
Ground  
GND  
0
V
Supply current  
VDD = 5V  
15  
mA  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.3 July 2000  
2
Product Preview  
WM8733  
ELECTRICAL CHARACTERISTICS  
Test Characteristics  
VDD = 5V, GND = 0V, TA = +25oC, fs = 44.1kHz, SCKI = 384fs unless otherwise stated.  
PARAMETER  
Digital Logic Levels  
Input LOW level  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
VIL  
VIH  
0.8  
V
V
Input HIGH level  
2.0  
Analogue Output Levels  
Output level  
Into 10kohm, full scale 0dB,  
(5V supply)  
1
VRMS  
VRMS  
Into 10kohm, full scale 0dB,  
(3V supply)  
0.6  
Minimum resistance load  
o midrail or AC coupled (5V supply)  
o midrail or AC coupled (3V supply)  
5V or 3V  
2
10  
10  
kohms  
kohms  
pF  
Maximum capacitance load  
Output DC level  
100  
VDD/2  
V
Reference Levels  
Potential divider resistance  
Voltage at CAP  
80  
100  
120  
kohms  
VDD to CAP and CAP to GND  
VDD/2  
DAC Circuit Specifications  
SNR (Note 1) Stereo mode  
Mono mode  
VDD = 5V  
VDD = 3V  
98  
96  
102  
100  
dB  
dB  
Stereo mode  
dB  
Mono mode  
dB  
THD (full scale)  
0dB  
0.03  
-40  
0.01  
%
THD+N  
-60dB  
-35  
0
dB  
Frequency response  
Pass band ripple  
20,000  
Hz  
±0.25  
dB  
Transition band  
20,000  
Hz  
Out of band rejection  
-40  
dB  
Dynamic  
Range  
Stereo mode  
Mono mode  
100  
dB  
dB  
Channel Separation  
90  
±1  
dB  
Gain mismatch  
±5  
%FSR  
channel-to-channel  
Audio Data Input and System Clock Timing Information  
BCKIN pulse cycle time  
BCKIN pulse width high  
BCKIN pulse width low  
tBCY  
tBCH  
tBCL  
tBL  
100  
50  
ns  
ns  
ns  
ns  
50  
BCKIN rising edge to LRCIN  
edge  
30  
LRCIN rising edge to BCKIN  
rising edge  
tLB  
30  
ns  
DIN setup time  
tDS  
tDH  
tSCKIH  
tSCKIL  
30  
30  
13  
13  
ns  
ns  
ns  
ns  
DIN hold time  
System clock pulse width high  
System clock pulse width low  
Note 1 Ratio of RMS output level with 1kHz full scale input, to the RMS output level with all zeros into the digital input, measured  
“A” weighted over a 20Hz to 20kHz bandwidth.  
Note 2 All performance measurements done with 20kHz low pass filter. Failure to use such a filter will result in higher THD+N  
and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes  
out of band noise; although it is not audible it may affect dynamic specification values.  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.3 July 2000  
3
WM8733  
Product Preview  
PIN DESCRIPTION  
PIN  
1
NAME  
LRCIN  
TYPE  
Digital input  
Digital input  
Digital input  
Digital input  
Analogue output  
Analogue output  
Supply  
DESCRIPTION  
Sample rate clock input  
Serial data input  
2
DIN  
3
BCKIN  
SEL0  
Bit clock input  
4
Mode select (internal pull-down)  
Analogue internal reference  
Right channel DAC output  
0V supply  
5
CAP  
6
VOUTR  
GND  
7
8
VDD  
Supply  
Positive supply  
9
VOUTL  
MUTE  
SEL1  
Analogue output  
Digital input  
Digital input  
Digital input  
Left channel DAC output  
10  
11  
12  
Soft mute control; high = muted, Z = auto mute input/output  
Mode select (internal pull-down)  
DEEMPH  
De-emphasis select; high = de-emphasis ON (44.1kHz only), (internal  
pull-up)  
13  
FORMAT  
Digital input  
Data input format select; ‘lo’ = normal, ‘hi’ = I2S (internal pull-up)  
14  
SCKI  
Digital input  
System clock input (256fs or 384fs or 512fs)  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.3 July 2000  
4
Product Preview  
WM8733  
DEVICE DESCRIPTION  
INTRODUCTION  
WM8733 is a complete high performance stereo audio 18-bit digital-to-analogue converter, including  
digital interpolation filter, multibit sigma-delta with dither, and switched capacitor multibit stereo DAC  
and output smoothing filters.  
Special functions of soft mute and de-emphasis are provided, and operation using system clock of  
256fs, or 384fs or 512fs is provided, selection between either clock rate being automatically  
controlled. Sample rates (fs) from less than 8ks/s to 96ks/s are allowed, provided the appropriate  
system clock is input.  
An auto mute function is provided which is enabled if MUTE (pin 10) is left at high impedance. If 64  
successive left and right channel data samples of value 0 are received, auto mute is achieved. This  
signal is wire ORed to MUTE (pin 10) via 10K resistor. If MUTE (pin 10) internally is not externally  
driven, the internal auto mute state is visible on this pin as a weak drive strength signal (10kΩ  
source).  
MUTE  
DESCRIPTION  
Soft mute is OFF  
0
Z
1
Auto mute is enabled  
Soft mute is ON  
Table 1 Soft Mute Control  
A novel multi bit sigma-delta DAC design is used, utilising a 64x oversampling rate, to optimise  
signal to noise performance and offer increased clock jitter tolerance.  
Internally generated midrail references are used to DC bias output signals, requiring only a single  
external capacitor for decoupling purposes.  
The device is packaged in a small 14-pin SOIC package, offering pin compatibility with Burr Brown  
PCM1733, but with added functionality of a soft mute input pin, which may be left floating to enable  
auto mute detection, or held ‘low’ leaving the device operational.  
Single 3V to 5V supplies may be used, the output amplitude scaling with absolute supply level. Low  
supply voltage operation and low current consumption, and the low pin count small package, make  
the WM8733 attractive for many consumer type applications.  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.3 July 2000  
5
WM8733  
Product Preview  
DAC CIRCUITS  
The WM8733 DACs are designed to allow playback of 18-bit PCM audio or similar data with high  
resolution and low noise and distortion. Sample rates up to 96ks/s may be used, with much lower  
sample rates acceptable provided that the ratio of sample rate (LRCIN) to system clock is maintained  
at the required 256fs, or 384fs or 512fs times.  
The DACs on WM8733 are implemented using sigma-delta oversampled conversion techniques.  
These require that the PCM samples are digitally filtered and interpolated to generate a set of  
samples at a much higher rate than the input rate. This sample stream is then digitally modulated to  
generate a digital pulse stream that is then converted to analogue signals in a switched capacitor  
DAC. The advantage of this technique is that the DAC is linearised using noise shaping techniques,  
allowing the 16-bit resolution to be met using non-critical analogue components. A further advantage  
is that the high sample rate at the DAC output means that smoothing filters on the output of the DAC  
need only have fairly crude characteristics in order to remove the characteristic steps, or images, on  
the output of the DAC. In order to ensure that generation of tones characteristic to sigma-delta  
convertors is not a problem, dithering is used in the digital modulator, and a higher order modulator is  
used. The switched capacitor technique used in the DAC reduces sensitivity to clock jitter compared  
to switched current techniques used in other implementations.  
De-emphasis of 44.1kHz signals may be applied if required.  
DEEMPH  
DESCRIPTION  
0
1
De-emphasis is OFF  
De-emphasis is ON  
(44.1kHz only)  
Table 2 De-emphasis Control  
The voltage on the CAP pin is used as the reference for the DACs, therefore the amplitude of the  
signals at the DAC outputs will scale with the amplitude of the voltage at the CAP. An external  
reference could be used to drive in on the CAP pin if desired, but a value typically of about midrail  
should be used for optimum performance.  
The outputs of the 2 DACs are buffered out of the device by buffer amplifiers. These amplifiers will  
source load current of several mA and sink current up to 1.5mA, so allowing significant loads to be  
driven. The output source is active, the sink is Class A, i.e. fixed value, so greater loads might be  
driven if an external ‘pull-down’ resistor is connected at the output.  
Typically an external low pass filter circuit will be used to remove residual sampling noise of the 64x  
oversampling used and if desired adjust the signal amplitude and device strength.  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.3 July 2000  
6
Product Preview  
WM8733  
SERIAL DATA INTERFACE  
WM8733 has serial interface formats that are fully compatible with both normal (MSB first, right-  
justified) and I2S interfaces. The data format is selected with the FORMAT pin. When FORMAT is  
LOW, normal data format is selected. When the format is HIGH, I2S format is selected.  
If the application demands 16-bit or 20-bit data, then I2S format may be used. Two LSBs will be lost  
in 20-bit mode. Normal mode will support 18-bit data applications or 16-bit packed mode applications  
(automatically detected).  
Note: In 16-bit “packed” mode operation (exactly 32 BLCKS per LRCIN period) the data word must  
align exactly with LRCIN clock edges (effectively both left and right justified at the same time).  
FORMAT  
DESCRIPTION  
Normal format (MSB-first, right justified)  
I2S format (Philips serial data protocol)  
0
1
Table 3 Serial Interface Formats  
1/fs  
LEFT CHANNEL  
RIGHT CHANNEL  
LRCIN  
BCKIN  
1
2
3
16 17 18  
LSB  
1
2
3
16 17 18  
LSB  
DIN  
AUDIO DATA WORD = 18-BIT  
MSB  
MSB  
Figure 1 ‘Normal’ Data Input Timing  
1/fs  
LEFT CHANNEL  
RIGHT CHANNEL  
LRCIN  
BCKIN  
18  
18  
16 17  
1
2
3
16 17  
1
2
3
DIN  
MSB  
LSB  
MSB  
LSB  
AUDIO DATA WORD = 18-BIT  
Figure 2 I2S Data Input Timing  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.3 July 2000  
7
WM8733  
Product Preview  
1/fs  
LEFT CHANNEL  
RIGHT CHANNEL  
LRCIN  
BCKIN  
DIN  
15 16  
1
2
3
14 15 16  
1
2
3
14 15 16  
LSB  
1
AUDIO DATA WORD = 16-BIT  
MSB  
LSB MSB  
Figure 3 16-bit Normal Packed Mode  
1/fs  
LEFT CHANNEL  
RIGHT CHANNEL  
LRCIN  
BCKIN  
DIN 17 18  
AUDIO DATA WORD = 18-BIT  
1
2
3
16 17 18  
1
2
3
16 17 18  
LSB  
1
MSB  
LSB MSB  
Figure 4 18-bit Normal Packed Mode  
MODE SELECT PINS  
The WM8733 has four possible modes.  
SEL0  
SEL1  
MODE  
0
0
1
1
0
1
0
1
Normal stereo operation  
Power down  
Left only differential output  
Right only differential output  
Table 4 Mode Select Pins  
The SEL0/1 pins (pins 4 and 11) can be hard wired, or left floating as internal “pull-downs” will cause  
the device to operate in normal stereo mode.  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.3 July 2000  
8
Product Preview  
WM8733  
SYSTEM CLOCK  
The system clock is used to operate the digital filters and the noise shaping circuits. The system  
clock input is at pin 14 (SCKI). The frequency of WM8733’s system clock should be set to 256fs or  
384fs or 512fs, (where fs is the audio sampling frequency). The sample rate is typically: 32 kHz, 44.1  
kHz, 48 kHz or 96kHz.  
WM8733 has a system clock detection circuit that automatically determines whether the system  
clock being supplied is at 256fs or 384fs or 512fs. The system clock should be synchronised with  
LRCIN, but WM8733 is tolerant of phase differences. Severe distortion in the phase difference  
between LRCIN and the system clock will be detected, and cause the device to automatically  
resynchronise. During resynchronisation, the output of the device will either repeat the previous  
sample, or drop the next sample, depending on the nature of the phase slip. This will ensure minimal  
“click“ at the analog outputs during resynchronisation.  
tSCKIH  
SCKI  
tSCKIL  
Figure 5 System Clock Timing Requirements  
SYSTEM CLOCK FREQUENCY (MHz)  
SAMPLING RATE  
(LRCIN)  
256fs  
384fs  
512fs  
32 kHz  
8.192  
12.288  
16.384  
44.1 kHz  
48 kHz  
96kHz  
11.2896  
12.288  
24.576  
16.9340  
18.432  
36.864  
22.5792  
24.576  
49.152  
Table 5 System Clock Frequencies Versus Sampling Rate  
LRCIN  
tBCH  
tBCL  
tLB  
BCKIN  
DIN  
tBL  
tBCY  
tDS  
tDH  
Figure 6 Audio Data Input Timing  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.3 July 2000  
9
WM8733  
Product Preview  
RECOMMENDED EXTERNAL COMPONENTS  
1
256fs/384fs/512fs CLK  
14  
13  
SCKI  
LRCIN  
FROM AUDIO  
PROCESSOR  
2
3
4
DIN  
FORMAT  
BCKIN  
SEL0  
CAP  
DEEMPH 12  
WM8733  
SEL1 11  
MUTE 10  
(diode allows automute operation)  
10µF  
+
5
6
ANALOGUE  
ANALOGUE  
OUTPUT FOR  
LEFT CHANNEL  
OUTPUT FOR  
RIGHT  
External  
LPF  
External  
LPF  
VOUTR  
GND  
VOUTL  
VDD  
9
8
CHANNEL  
7
GND  
10µF  
0.1µF  
VDD  
Figure 5 Applications Diagram  
DETAIL OF APPLICATION DIAGRAM SHOWING THE EXTERNAL LOW POWER FILTER  
External LPF  
x2 for Stereo Operation  
-
Filtered  
Analogue  
Output  
1500pF  
10k  
+
10k  
Vin  
Ω
10kΩ  
Ω
+
-
680pF  
100pF  
Figure 6 Third-Order Low Pass Filter (LPF) Example  
An external low pass filter is recommended if the device is driving a wide band amplifier, as shown in  
Figure 6. In some applications, second-order or passive RC filter may be adequate.  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.3 July 2000  
10  
Product Preview  
WM8733  
PACKAGE DIMENSIONS  
DM001.C  
D: 14 PIN SOIC 3.9mm Wide Body  
e
B
14  
8
H
E
1
7
D
L
h x 45o  
A1  
SEATING PLANE  
-C-  
α
C
A
0.10 (0.004)  
Dimensions  
(MM)  
Dimensions  
(Inches)  
Symbols  
MIN  
MAX  
1.75  
0.25  
0.51  
0.25  
8.75  
4.00  
MIN  
MAX  
A
A1  
B
C
D
E
1.35  
0.10  
0.33  
0.19  
8.55  
3.80  
0.0532  
0.0040  
0.0130  
0.0075  
0.3367  
0.1497  
0.0688  
0.0098  
0.0200  
0.0098  
0.3444  
0.1574  
e
1.27 BSC  
0.05 BSC  
H
h
L
5.80  
0.25  
0.40  
0o  
6.20  
0.50  
1.27  
8o  
0.2284  
0.0099  
0.0160  
0o  
0.2440  
0.0196  
0.0500  
8o  
α
REF:  
JEDEC.95, MS-012  
NOTES:  
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS (INCHES).  
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.  
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM (0.010IN).  
D. MEETS JEDEC.95 MS-012, VARIATION = AB. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.3 July 2000  
11  
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