Advanced Information
WM9708
The datastreams currently defined by the AC’97 specification include:
PCM playback - 2 output slots
PCM record data - 2 input slots
Control - 2 output slots
2-channel composite PCM output stream
2-channel composite PCM input stream
Control Register write port
Status - 2 input slots
Control Register read port
Optional modem line codec output -
1 output slot
Modem line codec DAC input stream
Optional modem line codec input –
Modem line codec ADC output stream
1 input slot
Optional dedicated microphone input -
1 input slot
Dedicated microphone input stream in support
of stereo AEC and/or other voice applications.
Synchronisation of all AC-link data transactions is signalled by the WM9708 controller. The WM9708
drives the serial bit clock onto AC-link, which the AC’97 controller then qualifies with
a
synchronisation signal to construct audio frames.
SYNC, fixed at 48kHz, is derived by dividing down the serial clock (BITCLK). BITCLK, fixed at
12.288MHz, provides the necessary clocking granularity to support 12, 20-bit outgoing and incoming
time slots and the tag slot. AC-link serial data is transitioned on each rising edge of BITCLK. The
receiver of AC-link data, (WM9708 for outgoing data and AC’97 controller for incoming data),
samples each serial bit on the falling edges of BITCLK.
The AC-link protocol provides for a special 16-bit time slot (slot 0) wherein each bit conveys a valid
tag for its corresponding time slot within the current audio frame. A 1 in a given bit position of slot 0
indicates that the corresponding time slot within the current audio frame has been assigned a data
stream, and contains valid data. If a slot is tagged invalid, it is the responsibility of the source of the
data, (the WM9708 for the input stream, AC’97 controller for the output stream), to stuff all bit
positions with 0s during that slot’s active time.
SYNC remains high for a total duration of 16 BITCLKs at the beginning of each audio frame.
The portion of the audio frame where SYNC is high is defined as the Tag Phase. The remainder of
the audio frame where SYNC is low is defined as the Data Phase. Additionally, for power savings, all
clock, sync, and data signals can be halted. This requires that the WM9708 be implemented as a
static design to allow its register contents to remain intact when entering a power savings mode.
AC-LINK AUDIO OUTPUT FRAME (SDATA_OUT)
The audio output frame data streams correspond to the multiplexed bundles of all digital output data
targeting the WM9708’s DAC inputs, and control registers. As briefly mentioned earlier, each audio
output frame supports up to 12 20-bit outgoing data time slots. Slot 0 is a special reserved time slot
containing 16-bits, which are used for AC-link protocol infrastructure.
OUTPUT TAG SLOT (16-BITS)
Bit (15)
Bit (14)
Bit (13)
Bit (12:3)
Bit 2
Frame Valid
Slot 1 Valid Command Address bit
Slot 2 Valid Command Data bit
Slot 3-12 Valid bits as defined by AC’97
Reserved
(Primary Codec only)
(Primary Codec only)
(Set to 0)
Bit (1:0)
2-bit Message ID field
(00 reserved for Primary; 01
indicates Secondary)
Within slot 0 the first bit is a global bit (SDATAOUT slot 0, bit 15) which flags the validity for the entire
audio frame. If the Valid Frame bit is a 1, this indicates that the current audio frame contains at least
one time slot of valid data. The next 12-bit positions sampled by the WM9708 indicate which of the
corresponding 12 time slots contain valid data. It should be noted that in URA, even when slot 1 is
tagged as invalid, the request bits are still valid.
In this way data streams of differing sample rates can be transmitted across AC-link at its fixed
48kHz audio frame rate. Figure 9 illustrates the time slot based AC-link protocol.
WOLFSON MICROELECTRONICS LTD
AI Rev 2.0 April 2001
13
