NX25P40-VNI-C,PDF,NX25P40-VNI-C PDF资料,Datasheet,下载NX25P40-VNI-C技术资料

PRELIMINARY

APRIL2005

1M-BIT, 2M-BIT AND 4M-BIT

Serial Flash Memory with 40MHz SPI

NX25P10, NX25P20 AND NX25P40

NexFlashTechnologies, Inc.

1

PRELIMINARY MKP-0009 Rev 6 NXSF040I-0405

04/04/05 ©

1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI

NX25P10,NX25P20ANDNX25P40

Table of Contents

NX25P10, NX25P20 AND NX25P40

1M-BIT, 2M-BIT AND 4M-BIT Serial Flash Memory with 40MHz SPI ........................................................................... 1

FEATURES..................................................................................................................................................................... 4

GENERAL DESCRIPTION ............................................................................................................................................. 4

8-Pin SOIC 150-mil (Package Code N)..........................................................................................................................4

Figure 1. NX25P10, NX25P20 and NX25P40 Block Diagram .................................................................................... 5

PIN DESCRIPTIONS ...................................................................................................................................................... 6

PackageTypes ......................................................................................................................................................... 6

Serial Data Input (DI) ................................................................................................................................................ 6

Serial Data Output (DO) ............................................................................................................................................6

Serial Clock (CLK) .................................................................................................................................................... 6

Chip Select (CS) ....................................................................................................................................................... 6

Hold (HOLD) ............................................................................................................................................................. 6

Write Protect (WP).................................................................................................................................................... 6

Figure 2.NX25P10, NX25P20 and NX25P40 Pin Assignments, 8-pin SOIC (Package Code N) ................................6

Table 1.Pin Descriptions .......................................................................................................................................... 6

SPI OPERATION ............................................................................................................................................................ 7

SPI Modes ............................................................................................................................................................... 7

Hold Function ...........................................................................................................................................................7

WRITE PROTECTION .................................................................................................................................................... 7

Write Protect Features.............................................................................................................................................. 7

STATUS REGISTER....................................................................................................................................................... 8

BUSY .......................................................................................................................................................................8

Write Enable Latch (WEL).........................................................................................................................................8

Figure 3. Status Register Bit Locations..................................................................................................................... 8

Block Protect Bits (BP2, BP1, BP0) ......................................................................................................................... 8

Reserved Bits ...........................................................................................................................................................8

Status Register Protect (SRP) .................................................................................................................................. 8

Table 2:Status Register Memory Protection ............................................................................................................. 9

INSTRUCTIONS ........................................................................................................................................................... 10

Table 3: Instruction Set ........................................................................................................................................... 10

Table 4:Manufacturer and Device Identification ...................................................................................................... 10

Write Enable (06h).................................................................................................................................................... 11

Figure 4.Write Enable Instruction Sequence Diagram ............................................................................................. 11

Write Disable (04h) ................................................................................................................................................... 11

Figure 5.Write Disable Instruction Sequence Diagram ............................................................................................ 11

Read Status Register (05h) ...................................................................................................................................... 12

Figure 6. Read Status Register Instruction Sequence Diagram ............................................................................... 12

Write Status Register (01h) ...................................................................................................................................... 13

Figure 7.Write Status Register Instruction Sequence Diagram ............................................................................... 13

Read Data (03h) ........................................................................................................................................................ 14

Figure 8. Read Data Instruction Sequence Diagram ................................................................................................ 14

2

NexFlashTechnologies, Inc.

PRELIMINARY MKP-0009 Rev 6 NXSF040I-0405

04/04/05 ©

1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI

NX25P10,NX25P20ANDNX25P40

Table of Contents

1

Fast Read (0Bh) ........................................................................................................................................................ 15

Figure 9.Fast Read Instruction Sequence Diagram ................................................................................................ 15

Page Program (02h) ................................................................................................................................................. 16

Figure 10.Page Program Instruction Sequence Diagram ........................................................................................ 16

2

Sector Erase (D8h) ................................................................................................................................................... 17

Figure 11. Sector Erase Instruction Sequence Diagram .......................................................................................... 17

Bulk Erase (C7h) ...................................................................................................................................................... 18

Figure 12. Bulk Erase Instruction Sequence Diagram ............................................................................................. 18

3

Power-down (B9h) .................................................................................................................................................... 19

Figure 13.Deep Power-down Instruction Sequence Diagram ................................................................................... 19

4

Release Power-down / Device ID (ABh)................................................................................................................... 20

Figure 14.Release Power-down Instruction Sequence ............................................................................................ 20

Figure 15.Release Power-down / Device ID Instruction Sequence Diagram ............................................................ 20

Read Manufacturer / Device ID (90h) ....................................................................................................................... 21

Figure 16. Read Manufacturer / Device ID Diagram ................................................................................................ 21

5

SPECIFICATIONS ANDTIMING DIAGRAMS ............................................................................................................... 22

Table 5. Absolute Maximum Ratings ....................................................................................................................... 22

Table 6.Operating Ranges ...................................................................................................................................... 22

Table 7.Power-upTiming andWrite InhibitThreshold .............................................................................................. 22

Figure 17.Power-upTiming andVoltage Levels....................................................................................................... 22

Table 8.DC Electrical Characteristics (Preliminary) ................................................................................................ 23

Table 9.AC Measurement Conditions ..................................................................................................................... 23

Figure 18.AC Measurement I/O Waveform ............................................................................................................. 23

Table 10.AC Electrical Characteristics (Preliminary)............................................................................................... 24

Figure 19.Serial OutputTiming ............................................................................................................................... 25

Figure 20.InputTiming ........................................................................................................................................... 25

Figure 21.HoldTiming ............................................................................................................................................ 25

6

7

8

PACKAGING INFORMATION ........................................................................................................................................ 26

8-Pin SOIC 150-mil (Package Code N) ....................................................................................................................... 26

9

PRELIMINARY DESIGNATION .................................................................................................................................... 27

IMPORTANT NOTICE ................................................................................................................................................... 27

ORDERING INFORMATION ......................................................................................................................................... 27

LIFE SUPPORT POLICY ............................................................................................................................................. 27

TRADEMARKS ............................................................................................................................................................. 27

Document Revision History ........................................................................................................................................ 28

10

11

12

NexFlashTechnologies, Inc.

3

PRELIMINARY MKP-0009 Rev 6 NXSF040I-0405

04/04/05 ©

1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI

NX25P10,NX25P20ANDNX25P40

FEATURES

GENERAL DESCRIPTION

•

1M / 2M / 4M-bit Serial Flash Memories

The NX25P10 (1M-bit), NX25P20 (2M-bit) and NX25P40

(4M-bit) Serial Flash memories provide a storage solution

for systems with limited space, pins and power. They are

ideal for code download applications as well as storing

voice, text and data. The devices operate on a single 2.7V

to 3.6V power supply with current consumption as low as

4mAactiveand1µAforpower-down.Alldevicesareoffered

in space-saving 8-pin SOIC type packages as shown

below. Contact NexFlash for availability of alternate pack-

ages. As part of a family of Serial Flash products,

NexFlashalsoprovidesacompatiblemigrationpathto8M/

16M/32M-bitdensities.

• Family of Serial Flash Memories

– NX25P10: 1M-bit / 128K-byte (131,072 ) 512 pages

– NX25P20: 2M-bit / 256K-byte (262,144 ) 1024 pages

– NX25P40: 4M-bit / 512K-byte (524,288 ) 2048 pages

– 256-bytesperprogrammablepage

– Compatiblemigrationpathto8M/16M/32M-bit

•

4-pin SPI Serial Interface

– Clock, Chip Select, Data In, Data Out

– Easily interfaces to popular microcontrollers

– Compatible with SPI Modes 0 and 3

– Optional Hold function for SPI flexibility

TheNX25P10/20/40arrayisorganizedinto512/1024/2048

programmable pages of 256-bytes each. A single byte or,

up to 256 bytes, can be programmed at a time using the

Page Program instruction. Pages are grouped into 2/4/8

erasablesectorsof256pages(64K-byte)eachasshownin

figure 1. Both Sector Erase and Bulk (full chip) Erase

instructionsaresupported.

• Low Power Consumption,WideTemperature Range

– Single 2.7 to 3.6V supply

– 4mA active current, 1µA Power-down (typ)

– -40°to+85°Coperatingrange

• Fast and Flexible Serial Data Access

– Clock operation to 40MHz Fast Read, 33MHz

StandardRead

The Serial Peripheral Interface (SPI) consists of four pins

(Serial Clock, Chip Select, Serial Data In and Serial Data

Out) that support high speed serial data transfers up to

40MHz. A Hold pin, Write Protect pin and programmable

write protect features provide further control flexibility.

Additionally, the device can be queried for manufacturer

and device ID. Special customer ID (for copy authentica-

tion) and factory programming is available, contact Nex-

Flash for more information.

– Byte-addressableReadandProgram

– Auto-incrementReadcapability

– Manufacturer and Device ID

• Programming Features

– Page program up to 256 bytes <2ms

– Sector Erase (64K-byte) 2 seconds

– Chip erase: 3 seconds (25P10/20),

5 seconds (25P40)

– 100,000 erase/write cycles

– Twenty year data retention

• Software and HardwareWrite Protection

– Write-Protect all or portion of memory via software

– Enable/Disable protection with WP pin

8-Pin SOIC 150-mil

(PackageCodeN)

• Space Saving Package

– Tiny 8-pin SOIC

• Ideal for systems with limited pins, space, and power

– ASICandController-basedserialcode-download

– Microcontroller systems storing data, text or voice

– Battery-operatedandportableproducts

4

NexFlashTechnologies, Inc.

PRELIMINARY MKP-0009 Rev 6 NXSF040I-0405

04/04/05 ©

1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI

NX25P10,NX25P20ANDNX25P40

Serial Flash Memory Array

1

07FF00h

07FFFFh

Sector 7

Sector 6

2

070000h

06FF00h

0700FFh

06FFFFh

060000h

05FF00h

0600FFh

05FFFFh

3

Sector 5

Sector 4

Sector 3

050000h

04FF00h

0500FFh

04FFFFh

4

040000h

03FF00h

0400FFh

03FFFFh

5

030000h

02FF00h

0300FFh

02FFFFh

6

Write Control

Logic

WP

Sector 2

Sector 1

Sector 0

020000h

01FF00h

0200FFh

01FFFFh

7

Status

Register

010000h

00FF00h

0100FFh

00FFFFh

8

*

High-voltage

Generators

HOLD

000000h

0000FFh

9

Begining

Page Address

Ending

Page Address

Latch / Counter

CLK

SPI

Comand and

Control Logic

CS

Column Decode

and 256 Byte Page Buffer

10

11

12

Data

DI

Byte Address

Latch / Counter

DO

Every Sector Consists of 256 Pages of 256 Bytes Each

*

Figure 1. NX25P10, NX25P20 and NX25P40 Block Diagram

NexFlashTechnologies, Inc.

5

PRELIMINARY MKP-0009 Rev 6 NXSF040I-0405

04/04/05 ©

1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI

NX25P10,NX25P20ANDNX25P40

PIN DESCRIPTIONS

WriteProtect(WP)

PackageTypes

The Write Protect (WP) pin can be used to prevent the

StatusRegisterfrombeingwritten.Usedinconjunctionwith

theStatusRegister’sBlockProtect(BP0andBP1)bitsand

Status Register Protect (SRP) bits, a portion or the entire

memory array can be hardware protected. The WP pin is

active low.

The standard package for the NX25P10/20/40 is an 8-pin

plasticSOICwith150milbody(NexFlashpackagecode N).

It also allows a package migration path to higher density

Serial Flash devices. The pinout for the “N” package is

showninFigure2. Packagediagramsanddimensionsare

illustrated at the end of this data sheet. Optional 8-contact

MLPpackagesmaybeavailable.PleasecontactNexFlash

for further MLP package information.

Serial Data Input (DI)

8

7

6

5

1

2

3

4

CS

DO

VCC

HOLD

CLK

DI

The SPI Serial Data Input (DI) pin provides a means for

instructions, addresses and data to be serially written to

(shifted into) the device. Data is latched on the rising edge

of the Serial Clock (CLK) input pin.

WP

SerialDataOutput(DO)

The SPI Serial Data Output (DO) pin provides a means for

data and status to be serially read from (shifted out of) the

device. Data is shifted out on the falling edge of the Serial

Clock (CLK) input pin.

GND

Figure 2. NX25P10, NX25P20 and NX25P40 Pin

Assignments, 8-pin SOIC (Package Code N)

SerialClock(CLK)

TheSPISerialClockInput(CLK)pinprovidesthetimingfor

serialinputandoutputoperations.("SeeSPI"Operations")

Table 1. Pin Descriptions

Chip Select (CS)

DI

DataInput

The SPI Chip Select (CS) pin enables and disables device

operation.WhenCSishighthedeviceisdeselectedandthe

Serial Data Output (DO) pin is at high impedance. When

deselected, the devices power consumption will be at

standby levels unless an internal erase, program or status

register cycle is in progress. When CS is brought low the

devicewillbeselected,powerconsumptionwillincreaseto

activelevelsandinstructionscanbewrittentoanddataread

from the device. After power-up, CS must transition from

hightolowbeforeanewinstructionwillbeaccepted.TheCS

input must track the Vcc supply level at power-up (see

“WriteProtection”andfigure17).Ifneededapull-upresister

on CS can be used to accomplish this.

DO

DataOutput

CLK

Serial Clock Input

Chip Select Input

Write Protect Input

HoldInput

CS

WP

HOLD

Vcc, GND

PowerSupply

Hold(HOLD)

The HOLD pin allows the device to be paused while it is

actively selected. When HOLD is brought low, while CS is

low,theDOpinwillbeathighimpedanceandsignalsonthe

DI and CLK pins will be ignored (don’t care). When

HOLD is brought high, device operation can resume. The

hold function can be useful when multiple devices are

sharing the same SPI signals. (“See Hold function”)

6

NexFlashTechnologies, Inc.

PRELIMINARY MKP-0009 Rev 6 NXSF040I-0405

04/04/05 ©

1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI

NX25P10,NX25P20ANDNX25P40

SPI OPERATION

WriteProtectFeatures

SPI Modes

The NX25P10/20/40 is accessed through an SPI compat-

iblebusconsistingoffoursignals:SerialClock(CLK),Chip

Select (CS), Serial Data Input (DI) and Serial Data Output

(DO).BothSPIbusoperationModes0(0,0)and3(1,1)are

supported. The primary difference between Mode 0 and

Mode 3 concerns the normal state of the CLK signal when

the SPI bus master is in standby and data is not being

transferred to the Serial Flash. For Mode 0 the CLK signal

isnormallylow.ForMode3theCLKsignalisnormallyhigh.

In either case data input on the DI pin is sampled on the

risingedgeoftheCLK.DataoutputontheDOpinisclocked

out on the falling edge of CLK.

1

• Device resets when Vcc is below threshold.

• Time delay write disable after Power-up.

• Writeenable/disableinstructions.

2

• Automatic write disable after program and erase.

• Software write protection using Status Register.

• Hardware write protection using Status Register and

WP pin.

3

• WriteProtectionusingPower-downinstruction.

4

Upon power-up or at power-down the NX25P10/20/40 will

maintain a reset condition while Vcc is below the threshold

value of V^WI, (See Power-up Timing and Voltage Levels:

Table 7 and Figure 17). While reset, all operations are

disabledandnoinstructionsarerecognized.Duringpower-

up and after the Vcc voltage exceeds VWI, all program and

erase related instructions are further disabled for a time

delay of tPUW. This includes the Write Enable, Page Pro-

gram, Sector Erase, Bulk Erase and the Write Status

Register instructions. Note that the chip select pin (CS)

must track the Vcc supply level at power-up until the Vcc-

minlevelandtVSL timedelayisreached.Ifneededapull-up

resister on CS can be used to accomplish this.

HoldFunction

TheHOLDsignalallowstheNX25P10/20/40operationtobe

paused while it is actively selected (when CS is low). The

holdfunctionmaybeusefulincaseswheretheSPIdataand

clock signals are shared with other devices. For example,

considerifthepagebufferwasonlypartiallywrittenwhena

priorityinterruptrequiresuseoftheSPIbus.Inthiscasethe

hold function can save the state of the instruction and the

data in the buffer so programming can resume where it left

off once the bus is available again.

5

6

Toinitiateaholdcondition,thedevicemustbeselectedwith

CS low. A hold condition will activate on the falling edge of

the HOLD signal if the CLK signal is already low. If the CLK

is not already low the hold condition will activate after the

next falling edge of CLK. The hold condition will terminate

on the rising edge of the hold signal if the CLK signal is

alreadylow. IftheCLKisnotalreadylowtheholdcondition

will terminate after the next falling edge of CLK.

7

Afterpower-upthedeviceinautomaticallyplacedinawrite-

disabled state with the Status Register Write Enable Latch

(WEL)settoa0.AWriteEnableinstructionmustbeissued

beforeaPageProgram, SectorErase, BulkEraseorWrite

Status Register instruction will be accepted. After complet-

ing a program, erase or write instruction the Write Enable

Latch(WEL)isautomaticallyclearedtoawrite-disabledstate

of 0.

8

Duringaholdcondition,theSerialDataOutput(DO)ishigh

impedance, and Serial Data Input (DI) and Serial Clock

(CLK) are ignored. The Chip Select (CS) signal should be

keptactive(low)forthefulldurationoftheholdoperationto

avoid resetting the internal logic state of the device.

9

Software controlled write protection is facilitated using the

Write Status Register instruction and setting the Status

Register Protect (SRP) and Block Protect (BP0, BP2) bits.

These Status Register bits allow a portion or all of the

memorytobeconfiguredasreadonly.Usedinconjunction

with the Write Protect (WP) pin, changes to the Status

Registercanbeenabledordisabledunderhardwarecontrol.

See Status Register for further information.

10

11

12

WRITE PROTECTION

Applications that use non-volatile memory must take into

consideration the possibility of noise and other adverse

system conditions that may compromise data integrity. To

addressthisconcerntheNX25P10/20/40providesseveral

means to protect data from inadvertent writes.

Additionally, the Power-down instruction offers an extra

level of write protection as all instructions are ignored

except for the Release Power-down instruction.

NexFlashTechnologies, Inc.

7

PRELIMINARY MKP-0009 Rev 6 NXSF040I-0405

04/04/05 ©

1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI

NX25P10,NX25P20ANDNX25P40

STATUS REGISTER

TheReadStatusRegisterinstructioncanbeusedtoprovide

status on the availability of the Flash memory array, if the

device is write enabled or disabled, and the state of write

protection. The Write Status Register instruction can be

usedtoconfigurethedeviceswriteprotectionfeatures.See

Figure3.

Block Protect Bits (BP2, BP1, BP0)

The Block Protect Bits (BP2, BP1, BP0) are non-volatile

read/writebitsinthestatusregister(S4,S3,S2)thatprovide

Write Protection control and status. Block Protect bits can

be set using the Write Status Register Instruction (see tW

in AC characteristics). All, none or a portion of the memory

arraycanbeprotectedfromProgramandEraseinstructions

(see table 2). The factory default setting for the Block

Protection Bits is 0, none of the array protected. The Block

Protect bits can not be written to if the Status Register

Protect (SRP) bit is set to 1 and the Write Protect (WP) pin

is low. The NX25P20 and NX25P10 do not use BP2.

BUSY

BUSY is a read only bit in the status register (S0) that is set

to a 1 state when the device is executing a Page Program,

Sector Erase, Bulk Erase or Write Status Register instruc-

tion. During this time the device will ignore further instruc-

tions except for the Read Status Register instruction (see

tW, tPP, tSE and tBE in AC Characteristics). When the

program, erase or write status register instruction has

completed, the BUSY bit will be cleared to a 0 state

indicating the device is ready for further instructions.

ReservedBits

Status register bit locations 5 and 6 are reserved for future

use. Current devices will read 0 for these bit locations. It is

recommendedtomaskoutthereservedbitwhentestingthe

Status Register. Doing this will ensure compatibility with

future devices.

Write Enable Latch (WEL)

Write Enable Latch (WEL) is a read only bit in the status

register(S1)thatissettoa1afterexecutingaWriteEnable

Instruction. The WEL status bit is cleared to a 0 when the

device is write disabled. A write disable state occurs upon

power-up or after any of the following instructions: Write

Disable, Page Program, Sector Erase, Bulk Erase and

Write Status Register.

StatusRegisterProtect(SRP)

TheStatusRegisterProtect(SRP)bitisanon-volatileread/

write bit in the status register (S7) that can be used in

conjunctionwiththeWriteProtect(WP)pintodisablewrites

to the status register. When the SRP bit is set to a 0 state

(factory default) the WP pin has no control over the status

register. When the SRP pin is set to a 1, the Write Status

Register instruction is locked out while the WP pin is low.

When the WP pin is high the Write Status Register instruc-

tion is allowed.

S7

S6

S5

S4

S3

S2

S1

S0

SRP

(Reserved)

BP2

BP1

BP0

WEL BUSY

Status RegisterProtect

(Non-volatile)

Block Protect Bits

(Non-volatile)

Write Enable Latch

Device Busy

Erase Program or Write in Progress

Figure 3. Status Register Bit Locations

8

NexFlashTechnologies, Inc.

PRELIMINARY MKP-0009 Rev 6 NXSF040I-0405

04/04/05 ©

1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI

NX25P10,NX25P20ANDNX25P40

Table2:StatusRegisterMemoryProtection

Status Register ⁽¹⁾

NX25P40 (4M-bit) Memory Protection

BP2 BP1 BP0

Sector(s)

NONE

7

Addresses

Density

NONE

512K-bit

1M-bit

Portion

NONE

1

0

1

0

1

x

0

1

0

1

x

NONE

070000h - 07FFFFh

060000h - 07FFFFh

040000h - 07FFFFh

000000h - 07FFFFh

Upper 1/8

Upper 1/4

Upper 1/2

ALL

6 and 7

4 thru 7

ALL

2

2M-bit

4M-bit

3

Status Register ⁽¹⁾

BP2 BP1 BP0

NX25P20 (2M-bit) Memory Protection

Sector(s)

NONE

3

Addresses

Density

NONE

512K-bit

1M-bit

Portion

NONE

x

0

1

0

1

0

1

NONE

4

030000h - 03FFFFh

020000h - 03FFFFh

000000h - 03FFFFh

Upper 1/4

Upper 1/2

ALL

2 and 3

ALL

2M-bit

5

Status Register ⁽¹⁾

BP2 BP1 BP0

NX25P10 (1M-bit) Memory Protection

Sector(s)

NONE

ALL

Addresses

NONE

Density

NONE

1M-bit

Portion

NONE

ALL

6

x

0

1

x

0

1

NONE

000000h - 01FFFFh

7

Notes:

1. x = don't care.

8

9

10

11

12

NexFlashTechnologies, Inc.

9

PRELIMINARY MKP-0009 Rev 6 NXSF040I-0405

04/04/05 ©

1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI

NX25P10,NX25P20ANDNX25P40

INSTRUCTIONS

feature further protects the device from inadvertent writes.

Additionally, while the memory is being programmed or

erased, or when the Status Register is being written, all

instructionsexceptforReadStatusRegisterwillbeignored

until the program or erase cycle has completed.

The instruction set of the NX25P10/20/40 consists of

twelvebasicinstructionsthatarefullycontrolledthroughthe

SPI bus (see Table 3). Instructions are initiated with the

falling edge of Chip Select (CS). The first byte of data

clockedintotheDIinputprovidestheinstructioncode.Data

on the DI input is sampled on the rising edge of clock with

most significant bit (MSB) first.

Instructions vary in length from a single byte to several

bytes and may be followed by address bytes, data bytes,

dummy bytes (don’t care), and in some cases, a combina-

tion.Instructionsarecompletedwiththerisingedgeofedge

CS. Clock relative timing diagrams for each instruction are

includedinfigures5through17.Allreadinstructionscanbe

completed after any clocked bit. However, all instructions

that Write, Program or Erase must complete on a byte

boundary (CS driven high after a full 8-bits have been

clocked) otherwise the instruction will be terminated. This

Table4:ManufacturerandDeviceIdentification

Manufacturer ID

(M7-M0)

NexFlash

EFh

Device ID

NX25P10

NX25P20

NX25P40

(ID7-ID0)

10h

11h

12h

Table 3: Instruction Set ⁽¹⁾

InstructionName

Byte1 Byte 2⁽⁵⁾

Code

Byte3

Byte4

Byte5

Byte6

n-Bytes

WriteEnable

06h

04h

WriteDisable

(2)

Read Status Register

Write Status Register

ReadData

05h

01h

03h

0Bh

(S7–S0)⁽¹⁾

S7–S0

A23–A16

A15–A8

A7–A0

(D7–D0)

dummy

(Next byte)

continuous

Fast Read

(D7–D0)

(Next Byte)

continuous

PageProgram

Sector Erase

Bulk Erase

02h

D8h

C7h

B9h

ABh

A23–A16

A15–A8

A7–A0

A7–A0⁽⁶⁾

(D7–D0)

(Next byte)

upto256bytes

Power-down

(3)

(4)

ReleasePower-down

and Device ID

dummy

00h

(ID7-ID0)

Manufacturer/DeviceID

90h

(M7-M0) (ID7-ID0)

Notes:

1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data being read from

the device on the DO pin.

2. The Status Register contents will repeat continuously until CS terminate the instruction.

3. The Device ID will repeat continuously until CS terminate the instruction.

4. The Manufacturer ID and Device ID bytes will repeat continuously until CS terminate the instruction.

5. Unused upper address bits must be set to a 0 for the NX25P10.

6. The lowest 16 address bits (A15-A0) must be set to 0.

10

NexFlashTechnologies, Inc.

PRELIMINARY MKP-0009 Rev 6 NXSF040I-0405

04/04/05 ©

1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI

NX25P10,NX25P20ANDNX25P40

Write Enable (06h)

The Write Enable instruction is entered by driving CS low,

shiftingtheinstructioncode“06h”intotheDataInput(DI)pin

on the rising edge of CLK, and then driving CS high.

The Write Enable instruction (Figure 4) sets the Write

Enable Latch (WEL) bit in the Status Register to a 1. The

WEL bit must be set prior to every Page Program, Sector

Erase, Bulk Erase and Write Status Register instruction.

1

2

CS

Mode 3

Mode 0

0

1

2

3

4

5

6

7

3

CLK

Instruction (06h)

High Impedance

DI

4

DO

5

Figure 4. Write Enable Instruction Sequence Diagram

6

7

Write Disable (04h)

The Write Disable instruction (Figure 5) resets the Write

Enable Latch (WEL) bit in the Status Register to a 0. The

Write Disable instruction is entered by driving CS low,

shifting the instruction code “04h” into the DI pin and then

drivingCShigh.NotethattheWELbitisautomaticallyreset

after Power-up and upon completion of the Write Status

Register, Page Program, Sector Erase, and Bulk Erase

instructions.

8

9

CS

10

11

12

0

1

2

3

4

5

6

7

Mode 3

Mode 0

CLK

Instruction (04h)

DI

High Impedance

DO

Figure 5. Write Disable Instruction Sequence Diagram

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Read Status Register (05h)

TheReadStatusRegisterinstructionallowsthe8-bitStatus

Register to be read. The instruction is entered by

drivingCSlowandshiftingtheinstructioncode“05h”intothe

DIpinontherisingedgeofCLK.Thestatusregisterbitsare

thenshiftedoutontheDOpinatthefallingedgeofCLKwith

most significant bit (MSB) first as shown in figure 6. The

Status Register bits are shown in figure 3 and include the

BUSY, WEL, BPO-BP2, and STP bits (see description of

the Status Register earlier in this data sheet).

The Status Register instruction may be used at any time,

evenwhileaProgram,EraseorWriteStatusRegistercycle

is in progress. This allows the BUSY status bit to be

checkedtodeterminewhenthecycleiscompleteandifthe

devicecanacceptanotherinstruction.TheStatusRegister

can be read continuously, as shown in Figure 6. The

instruction is completed by driving CS high.

CS

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23

Mode 3

Mode 0

CLK

DI

Instruction (05h)

Status Register Out

High Impedance

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

DO

7

*

= MSB

*

Figure 6. Read Status Register Instruction Sequence Diagram

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Write Status Register (01h)

The Write Status Register instruction allows the Status

Register to be written. A Write Enable instruction must

previouslyhavebeenexecutedforthedevicetoacceptthe

Write Status Register Instruction (Status Register bit WEL

mustequal1).Oncewriteenabled,theinstructionisentered

by driving CS low, sending the instruction code “01h”, and

then writing the status register data byte as illustrated in

figure 7. The Status Register bits are shown in figure 3 and

described earlier in this data sheet.

While the Write Status Register cycle is in progress, the

Read Status Register instruction may still accessed to

checkthestatusoftheBUSYbit.TheBUSYbitisa1during

the Write Status Register cycle and a 0 when the cycle is

finishedandreadytoacceptotherinstructionsagain. After

theWriteRegistercyclehasstartedtheWriteEnableLatch

(WEL) bit in the Status Register will be cleared to 0.

1

2

The Write Status Register instruction allows the Block

Protectbits(BP2, BP1andBP0)tobesetforprotectingall,

a portion, or none of the memory from erase and program

instructions. Protectedareasbecomeread-only(seetable

2). The Write Status Register instruction also allows the

Status Register Protect bit (SRP) to be set. This bit is used

in conjunction with the Write Protect (WP) pin to disable

writes to the status register. When the SRP bit is set to a 0

state (factory default) the WP pin has no control over the

status register. When the SRP pin is set to a 1, the Write

Status Register instruction is locked out while the WP pin

is low. When the WP pin is high the Write Status Register

instruction is allowed.

For the NX25P40, only non-volatile Status Register bits

STP, BP2, BP1 and BP0 (bits 7, 4, 3 and 2) can be written

to.FortheNX25P20andNX25P10onlyStatusRegisterbits

STP, BP1 and BP0 (bits 7, 3 and 2) can be written to. All

otherStatusRegisterbitlocationsareread-onlyandwillnot

be affected by the Write Status Register instruction.

3

4

TheCSpinmustbedrivenhighaftertheeighthbitofthelast

byte has been latched. If this is not done the Write Status

Registerinstructionwillnotbeexecuted. AfterCS isdriven

high, the self-timed Write Status Register cycle will com-

mence for a time duration of t^W(See AC Characteristics).

5

6

CS

7

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

Status Register In

Mode 3

Mode 0

CLK

Instruction (01h)

8

7

6

5

4

3

2

1

0

DI

*

High Impedance

DO

9

= MSB

*

10

11

12

Figure 7. Write Status Register Instruction Sequence Diagram

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Read Data (03h)

TheReadDatainstructionallowsoneormoredatabytesto

be sequentially read from the memory. The instruction is

initiated by driving the CS pin low and then shifting the

instructioncode“03h” followedbya24-bitaddress(A23-A0)

intotheDIpin.Thecodeandaddressbitsarelatchedonthe

risingedgeoftheCLKpin.Aftertheaddressisreceived,the

data byte of the addressed memory location will be shifted

out on the DO pin at the falling edge of CLK with most

significant bit (MSB) first. The address is automatically

incremented to the next higher address after each byte of

dataisshiftedoutallowingforacontinuousstreamofdata.

This means that the entire memory can be accessed with

a single instruction as long as the clock continues. The

instructioniscompletedbydrivingCShigh.TheReadData

instruction sequence is shown in figure 8. If a Read Data

instructionisissuedwhileanErase,ProgramorWritecycle

isinprocess(BUSY=1)theinstructionisignoredandwillnot

have any effects on the current cycle. The Read Data

instruction allows clock rates from D.C. to a maximum of fR

( see AC Electrical Characteristics).

CS

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31 32 33 34 35 36 37 38 39

Mode 3

Mode 0

CLK

Instruction (03h)

24-Bit Addess

DI

23 22 21

3

2

1

0

Data Out 1

Data Out 2

*

High Impedance

7

6

5

4

3

2

1

0

DO

*

= MSB

*

Figure 8. Read Data Instruction Sequence Diagram

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Fast Read (0Bh)

The Fast Read instruction is similar to the Read Data

instructionexceptthatitcanoperateatthehighestpossible

frequency of FR (seeACElectricalCharacteristics). Thisis

accomplished by adding a “dummy” byte after the 24-bit

address as shown in figure 9. The dummy byte allows the

devices internal circuits additional time for setting up the

initial address. The dummy byte data value on the DI pin is

a “don’t care”.

1

2

CS

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31

Mode 3

Mode 0

3

CLK

Instruction (0Bh)

24-Bit Address

23 22 21

DI

3

2

1

0

4

DO

5

CS

6

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

CLK

DI

Dummy Byte

7

6

5

4

3

2

1

0

Data Out 1

Data Out 2

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

DO

8

*

= MSB

*

9

Figure 9. Fast Read Instruction Sequence Diagram

10

11

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Page Program (02h)

The Page Program instruction allows from one byte to 256

bytes of data to be programmed at memory locations

previouslyerasedtoall1s(FFh).AWriteEnableinstruction

must be executed before the device will accept the Page

Program Instruction (Status Register bit WEL must equal

1). Theinstructionisinitiatedbydrivingthe CSpinlowthen

shifting the instruction code “02h” followed by a 24-bit

address(A23-A0)andatleastonedatabyte,intotheDIpin.

The CS pin must be driven low for the entire length of the

instructionwhiledataisbeingsenttothedevice. ThePage

Program instruction sequence is shown in figure 10.

tothedevicetheaddressingwillwraptothebeginningofthe

page and overwrite previously sent data.

Aswiththewriteanderaseinstructions,theCSpinmustbe

driven high after the eighth bit of the last byte has been

latched.IfthisisnotdonethePagePrograminstructionwill

not be executed. After CS is driven high, the self-timed

PagePrograminstructionwillcommenceforatimeduration

of tpp (See AC Characteristics). While the Page Program

cycle is in progress, the Read Status Register instruction

may still be accessed for checking the status of the BUSY

bit. TheBUSYbitisa1duringthePageProgramcycleand

becomes a 0 when the cycle is finished and the device is

ready to accept other instructions again. After the Page

ProgramcyclehasstartedtheWriteEnableLatch(WEL)bit

in the Status Register is cleared to 0. The Page Program

instruction will not be executed if the addressed page is

protected by the Block Protect (BP2, BP1, BP0) bits (see

Table2).

If an entire 256 byte page is to be programmed, the last

addressbyte(the8leastsignificantaddressbits)shouldbe

setto0. Ifthelastaddressbyteisnotzero, andthenumber

ofclocksexceedtheremainingpagelength,theaddressing

will wrap to the beginning of the page. Less than 256 bytes

can be programmed without having any effect on other

byteswithinthesamepage.Ifmorethan256bytesaresent

CS

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31 32 33 34 35 36 37 38 39

CLK

DI

Instruction (02h)

24-Bit Address

Data Byte 1

23 22 21

3

2

1

0

7

6

5

4

3

2

1

0

*

CS

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

CLK

DI

Data Byte 2

Data Byte 3

Data Byte 256

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

*

= MSB

*

Figure 10. Page Program Instruction Sequence Diagram

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Sector Erase (D8h)

The Sector Erase instruction sets all memory within a

specified sector to the erased state of all 1s (FFh). A Write

Enable instruction must be executed before the device will

accept the Erase Sector Instruction (Status Register bit

WELmustequal1).Theinstructionisinitiatedbydrivingthe

CS pin low and shifting the instruction code “D8h” followed

a24-bitsectoraddress(A23-A0)(seeFigure1).Thelowest

16addressbits(A15-A0)mustbesetto0.TheSectorErase

instruction sequence is shown in figure 11.

instruction will not be executed. After CS is driven high, the

self-timed Sector Erase instruction will commence for a time

duration of t^SE(See AC Characteristics). While the Sector

Erase cycle is in progress, the Read Status Register instruc-

tionmaystillbeaccessedforcheckingthestatusoftheBUSY

bit. The BUSY bit is a 1 during the Sector Erase cycle and

becomesa0whenthecycleisfinishedandthedeviceisready

toacceptotherinstructionsagain.AftertheSectorErasecycle

has started the Write Enable Latch (WEL) bit in the Status

Register is cleared to 0. The Sector Erase instruction will not

be executed if the addressed page is protected by the Block

Protect (BP2, BP1, BP0) bits (see Table 2).

1

2

TheCSpinmustbedrivenhighaftertheeighthbitofthelast

byte has been latched. If this is not done the Sector Erase

3

4

CS

0

1

2

3

4

5

6

7

8

9

29 30 31

Mode 3

Mode 0

5

CLK

Instruction (D8h)

24-Bit Address

DI

23 22

2

1

0

6

*

High Impedance

DO

7

= MSB

*

Figure 11. Sector Erase Instruction Sequence Diagram

8

9

10

11

12

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Bulk Erase (C7h)

The Bulk Erase instruction sets all memory within the

device to the erased state of all 1s (FFh). A Write Enable

instruction must be executed before the device will accept

the Bulk Erase Instruction (Status Register bit WEL must

equal1).TheinstructionisinitiatedbydrivingtheCSpinlow

and shifting the instruction code “C7h”. The Bulk Erase

instruction sequence is shown in figure 12.

Erase instruction will commence for a time duration of tBE

(See AC Characteristics). While the Bulk Erase cycle is in

progress, the Read Status Register instruction may still be

accessed to check the status of the BUSY bit. The BUSY

bitisa1duringtheBulkErasecycleandbecomesa0when

finishedandthedeviceisreadytoacceptotherinstructions

again. After the Bulk Erase cycle has started the Write

Enable Latch (WEL) bit in the Status Register is cleared to

0. The Bulk Erase instruction will not be executed if any

pageisprotectedbytheBlockProtect(BP2,BP1,BP0)bits

(see Table 2).

TheCSpinmustbedrivenhighaftertheeighthbithasbeen

latched.IfthisisnotdonetheBulkEraseinstructionwillnot

be executed. After CS is driven high, the self-timed Bulk

CS

0

1

2

3

4

5

6

7

Mode 3

Mode 0

CLK

Instruction (C7h)

High Impedance

DI

DO

Figure 12. Bulk Erase Instruction Sequence Diagram

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Power-down (B9h)

Although the standby current during normal operation is

relatively low, standby current can be further reduced with

thePower-downinstruction.Thelowerpowerconsumption

makes the Power-down instruction especially useful for

battery powered applications (See ICC1 and ICC2 in AC

Characteristics). The instruction is initiated by driving the

CSpinlowandshiftingtheinstructioncode“B9h”asshown

in figure 13.

not be executed. After CS is driven high, the power-down

state will entered within the time duration of tDP (See AC

Characteristics). While in the power-down state only the

Release from Power-down / Device ID instruction, which

restoresthedevicetonormaloperation,willberecognized.

All other instructions are ignored. This includes the Read

Status Register instruction, which is always available

during normal operation. Ignoring all but one instruction

makesthePowerDownstateausefulconditionforsecuring

maximumwriteprotection.Thedevicealwayspowers-upin

the normal operation with the standby current of ICC1.

1

2

TheCSpinmustbedrivenhighaftertheeighthbithasbeen

latched. If this is not done the Power-down instruction will

3

4

CS

t

DP

0

1

2

3

4

5

6

7

Mode 3

Mode 0

CLK

5

Instruction (B9h)

DI

High Impedance

6

DO

Stand-by Current

Power-down Current

Figure 13. Deep Power-down Instruction Sequence Diagram

7

8

9

10

11

12

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Release Power-down / Device ID (ABh)

The Release from Power-down / Device ID instruction is a

multi-purpose instruction. It can be used to release the

device from the power-down state, obtain the devices

electronic identification (ID) number or do both.

first as shown in figure 15. The Device ID values for the

NX25P10, NX25P20, and NX25P40 are listed in Table 4.

The Device ID can be read continuously. The instruction is

completed by driving CS high.

Whenusedonlytoreleasethedevicefromthepower-down

state, the instruction is issued by driving the CS pin low,

shifting the instruction code “ABh” and driving CS high as

shown in figure 14. After the time duration of t^RES1 (SeeAC

Characteristics) the device will resume normal operation

and other instructions will be accepted. The CS pin must

remain high during the t^RES1 time duration.

Whenusedtoreleasethedevicefromthepower-downstate

and obtain the Device ID, the instruction is the same as

previously described, and shown in figure 13, except that

afterCSisdrivenhighitmustremainhighforatimeduration

of t^RES2 (See AC Characteristics). After this time duration

the device will resume normal operation and other instruc-

tions will be accepted.

When used only to obtain the Device ID while not in the

power-down state, the instruction is initiated by driving the

CS pin low and shifting the instruction code “ABh” followed

by 3-dummy bytes. The Device ID bits are then shifted out

on the falling edge of CLK with most significant bit (MSB)

If the Release from Power-down / Device ID instruction is

issuedwhileanErase,ProgramorWritecycleisinprocess

(whenBUSYequals1)theinstructionisignoredandwillnot

have any effects on the current cycle.

CS

t

RES1

0

1

2

3

4

5

6

7

Mode 3

Mode 0

CLK

Instruction (ABh)

DI

High Impedance

DO

Power-down Current

Stand-by Current

Figure14. ReleasePower-downInstructionSequence

CS

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31 32 33 34 35 36 37 38

Mode 3

Mode 0

CLK

Instruction (ABh)

3 Dummy Bytes

tRES2

23 22 21

3

2

1

0

DI

Device ID

*

**

High Impedance

DO

7

6

5

4

3

2

1

0

*

Power-down Current

Stand-by Current

= MSB

*

** ^{= See Table 4}

Figure 15. Release Power-down / Device ID Instruction Sequence Diagram

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Read Manufacturer / Device ID (90h)

turerIDforNexFlash(EFh)andtheDeviceIDareshiftedout

on the falling edge of CLK with most significant bit (MSB)

first as shown in figure 16. The Device ID values for the

NX25P10, NX25P20, andNX25P40arelistedinTable4. If

the 24-bit address is initially set to 000001h the Device ID

will be read first and then followed by the Manufacturer ID.

TheManufacturerandDeviceIDscanbereadcontinuously,

alternating from one to the other. The instruction is com-

pleted by driving CS high.

TheReadManufacturer/DeviceIDinstructionisanalterna-

tivetotheReleasefromPower-down/DeviceIDinstruction

that provides both the JEDEC assigned manufacturer ID

and the specific device ID.

1

TheReadManufacturer/DeviceIDinstructionisverysimilar

to the Release from Power-down / Device ID instruction.

The instruction is initiated by driving the CS pin low and

shifting the instruction code “90h” followed by a 24-bit

address (A23-A0) of 000000h. After which, the Manufac-

2

3

CS

4

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31

Mode 3

Mode 0

CLK

Instruction (90h)

Address (000000h)

23 22 21

3

2

1

0

5

DI

*

High Impedance

DO

6

CS

32 33 34 35 36 37 38

39 40 41 42 43 44 45

7

CLK

DI

8

^{Device ID (}**⁾

Manufacturer ID (EFh

)

7

6

5

4

3

2

1

0

DO

*

9

= MSB

** ^{= See Table 4}

*

Figure 16. Read Manufacturer / Device ID Diagram

10

11

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SPECIFICATIONS AND TIMING DIAGRAMS

Table 5. Absolute Maximum Ratings⁽¹⁾

Symbol

Vcc

Parameters

Conditions

Range

Unit

V

°C

SupplyVoltage

–0.6 to +4.0

–0.6 to Vcc + 0.4

–65 to +150

See Note 2

VIO

Voltage Applied to Any Pin

StorageTemperature

LeadTemperature

RelativetoGround

TSTG

TLEAD

VESD

Electrostatic Discharge Voltage

Human Body Model⁽³⁾

–2000 to +2000

V

Note:

1. This device has been designed and tested for the specified operation ranges. Proper operation outside of these levels is

not guaranteed. Exposure beyond absolute maximum ratings (listed above) may cause permanent damage.

2. Compliant with JEDEC Standard J-STD-20C for small body Sn-Pb or Pb-free (Green) assembly and the European directive

on restrictions on hazardous substances (RoHS) 2002/95/EU.

3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 ohms, R2=500 ohms).

Table 6. Operating Ranges

Symbol

Parameter

Supply Voltage⁽¹⁾

Conditions

Min

2.7

3.0

Max

3.6

Unit

V

Vcc

FR = 33MHz, fR = 20MHz

FR = 40MHz, fR = 33MHz

Industrial

TA

AmbientTemperature,Operating

–40

+85

°C

Note:

1. Vcc voltage during Read can operate across the min and max range but should not exceed 10ꢀ of the programming

(erase/write) voltage.

Table 7. Power-up Timing and Write Inhibit Threshold

Symbol

Parameter

Min

10

1

Max

Unit

µs

ms

V

(1)

tVSL

VCC(min) to CS Low

Time Delay Before Write Instruction

Write Inhibit Threshold Voltage

(1)

tPUW

10

2

(1)

VWI

1

Note:

1. These parameters are characterized only.

Vcc

Vcc ^(max)

Program, Erase and Write Instructions are Ignored

CS Must Track Vcc

Vcc (min)

tVSL

Read Instructions

Allowed

Device is Fully

Accessible

Reset

State

V

WI

tPUW

Time

Figure 17. Power-up Timing and Voltage Levels

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Table 8. DC Electrical Characteristics (Preliminary) ⁽¹⁾

Symbol

Parameter

Conditions

VIN = 0V⁽²⁾

Min

Typ

Max

6

8

2

50

5

7

14

18

Unit

pf

µA

mA

(2)

CIN

InputCapacitance

OutputCapacitance

InputLeakage

I/O Leakage

StandbyCurrent

Power-downCurrent

CurrentReadData1MHz

CurrentReadData20MHz

CurrentReadData33MHz

1

Cout⁽²⁾

VOUT = 0V⁽²⁾

ILI

ILO

ICC1

ICC2

I^CC3

CS = VCC, VIN = GND or VCC

C = 0.1VCC / 0.9 VCC DO = Open

25

<1

4

10

14

2

3

ICC4

ICC5

ICC6

ICC7

VIL

CurrentPageProgram

Current Write Status Register

CurrentSectorErase

Current Bulk Erase

Input Low Voltage

Input High Voltage

CS = VCC

15

8

15

17

20

25

mA

V

4

25

–0.5

Vccx0.7

Vccx0.3

Vcc +0.4

0.4

VIH

VOL

VOH

Output Low Voltage

OutputHighVoltage

IOL = 1.6 mA

IOH = –100 µA

5

VCC–0.2

Notes:

1. See Preliminary Designation.

2. Tested on sample basis and specified through design and characterization data. TA=25° C, Vcc 3V, Frequency 20MHz.

6

7

Table 9. AC Measurement Conditions

Symbol

CL

Parameter

Min

Max

30

5

0.8VCC

0.7VCC

Unit

pF

ns

V

LoadCapacitance

30

8

TR, TF

VIN

Input Rise and Fall Times

Input Pulse Voltages

Output Timing Reference Voltages

0.2VCC to

0.3VCC to

OUT

V

9

Note:

1. Output Hi-Z is defined as the point where data out is no longer driven.

10

11

12

Input and Output

Timing Reference Levels

Input Levels

0.8 Vcc

0.7 Vcc

0.3 Vcc

0.2 Vcc

Figure 18. AC Measurement I/O Waveform

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Table10.ACElectricalCharacteristics(Preliminary)

Symbol

Alt

Description

Min

Typ Max

Unit

FR

fC

Clock frequency, for Fast Read (0Bh) and all other

instructions except Read Data (03h) 2.7V-3.6V Vcc

3.0V-3.6V Vcc

D.C.

33

40

MHz

fR

Clock freq. Read Data instruction (03h) 2.7V-3.6V Vcc

3.0V-3.6V Vcc

Clock High, Low Time, for Fast Read (0Bh)

and all other instructions except Read Data (03h)

Clock High, Low Time for Read Data instruction (20 / 33-40MHz) 18 / 11

Clock Rise Time peak to peak

Clock Fall Time peak to peak

CS Active Setup Time relative to CLK (20 / 33-40MHz)

CS Not Active Hold Time relative to CLK (20 / 33-40MHz)

Data In Setup Time (20 / 33-40MHz)

D.C.

11

20

33

MHz

ns

(1)

t^CLH, tCLL

(1)

tCRLH,tCRLL

ns

V / ns

ns

(2)

tCLCH

0.1

10 / 5

5 / 2

5

10 / 5

100

(2)

tCHCL

tSLCH

tCHSL

tDVCH

tCHDX

tCHSH

tSHCH

tSHSL

tCSS

tDSU

tDH

Data In Hold Time

CS Active Hold Time relative to CLK (20 / 33-40MHz)

CS Not Active Setup Time relative to CLK (20 / 33-40MHz)

CS Deselect Time

Output Disable Time (20/ 33-40MHz)

Clock Low to Output Valid (20 / 33-40MHz)

Output Hold Time

HOLD Active Setup Time relative to CLK (20 / 33-40MHz)

HOLD Active Hold Time relative to CLK (20 / 33-40MHz)

HOLD Not Active Setup Time relative to CLK (20 / 33-40MHz) 10 / 5

HOLD Not Active Hold Time relative to CLK (20 / 33-40MHz)

HOLD to Output Low-Z (20/ 33-40MHz)

HOLD to Output High-Z (20/ 33-40MHz)

Write Protect Setup Time Before CS Low

Write Protect Hold Time After CS High

CS HightoPower-downMode

tCSH

tDIS

tV

(2)

tSHQZ

15 / 9

15 / 10

tCLQV

tCLQX

tHLCH

tCHHH

tHHCH

tCHHL

tHO

0

10 / 5

(2)

tHHQX

tLZ

tHZ

15 / 9

20 / 9

(2)

tHLQZ

ns

µs

(4)

tWHSL

20

100

(4)

tSHWL

(2)

tDP

tRES1⁽²⁾

3

CS High to Standby Mode without Electronic

SignatureRead

CS High to Standby Mode with Electronic

SignatureRead

µs

tRES2⁽²⁾

1.8

µs

tW

Write Status Register Cycle Time

Page Program Cycle Time

Sector Erase Cycle Time

10

2

15

5

ms

s

tPP

tSE

tBE

0.7

3

Bulk Erase Cycle Time 25P10 and 25P20

Bulk Erase Cycle Time 25P40

3

5

6

10

s

Notes:

1. Clock high + Clock low must be less than or equal to 1/fC.

2. Value guaranteed by design and/or characterization, not 100ꢀ tested in production.

3. Expressed as a slew-rate.

4. Only applicable as a constraint for a Write Status Register instruction when Sector Protect Bit is set at 1.

24

NexFlashTechnologies, Inc.

PRELIMINARY MKP-0009 Rev 6 NXSF040I-0405

04/04/05 ©

1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI

NX25P10,NX25P20ANDNX25P40

CS

1

tCH

CLK

tCLQV

tCLQX

tCLQV

tCL

tSHQZ

tCLQX

2

DO

DI

LSB OUT

tQLQH

tQHQL

3

*

LEAST SIGNIFICANT ADDRESS BIT (LSB) IN

Figure 19. Serial Output Timing

4

tSHSL

5

CS

tCHSL

tSLCH

tCHSH

tSHCH

6

CLK

DI

tDVCH

tCHCL

tCLCH

tCHDX

MSB IN

(High Impedance)

LSB IN

7

DO

8

Figure 20. Input Timing

9

CS

tHLCH

tCHHH

tCHHL

tHLQZ

tHHCH

CLK

DO

10

11

12

tHHQX

DI

HOLD

Figure 21. Hold Timing

NexFlashTechnologies, Inc.

25

PRELIMINARY MKP-0009 Rev 6 NXSF040I-0405

04/04/05 ©

1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI

NX25P10,NX25P20ANDNX25P40

PACKAGING INFORMATION

8-Pin SOIC 150-mil (Package Code N)

SEATING PLANE

A2

A1

A

CP

b

E1

E

e

1

D

α

L

C

Package Dimensions⁽¹⁾

Millimeters

Inches

Typ.

Symbol

Min Typ. Max

Min

Max

A

1.47 1.60 1.72

0.058

0.004

0.063

0.068

0.009

A1

A2

b

0.10

0.24

1.45

0.057

0.016

0.33 0.41 0.50

0.19 0.20 0.25

4.80 4.85 4.95

5.80 6.00 6.19

3.80 3.90 4.00

1.27 BSC

0.013

0.0075

0.189

0.228

0.150

0.020

0.0098

0.195

0.244

0.157

Notes:

1. Controlling dimensions: inches,

unless otherwise specified.

2. BSC = Basic lead spacing between

centers.

3. Dimensions D and E1 do not include

mold flash protrusions and should

be measured from the bottom of the

package.

C

D⁽³⁾

0.008

0.191

E

0.236

E1⁽³⁾

e⁽²⁾

L

0.154

0.050 BSC

0.028

0.40 0.71 1.27

0.015

0^o

0.050

8^o

0^o

8^o

4. Formed leads shall be planar with

respect to one another within .0004

inches at the seating plane.

α

CP

0.10

0.004

26

NexFlashTechnologies, Inc.

PRELIMINARY MKP-0009 Rev 6 NXSF040I-0405

04/04/05 ©

1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI

NX25P10,NX25P20ANDNX25P40

PRELIMINARY DESIGNATION

LIFE SUPPORT POLICY

The “Preliminary” designation on a NexFlash data sheet

indicates that the product is not fully characterized. The

specifications are subject to change and are not guaran-

teed. NexFlash or an authorized sales representative

shouldbeconsultedforcurrentinformationbeforeusingthis

product.

NexFlash does not recommend the use of any of it's

products in life support applications where the failure or

malfunctionoftheproductcanreasonablybeexpectedto

cause failure in the life support system or to significantly

affect its safety or effectiveness. Products are not

authorized for use in such applications unless NexFlash

receives written assurances, to it’s satisfaction, that:

1

2

IMPORTANT NOTICE

(a) the risk of injury or damage has been minimized;

(b) the user assumes all such risks; and

NexFlash reserves the right to make changes to the

products contained in this publication in order to improve

design, performance or reliability. NexFlash assumes no

responsibility for the use of any circuits described herein,

conveys no license under any patent or other right, and

makesnorepresentationthatthecircuitsarefreeofpatent

infringement.Chartsandschedulescontainedhereinreflect

representative operating parameters, and may vary de-

pending upon a user’s specific application. While the

information in this publication has been carefully checked,

NexFlash shall not be liable for any damages arising as a

result of any error or omission.

3

(c) potential liability of NexFlash is adequately pro-

tected under the circumstances.

4

TRADEMARKS

NexFlash and spiFlash are trademarks of NexFlash

Technologies, Inc. All other marks are the property of their

respectiveowner.

5

ORDERING INFORMATION

6

NX 25P xx - V x I - xx..

Company Prefix

NX = NexFlash

7

Product Family

25P = spiFlash Serial Flash Memory

Product Number / Density

8

10 = 1M-bit

20 = 2M-bit

40 = 4M-bit

Supply Voltage

9

V = 2.7V to 3.6V

Package Type

N = 8-pin SOIC 150-mil

P = 8-contact MLP 6x5mm

10

11

12

*

Temperature Range

I

= Industrial (–40˚C to +85˚C)

Special Options

(Blank) Standard Package

G = Green Package (Lead-Free, RoHS compliant)

C = Customer Specification (For factory programming and other custom specifications)

T = Tape and Reel

Contact NexFlash for availability of this package.

*

NexFlashTechnologies, Inc.

27

PRELIMINARY MKP-0009 Rev 6 NXSF040I-0405

04/04/05 ©

1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI

NX25P10,NX25P20ANDNX25P40

Document Revision History

Date

Rev

DescriptionofRevision

04/29/03

09/12/03

A

DocumentWritten

B

Incorporated spiFlash trademark for NX25P10, 20 and 40 product

family. Adjusted data for consistency

03/09/04

03/24/04

05/11/04

06/16/04

11/23/04

C

D

E

F

Adjusted pages 10, 11, 14, 16 and 24 for technical clarity. Updated

SpecialOptionsandOrderingInformation

MLP metal die pad notification; Under "Package Types," figure 3 and

packaginginformation.

Corrected dimensions in Packaging Information section for 6x5mm MLP.

UpdatedCharacterizationinformationDC(Table8)&AC(Table10).

Modified dimensional data in the Packaging Information for the 6x5mm

MLP package

G

Added FR = 40MHz @ 3.0V to 3.6V Vcc. Added fR = 33MHz @ 3.0V

to 3.6V Vcc. Modified t^LEADin Absolute Maximum Ratings (Table 5) to

reference JEDEC Standard information. Added FR and fR conditions to

Operating Ranges (Table 6). Updated ICC3 and ICC5 data in DC Electri-

cal Characteristics (Table 8). Added 20/33MHz call outs and updated

min, max and typ data in AC Electrical Characteristics (Table 10).

12/08/04

04/04/05

H

I

Updated 8-pin 150mil SOIC package information.

Removed 8-contact 6x5 MLP package from document.

28

NexFlashTechnologies, Inc.

PRELIMINARY MKP-0009 Rev 6 NXSF040I-0405

04/04/05 ©

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