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IX2R11

型号：

IX2R11

描述：

2A半桥驱动器[ 2A Half-Bridge Driver ]

品牌：

IXYS[ IXYS CORPORATION ]

页数：

6 页

PDF大小：

617 K

下载PDF手册
Preliminary Data Sheet  
IX2R11  
2A Half-Bridge Driver  
Features  
General Description  
• Floating High Side Driver with boot-strap Power  
supply along with a Low Side Driver.  
• Fully operational to 650V  
The IX2R11 Bridge Driver for N-channel MOSFETs and IGBTs  
with a high side and low side output, whose input signals  
reference the low side. The High Side driver can control a  
MOSFET or IGBT connected to a positive buss voltage up to  
650V. The logic input stages are compatible with TTL or  
CMOS, have built-in hysteresis and are fully immune to latch  
up over the entire operating range. The IX2R11 can withstand  
dV/dt on the output side up to ± 50V/ns.  
• ± 50V/ns dV/dt immunity  
• Gate drive power supply range: 10 - 35V  
• Undervoltage lockout for both output drivers  
• Separate Logic power supply range: 3.3V to VCL  
• Built using the advantages and compatibility  
of CMOS and IXYS HDMOSTM processes  
• Latch-Up protected over entire  
The IX2R11 comes in either the 16-PIN SOIC package  
(IX2R11S3) or the 14-PIN DIP through-hole package  
(IX2R11P7)  
operating range  
• High peak output current: 2A  
• Matched propagation delay for both outputs  
• Low output impedance  
• Low power supply current  
Applications  
• Immune to negative voltage transients  
• Driving MOSFETs and IGBTs in half-bridge circuits  
• High voltage, high side and low side drivers  
• Motor Controls  
• Switch Mode Power Supplies (SMPS)  
• DC to DC Converters  
Warning: The IX2R11 is ESD sensitive.  
Figure 1. Typical Circuit Connection  
• Class D Switching Amplifiers  
Copyright © IXYS CORPORATION 2004  
DS99165A(08/04)  
First Release  
IX2R11  
Figure 2 - IX2R11 Functional Block Diagram  
VDD  
VCH  
VCH  
HGO  
Low to  
HIN  
High  
OUT  
Gate Current  
Output  
HIN  
RST  
IN  
HIN  
UVCC  
Detect  
DG  
HS  
Isolated High Side  
VCL  
HS  
VCL  
VDD  
LIN  
Low to High  
Side Delay  
Equalizer  
and  
Shutdown  
Gate Current  
Output  
LGO  
Shutdown  
Logic  
ENB  
DG  
UVCC  
Detect  
DG  
LS  
LS  
1 Ohm  
Pin Description And Configuration  
SYMBOL  
VDD  
HIN  
FUNCTION  
Logic Supply  
HS Input  
DESCRIPTION  
Positive power supply for the chip CMOS functions  
High side Input signal, TTL or CMOS compatible; HGO in phase  
Low side Input signal, TTL or CMOS compatible; LGO in phase  
Chip enable. When driven high, both outputs go low.  
Logic Reference Ground  
LIN  
LS Input  
ENB  
DG  
Not Enable  
Ground  
VCH  
HGO  
HS  
Supply Voltage  
Output  
High Side Power Supply  
High side driver output  
Return  
High side voltage return pin  
VCL  
Supply Voltage  
Low side power supply. This power supply provides power for  
both outputs. Voltage range is from 4.5 to 25V.  
Low side driver output  
LGO  
LS  
Output  
Ground  
Low side return  
14-PIN DIP  
16-PIN SOIC  
8
7
N/C  
VDD  
HIN  
ENB  
LIN  
HGO  
9
6
VCH  
HS  
10  
11  
12  
13  
14  
5
4
3
2
1
N/C  
VCL  
LS  
DG  
NC  
LGO  
2
IX2R11  
Absolute Maximum Ratings  
Symbol  
Definition  
Min  
-25  
Max  
650  
Units  
V
VCH  
High side floating supply voltage  
VHS  
VHGO  
VCL  
High side floating supply offset voltage  
High side floating output voltage  
Low side fixed supply voltage  
Low side output voltage  
VCH-200  
VHS-.3  
-0.3  
VCH+.3  
VCH+.3  
35  
V
V
V
V
V
V
V
VLGO  
VDD  
VDG  
VIN  
-0.3  
VCL+.3  
VDG+35  
VLS+3.8  
VDD+.3  
Logic supply voltage  
-0.3  
Logic supply offset voltage  
Logic input voltage(HIN & LIN)  
VLS-3.8  
VSS-.3  
dVS/dt  
PD  
PD  
RTHJA  
RTHJc  
Allowable offset supply voltage transient  
Package power dissipation@ TA ≤ 25C  
Package power dissipation@ TC ≤ 25C  
Thermal resistance, junction-to-ambient  
Thermal resistance, junction-to-case  
50  
1.25  
2.5  
100  
50  
V/ns  
W
W
K/W  
K/W  
TJ  
TS  
TL  
Junction Temperature  
150  
150  
300  
oC  
oC  
oC  
Storage temperature  
-55  
Lead temperature (soldering, 10 s)  
Recommended Operating Conditions  
Symbol  
VCH  
Definition  
Min  
Max  
VHS+20  
650  
VCH+20  
20  
Units  
V
V
V
V
V
V
V
High side floating supply absolute voltage VHS+10  
VHS  
VHGO  
VCL  
VLGO  
VDD  
High side floating supply offset voltage  
High side floating output voltage  
Low side fixed supply voltage  
Low side output voltage  
-20  
VHS  
10  
0
VCC  
Logic supply voltage  
VDG+3  
VLS-1  
VDG  
-40  
VDG+20  
VLS+1  
VDD  
VDG  
VIN  
TA  
Logic supply voffset voltage  
Logic input voltage(HIN, LIN, ENbar)  
Ambient Temperature  
V
125  
oC  
Ordering Information  
Part Number  
Package Type  
IX2R11P7  
IX2R11S3  
14-PIN DIP  
16-PIN SOIC  
3
IX2R11  
Dynamic Electrical Characteristics  
Symbol Definition  
Test Conditions  
Min  
Typ  
Max Units  
ton  
Turn-on propagation delay  
VHS= 0V, Cload= 2nF  
120  
ns  
toff  
tenb  
tr  
Turn-off propagation delay  
Device Not enable delay  
Turn-on rise time  
VHS= 600V, Cload= 2nF  
87  
202  
23  
ns  
ns  
ns  
ns  
Cload= 2nF  
Cload= 2nF  
tf  
Turn-off fall time  
22  
tdm  
Delay matching, HS & LS turn-on/off Cload= 2nF  
10  
20  
ns  
Static Electrical Characteristics  
Symbol  
Definition  
Test Conditions  
Min  
Typ  
Max Units  
VINH  
VINL  
Logic “1” input voltage  
Logic “0” input voltage  
VDD= VCL= 15V  
VDD= VCC= 15V  
IO= 0A  
7.0  
V
6
V
V
VHLGO // VHHGO High level output voltage,  
VCH-VHGO or VCL-VLGO  
0.28  
.23  
VLLGO // VLHGO High level output voltage,  
VHGO or VLGO  
IO= 0A  
V
IHL  
HS to LS bias current.  
VHS= VCH= 600V  
VIN= 0V or VDD  
VIN= 0V or VDD  
VIN= 0V or VDD  
VIN= VDD  
.17  
.77  
.79  
36  
2
mA  
mA  
mA  
uA  
uA  
uA  
V
IQHS  
IQLS  
Quiescent VCH supply current  
Quiescent VCL supply current  
Quiescent VDD supply current  
Logic “1” input bias current  
Logic “0” input voltage  
IQDD  
IIN+  
IIN-  
VIN= 0V  
1
VCHUV  
VCHUV  
+
-
VCH supply undervoltage positive going threshold.  
VCH supply undervoltage negative going threshold.  
VCL supply undervoltage positive going threshold  
VCL supply undervoltage negative going threshold.  
8.3  
8.2  
8.1  
8.0  
V
VCLUV  
VCLUV  
IGO+  
IGO-  
+
V
-
V
HS or LS Output low short circuit current; VGO= 15V, VIN= 0V, PW<10us +2  
HS or LS Output low short circuit current; VGO= 15V, VIN=0V, PW<10us  
A
-2  
A
Timing Waveform Definitions  
ENB  
HIN/LIN  
ENB  
50%  
tenb  
10%  
LGO/HGO  
LGO/HGO  
Figure 3. INPUT/OUPUT Timing Diagram  
Figure 4. ENABLE Waveform Definitions  
4
IX2R11  
Timing Waveform Definitions  
Figure 5. Definitions of Switching Time Waforms  
Figure 6. Definitions of Delay Matching Waveforms  
50%  
tr  
50%  
50%  
50%  
HIN  
LIN  
HIN  
LIN  
Input Signal  
tdoff  
90%  
tf  
tdon  
90%  
tdm  
90%  
LGO  
HGO  
10%  
HGO  
LGO  
LGO  
HGO  
10%  
10%  
tdm  
Outgoing Signal  
15V  
C2  
10uF  
+
C5  
0.1uF  
U1  
9
8
7
6
5
4
3
2
1
HS  
NC  
HGO  
VCH  
HS  
NC  
NC  
HGO  
HS  
OUTPUT MONITOR  
HV SCOPE PROBE  
10  
11  
12  
13  
14  
15  
16  
GND2  
GND2  
VDD  
HIN  
ENB  
LIN  
DG  
LS  
L1  
200uH  
D1  
DSEI12-10A  
100uF/250V  
VCL  
LS  
LGO  
C1  
+
C3  
+
10uF  
C6  
0.1uF  
U2  
15V  
1
18V  
3
Vin  
Vout  
GND1  
V1  
dVs/dt > 50v/ns  
HV  
600V  
GND1  
BATTERY  
15V  
V3  
C8  
0.1uF  
C9  
10uF  
Measure dVdt ( HV Scope Probe )  
PULSE  
VCC  
16  
Q1  
U3  
BNC  
2
3
U2  
D2  
1,8  
DSEI12-10A  
6,7  
OUT  
15  
2
IXDD414  
HCPL-314J  
4,5  
GND2  
14  
VEE  
IXFP4N100Q  
1/2  
GND3  
-600V  
GND3  
Figure 7. Test circuit for allowable offset supply voltage transient.  
5
IX2R11  
IX2R11S3 Package Outline  
IX6211P7 Package Outline  
IXYS Corporation  
IXYS Semiconductor GmbH  
3540 Bassett St; Santa Clara, CA 95054  
Tel: 408-982-0700; Fax: 408-496-0670  
e-mail: sales@ixys.net  
Edisonstrasse15 ; D-68623; Lampertheim  
Tel: +49-6206-503-0; Fax: +49-6206-503627  
e-mail: marcom@ixys.de  
www.ixys.com  
99165(04/04)  
6
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