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NX2305CMTR

型号：

NX2305CMTR

描述：

与NMOS LDO控制器， POWER GOOD ＆支持单电源12V同步PWM控制器[ SINGLE SUPPLY 12V SYNCHRONOUS PWM CONTROLLER WITH NMOS LDO CONTROLLER, POWER GOOD & ENABLES ]

品牌：

MICROSEMI[ Microsemi ]

页数：

19 页

PDF大小：

579 K

下载PDF手册
Evaluation board available.  
NX2305  
SINGLE SUPPLY 12V SYNCHRONOUS PWM CONTROLLER  
WITH NMOS LDO CONTROLLER, POWER GOOD & ENABLES  
PRELIMINARY DATA SHEET  
Pb Free Product  
FEATURES  
DESCRIPTION  
n 12V PWM controller plus LDO controller  
The NX2305 controller IC is a combination synchronous  
Buck and LDO controller IC designed to convert single  
12V supply to low cost dual on board supply applica-  
tions. The synchronous controller is used for high cur-  
rent high efficiency step down DC to DC converter appli-  
cations while the LDO controller in conjunction with an  
external low cost N ch MOSFET can be used as a very  
low drop out regulator in applications such as converting  
3.3V to 2.5V output. Internal UVLO keeps both regula-  
tors off until the supply voltage exceeds 9V where inde-  
pendent internal digital soft starts get initiated to ramp  
up both outputs.The switching section has hiccup cur-  
rent limit by sensing the Rdson of synchronous MOSFET.  
The LDO controller has Feedback Under Voltage Lock  
Out as a short circuit protection.Other features includes:  
12V gate drive capability , Adaptive dead band control,  
Power good flag for the switcher controller and separate  
Enable pins for independent power sequencing.  
n Hiccup current limit by sensing Rdson of MOSFET  
12V high side and low side driver  
n Fixed internal 300kHz for switching controller  
n Dual Independent Digital Soft Start Function  
n Adaptive Deadband Control  
n Enable pin available to program the Vbus UVLO  
n Shut Down switching and LDO via pulling down  
EnSW or ENLDO pins  
n
n Pb-free and RoHS compliant  
APPLICATIONS  
n
n
n
PCI Graphic Card on board converters  
Mother board On board DC to DC applications  
On board Single Supply 12V DC to DC such as  
12V to 3.3V, 2.5V or 1.8V  
n
Set Top Box and LCD Display  
TYPICAL APPLICATION  
10  
R14  
C11  
open  
C12  
1uF  
0.1uF  
C1  
VCC  
5V REG  
PVCC  
R6  
10k  
L1 1uH  
1N4148  
VIN2  
VIN1  
+12V  
PGOOD  
+3.3V  
C3  
100uF  
LDO OUT  
C2  
180uF  
C9  
47uF  
M5  
BST  
C4  
0.1uF  
M1  
C10 150pF  
VOUT2  
+1.6V/2A  
IRFR3709Z  
HDRV  
SW  
LDO FB  
ENLDO  
C8  
R8  
5k  
L2 2.2uH  
R9  
5k  
VOUT1  
150uF  
25mohm  
+1.8V/10A  
C7  
2 x 470uF  
R10  
VIN2  
+3.3V  
OCP  
LDRV  
PGND  
R11  
1.4k  
M2  
0.75k  
R1  
4k  
M3  
IRFR3709Z  
R2  
1.1k  
R3  
10k  
HI=SD  
C6  
3.9nF  
R12  
6.8k  
VIN1  
+12V  
FB  
ENSW  
C5  
R5  
10k  
R4  
8k  
R13  
1.4k  
COMP  
M4  
5.6nF  
AGND  
HI=SD  
C13 100pF  
Figure1 - Typical application of NX2305  
ORDERING INFORMATION  
Device  
NX2305CMTR  
NX2305CSTR  
Temperature  
0 to 70oC  
Package  
MLPQ-16L  
SOIC -16L  
Frequency  
300kHz  
300kHz  
Pb-Free  
Yes  
Yes  
0 to 70oC  
Rev.5.0  
08/19/08  
1
NX2305  
ABSOLUTE MAXIMUM RATINGS  
Vcc to PGND & BST to SW voltage .................... -0.3V to 16V  
BST to PGND Voltage ...................................... -0.3V to 35V  
SW to PGND .................................................... -2V to 35V  
All other pins .................................................... -0.3V to 6.5V  
Storage Temperature Range ............................... -65oC to 150oC  
Operating Junction Temperature Range ............... -40oC to 125oC  
CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to  
the device. This is a stress only rating and operation of the device at these or any other conditions above those  
indicated in the operational sections of this specification is not implied.  
PACKAGE INFORMATION  
16-LEAD PLASTIC MLPQ  
16-LEAD PLASTIC SOIC  
qJA » 83oC/W  
qJA » 46oC/W  
13  
16 15 14  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
BST  
HDRV  
SW  
OCP  
HDRV  
FB  
1
12  
11  
10  
9
GND  
COMP  
FB  
PGOOD  
EN-SW  
EN-LDO  
5V REG  
PGOOD  
EN-SW  
EN-LDO  
PGND 2  
17  
AGND  
LDRV  
PVCC  
LDRV  
PVCC  
3
4
VCC  
LDO-OUT  
LDO-FB  
7
5
8
6
ELECTRICAL SPECIFICATIONS  
Unless otherwise specified, these specifications apply over Vcc =12V, VBST-VSW=12V, ENSW=ENLDO=3V, and TA  
= 0 to 70oC. Typical values refer to TA = 25oC.  
PARAMETER  
Reference Voltage  
Ref Voltage  
SYM  
Test Condition  
Min  
8.2  
8.2  
TYP  
MAX Units  
VREF  
0.8  
0.2  
V
Ref Voltage line regulation  
Supply Voltage(Vcc&VBST  
VCC Voltage Range  
VCC Supply Current  
(Static)  
10V<=Vcc<=14V  
%
)
VCC  
V
14  
14  
ICC (Static) ENSW=LOW  
ENLDO=LOW  
8
mA  
PVCC Supply Current  
(Dynamic)  
ICC  
(Dynamic)  
CL=3300pF  
8.5  
mA  
VBST Voltage Range  
VBST to VSW  
V
VBST Supply Current(Static)  
VBST (Static) ENSW=LOW  
ENLDO=LOW  
0.2  
mA  
Rev.5.0  
08/19/08  
2
NX2305  
PARAMETER  
VBST Supply Current  
(Dynamic)  
SYM  
VBST  
Test Condition  
CL=3300PF  
Min  
TYP  
9.2  
MAX Units  
mA  
(dynamic)  
Under Voltage Lockout  
VCC-Threshold  
VCC_UVLO VCC Rising (NOTE1)  
VCC Falling (NOTE1)  
6.8  
V
VCC hysterises  
300  
mV  
Oscillator (Rt)  
Frequency  
FS  
300  
1.1  
94  
KHz  
V
Ramp-Amplitude Voltage  
Max Duty Cycle  
Min duty Cycle  
VRAMP  
%
%
0
Error Amplifiers  
Open Loop Gain  
Transconductance  
Comp SD threshold  
Input Bias Current  
EN & SS  
50  
65  
2000  
0.2  
dB  
umho  
V
gm  
Ib  
100  
nA  
Soft Start time  
Tss  
6.8  
1.24  
30  
mS  
V
Enable HI Threshold  
Enable Hysterises  
VENTHH  
VENTHL  
mV  
High Side Driver, Hdrv, BST,  
SW (CL=3300pF)  
Output Impedance , Sourcing Rsource(Hdrv)  
Current  
I=200mA  
I=200mA  
3.6  
1
ohm  
ohm  
Output Impedance , Sinking  
Current  
Rsink(Hdrv)  
Rise Time  
Fall Time  
THdrv(Rise)  
THdrv(Fall)  
10% to 90%  
90% to 10%  
30  
20  
50  
ns  
ns  
ns  
Deadband Time  
Tdead(L to Ldrv going Low to Hdrv going  
N
H)  
High, 10% to 10%  
Low Side Driver , Ldrv,  
PVcc, Pgnd(CL=3300pF)  
Output Impedance, Sourcing Rsource(Ldrv)  
Current  
I=200mA  
I=200mA  
2.2  
1
ohm  
ohm  
Output Impedance, Sinking  
Current  
Rsink(Ldrv)  
Rise Time  
TLdrv(Rise)  
TLdrv(Fall)  
10% to 90%  
90% to 10%  
30  
20  
50  
ns  
ns  
ns  
Fall Time  
Deadband Time  
Tdead(H to SW going Low to Ldrv going  
L) High, 10% to 10%  
LDO Controller  
FB Pin- Bias Current  
High Output Voltage  
Low Output Voltage  
High Output Source Current  
uA  
V
1
11.1  
0.2  
V
1.9  
mA  
Rev.5.0  
08/19/08  
3
NX2305  
PARAMETER  
Open Loop Gain  
SYM  
Test Condition  
GBNT(Note 2)  
Min  
TYP  
MAX Units  
dB  
%
50  
FB Under Voltage trip point  
50  
Power Good(Pgood)  
Threshold Voltage as % of  
Vref  
FB ramping up  
90  
5
%
%
Hysteresis  
OCP Adjust  
OCP Current Setting  
40  
uA  
NOTE1: VCC is connected to ENSW pin via a resistor divider. In VCC UVLO test, ENSW pin is open.  
NOTE2: This parameter is guaranteed by design but not tested in production(GBNT).  
Rev.5.0  
08/19/08  
4
NX2305  
PIN DESCRIPTIONS  
PIN SYMBOL  
PIN DESCRIPTION  
IC’s supply voltage. This pin biases the internal logic circuits. A high freq 1uF ceramic capacitor  
is placed as close as possible to and connected to this pin and ground pin. The maximum rating  
of this pin is 16V.  
VCC  
This pin supplies voltage to high side FET driver. A high freq 0.1uF ceramic capacitor is placed as  
close as possible to and connected to these pins and SW pin.  
BST  
A resistor divider is connected from the LDO bus voltage to this pin that holds off the LDO soft start  
until this threshold is reached. An external low cost MOSFET can be connected to this pin for  
external enable control.  
ENLDO  
A resistor divider is connected from the respective switcher BUS voltage to this pin that holds off  
the controller's soft start until this threshold is reached. An external low cost MOSFET can be  
connected to this pin for external enable control.  
ENSW  
This pin is the error amplifier inverting input. This pin is connected via resistor divider to the output  
of the switching regulator to set the output DC voltage.  
FB  
This pin is the output of error amplifier and is used to compensate the voltage control feedback  
loop.  
COMP  
OCP  
This pin is connected to the drain of the external low side MOSFET and is the input of the over  
current protection(OCP) comparator. An internal current source 40uA is flown to the external  
resistor which sets the OCP voltage across the Rdson of the low side MOSFET. Current limit  
point is this voltage divided by the Rds-on. Once this threshold is reached the Hdrv and Ldrv pins  
are switched low and an internal hiccup circuit is set that recycles the soft start circuit after 2048  
switching cycles.  
This pin is connected to source of high side FET and provides return path for the high side driver.  
It is also used to hold the low side driver low until this pin is brought low by the action of high side  
turning off. LDRV can only go high if SW is below 1V threshold .  
SW  
High side gate driver output.  
Low side gate driver output.  
HDRV  
LDRV  
PVCC  
Supply voltage for the low side fet driver. A high frequency 1uF ceramic cap must be connected  
from this pin to the PGND pin as close as possible.  
LDO controller feedback input. This pin is connected via resistor divider to the output of the  
switching regulator to set the output DC voltage.If the LDOFB pin is pulled below 0.4V, an internal  
comparator after a delay pulls down LDOOUT pin and initiates the HICCUP circuitry. During the  
startup this latch is not activated, allowing the LDOFB pin to come up and follow the soft started  
Vref voltage.  
LDO_FB  
LDO controller output. This pin is controlling the gate of an external NCH MOSFET. The maximum  
rating of this pin is 16V.  
LDO_OUT  
5V REG  
Output of an internal 5V regulator.  
Rev.5.0  
08/19/08  
5
NX2305  
PIN SYMBOL  
PIN DESCRIPTION  
An open drain output that requires a pull up resistor to Vcc or a voltage lower than Vcc. When  
FB pin reaches 90% of the reference voltage PGOOD transitions from LO to HI state.  
PGOOD  
Power ground pin for low side driver. In SOIC16 package, PGND andAGND are combined  
together called GND.  
PGND  
A((  
Analog ground. In MLPD16 package, pad isAGND.  
AGND  
Rev.5.0  
08/19/08  
6
NX2305  
BLOCK DIAGRAM  
PGOOD  
BST  
FB  
0.9Vref  
/0.85Vref  
1.25V  
0.8V  
Bias  
Generator  
5VREG  
Bias  
Regulator  
UVLO  
POR  
VCC  
90k  
20k  
START  
ENSW_HI  
HDRV  
SW  
ENSW  
VENTHH  
VENTHL  
COMP  
0.2V  
OC  
Control  
Logic  
START  
0.8V  
PWM  
OC  
OSC  
ramp  
PVCC  
LDRV  
PGND  
Digital  
start Up  
S
R
Q
FB  
0.6V  
CLAMP  
I
OCP  
40uA  
1.3V  
CLAMP  
COMP  
OCP  
Hiccup Logic  
0.4  
START  
OCP  
comparator  
GND  
FBLDO  
ENLDO  
LDOOUT  
LDO digital  
start up  
POR  
ENSW_HI  
1.25/1.15  
Figure 2 - Simplified block diagram of the NX2305  
Rev.5.0  
08/19/08  
7
NX2305  
APPLICATION INFORMATION  
V -VOUT VOUT  
1
IN  
IRIPPLE  
=
´
´
´
LOUT  
V
F
S
IN  
...(2)  
Symbol Used In Application Information:  
12V-1.8V 1.8V  
1
=
´
= 2.3A  
VIN  
- Input voltage  
- Output voltage  
- Output current  
2.2uH  
12V 300kHz  
VOUT  
IOUT  
Output Capacitor Selection  
∆VRIPPLE - Output voltage ripple  
Output capacitor is basically decided by the  
amount of the output voltage ripple allowed during steady  
state(DC) load condition as well as specification for the  
load transient. The optimum design may require a couple  
of iterations to satisfy both condition.  
FS  
- Switching frequency  
- Inductor current ripple  
∆IRIPPLE  
Design Example  
Power stage design requirements:  
VIN=12V  
Based on DC Load Condition  
The amount of voltage ripple during the DC load  
condition is determined by equation(3).  
VOUT=1.8V  
DIRIPPLE  
IOUT =10A  
DVRIPPLE = ESR´ DIRIPPLE  
+
...(3)  
8´ F ´ COUT  
∆VRIPPLE <=20mV  
∆VTRAN<=100mV @ 10A step  
FS=300kHz  
S
Where ESR is the output capacitors' equivalent  
series resistance,COUT is the value of output capacitors.  
Typically when large value capacitors are selected  
such as Aluminum Electrolytic,POSCAP and OSCON  
types are used, the amount of the output voltage ripple  
is dominated by the first term in equation(3) and the  
second term can be neglected.  
Output Inductor Selection  
The selection of inductor value is based on induc-  
tor ripple current, power rating, working frequency and  
efficiency. Larger inductor value normally means smaller  
ripple current. However if the inductance is chosen too  
large, it brings slow response and lower efficiency. Usu-  
ally the ripple current ranges from 20% to 40% of the  
output current. This is a design freedom which can be  
decided by design engineer according to various appli-  
cation requirements. The inductor value can be calcu-  
lated by using the following equations:  
For this example, POSCAP are chosen as output  
capacitors, the ESR and inductor current typically de-  
termines the output voltage ripple.  
DVRIPPLE  
DIRIPPLE  
20mV  
2.3A  
ESRdesire  
=
=
= 8.7mW  
...(4)  
If low ESR is required, for most applications, mul-  
tiple capacitors in parallel are better than a big capaci-  
tor. For example, for 20mV output ripple, POSCAP  
2R5TPE470M9 with 9mW are chosen.  
V -VOUT VOUT  
1
IN  
LOUT  
=
´
´
IRIPPLE  
V
F
S
IN  
...(1)  
IRIPPLE =k ´ IOUTPUT  
E S R E ´ DIR IPPLE  
N =  
...(5)  
D VR IPPLE  
where k is between 0.2 to 0.4.  
Select k=0.3, then  
Number of Capacitor is calculated as  
12V-1.8V 1.8V  
1
9mW´ 2.3A  
N =  
LOUT  
=
´
´
0.3´ 10A 12V 300kHz  
LOUT =1.7uH  
20mV  
N =1.03  
Choose LOUT=2.2uH, then coilcraft inductor  
DO5010P-222HC is a good choice.  
Current Ripple is calculated as  
The number of capacitor has to be round up to a  
integer. Choose N =2.  
Rev.5.0  
08/19/08  
8
NX2305  
If ceramic capacitors are chosen as output ca- put inductor is smaller than the critical inductance, the  
pacitors, both terms in equation (3) need to be evalu- voltage droop or overshoot is only dependent on the ESR  
ated to determine the overall ripple. Usually when this of output capacitor. For low frequency capacitor such  
type of capacitors are selected, the amount of capaci- as electrolytic capacitor, the product of ESR and ca-  
tance per single unit is not sufficient to meet the tran-  
sient specification, which results in parallel configura-  
tion of multiple capacitors.  
pacitance is high and L £ Lcrit is true. In that case, the  
transient spec is mostly like to dependent on the ESR  
of capacitor.  
For example, one 100uF, X5R ceramic capacitor  
with 2mW ESR is used. The amount of output ripple is  
Most case, the output capacitor is multiple capaci-  
tor in parallel. The number of capacitor can be calcu-  
lated by the following  
2.3A  
DVRIPPLE = 2mW´ 2.3A +  
8´ 300kHz´ 100uF  
ESRE ´ DIstep  
VOUT  
N =  
+
´ t 2  
...(9)  
= 4.6mV +9.6mV =14.2mV  
DV  
2´ L´ CE ´ DV  
tran  
tran  
Although this meets DC ripple spec, however it  
needs to be studied for transient requirement.  
where  
0
if L £ Lcrit  
ì
ï
L´ DI  
t =  
Based On Transient Requirement  
Typically, the output voltage droop during transient  
is specified as  
í
ï
î
step  
...(10)  
- ESRE ´ CE  
if L ³ Lcrit  
VOUT  
DV  
< DV  
@step load ∆I  
tran  
droop  
STEP  
For example, assume voltage droop during tran-  
sient is 100mV for 10A load step.  
During the transient, the voltage droop during the  
transient is composed of two sections. One section is  
dependent on the ESR of capacitor, the other section is  
a function of the inductor, output capacitance as well  
as input, output voltage. For example, for the over-  
shoot when load from high load to light load with a  
∆ISTEP transient load, if assuming the bandwidth of  
system is high enough, the overshoot can be esti-  
mated as the following equation.  
If the POSCAP 2R5TPE470M9 (470uF, 9mohm  
ESR) is used, the crticial inductance is given as  
ESRE ´ CE ´ VOUT  
Lcrit  
=
=
DIstep  
9mW´ 470mF´ 1.8V  
= 0.76mH  
10A  
The selected inductor is 2.2uH which is bigger than  
critical inductance. In that case, the output voltage tran-  
sient not only dependent on the ESR, but also capaci-  
tance.  
VOUT  
DVovershoot = ESR ´ DIstep  
+
´ t 2  
...(6)  
2´ L´ COUT  
where is the a function of capacitor,etc.  
t
number of capacitor is  
0
if L £ Lcrit  
ì
L´ DIstep  
ï
t =  
- ESRE ´ CE  
L´ DI  
t =  
í
ï
î
step  
VOUT  
...(7)  
...(8)  
- ESR ´ COUT  
if L ³ Lcrit  
VOUT  
2.2mH´ 10A  
=
- 9mW´ 470mF = 7.97us  
where  
ESR ´ COUT ´ VOUT ESRE ´ CE ´ VOUT  
1.8V  
Lcrit  
=
=
ESRE ´ DIstep  
VOUT  
N =  
+
´ t 2  
DIstep  
DIstep  
DV  
2´ L´ CE ´ DV  
tran  
tran  
where ESRE and CE represents ESR and capaci-  
tance of each capacitor if multiple capacitors are used  
in parallel.  
9mW´ 10A  
1.8V  
2´ 2.2mH´ 470mF´ 100mV  
=
+
´ (7.97us)2  
100mV  
=1.44  
The above equation shows that if the selected out-  
Rev.5.0  
08/19/08  
9
NX2305  
The number of capacitors has to satisfied both ripple  
and transient requirement. Overall, we choose N=2.  
It should be considered that the proposed equa-  
tion is based on ideal case, in reality, the droop or over-  
shoot is typically more than the calculation. The equa-  
tion gives a good start. For more margin, more capaci-  
tors have to be chosen after the test. Typically, for high  
frequency capacitor such as high quality POSCAP es-  
pecially ceramic capacitor, 20% to 100% (for ceramic)  
more capacitors have to be chosen since the ESR of  
capacitors is so low that the PCB parasitic can affect  
the results tremendously. More capacitors have to be  
selected to compensate these parasitic parameters.  
1
FZ1  
FZ2  
=
=
=
=
...(11)  
...(12)  
...(13)  
...(14)  
2´ p ´ R4 ´ C2  
1
2´ p ´ (R2 + R3 )´ C3  
1
F
P1  
2´ p ´ R3 ´ C3  
1
F
P2  
C1 ´ C2  
2´ p ´ R4 ´  
C1 + C2  
where FZ1,FZ2,FP1 and FP2 are poles and zeros in  
the compensator.  
The transfer function of type III compensator for  
transconductance amplifier is given by:  
Compensator Design  
Ve  
1- gm ´ Zf  
Due to the double pole generated by LC filter of the  
power stage, the power system has 180o phase shift ,  
and therefore, is unstable by itself. In order to achieve  
accurate output voltage and fast transient response,  
compensator is employed to provide highest possible  
bandwidth and enough phase margin. Ideally, the Bode  
plot of the closed loop system has crossover frequency  
between 1/10 and 1/5 of the switching frequency, phase  
margin greater than 50o and the gain crossing 0dB with -  
20dB/decade. Power stage output capacitors usually  
decide the compensator type. If electrolytic capacitors  
are chosen as output capacitors, type II compensator  
can be used to compensate the system, because the  
zero caused by output capacitor ESR is lower than cross-  
over frequency. Otherwise type III compensator should  
be chosen.  
=
VOUT  
1+ gm ´ Zin + Zin /R1  
For the voltage amplifier, the transfer function of  
compensator is  
Ve  
- Zf  
=
VOUT  
Zin  
To achieve the same effect as voltage amplifier,  
the compensator of transconductance amplifier must  
satisfy this condition: R4>>2/gm.And it would be desir-  
able if R1||R2||R3>>1/gm can be met at the same time.  
Zf  
Vout  
Zin  
R3  
C1  
C2  
R4  
R2  
R1  
A. Type III compensator design  
C3  
Fb  
For low ESR output capacitors, typically such as  
Sanyo oscap and poscap, the frequency of ESR zero  
caused by output capacitors is higher than the cross-  
over frequency. In this case, it is necessary to compen-  
sate the system with type III compensator. The follow-  
ing figures and equations show how to realize the type III  
compensator by transconductance amplifier.  
Ve  
gm  
Vref  
Figure 3 - Type III compensator using  
transconductance amplifier  
Rev.5.0  
08/19/08  
10  
NX2305  
R2 ´ VREF  
10kW´ 0.8V  
Case 1: FLC<FO<FESR  
R1=  
=
= 8kW  
VOUT -VREF  
1.8V-0.8V  
Choose R1=8kW.  
3. Set zero FZ2 = FLC and Fp1 =FESR  
.
power stage  
4. Calculate R4 and C3 with the crossover  
frequency at 1/10~ 1/5 of the switching frequency. Set  
FO=25kHz.  
LC  
F
40dB/decade  
1
1
1
C3 =  
´ (  
-
)
2´ p ´ R2  
F
F
p1  
z2  
1
1
1
loop gain  
=
´ (  
-
)
ESR  
F
2´ p ´ 10kW 3.5kHz 37.6kHz  
=4.1nF  
20dB/decade  
VOSC 2´ p ´ FO ´ L  
R4 =  
´
´ Cout  
V
C3  
1.1V 2´ p ´ 25kHz´ 2.2uH  
in  
compensator  
=
´
´ 940uF  
12V  
=10.4kW  
3.9nF  
Choose C3=3.9nF, R4=10.2k.  
5. Calculate C2 with zero Fz1 at 75% of the LC  
double pole by equation (11).  
FZ1  
FO  
FP2  
FZ2  
FP1  
1
C2 =  
Figure 4 - Bode plot of Type III compensator  
(FLC<FO<FESR  
2´ p ´ FZ1 ´ R4  
)
1
=
2´ p ´ 0.75´ 3.5kHz ´ 10.2kW  
= 5.95nF  
Typical design example of type III compensator in  
which the crossover frequency is selected as  
FLC<FO<FESR and FO<=1/10~1/5Fs is shown as the  
following steps.  
Choose C2=5.6nF.  
6. Calculate C1 by equation (14) with pole Fp2 at  
half the switching frequency.  
1. Calculate the location of LC double pole FLC  
1
and ESR zero FESR  
.
C1 =  
2´ p ´ R4 ´ F  
P2  
1
F
=
=
1
LC  
=
2´ p ´  
L
OUT ´ COUT  
2´ p ´ 10.2kW´ 150kHz  
= 104pF  
1
2´ p ´ 2.2uH´ 940uF  
Choose C1=100pF.  
= 3.5kHz  
7. Calculate R3 by equation (13).  
1
1
F
=
ESR  
R3 =  
2´ p ´ ESR´ COUT  
2´ p ´ F ´ C3  
P1  
1
1
=
=
2´ p ´ 4.5mW´ 940uF  
2´ p ´ 37.6kHz´ 3.9nF  
=1.1k W  
= 37.6kHz  
2. Set R2 equal to 10kW.  
Choose R3 =1.1kW.  
Rev.5.0  
08/19/08  
11  
NX2305  
Case 2: FLC<FESR<FO  
2. Set R2 equal to 15kW.  
R2 ´ VREF  
15kW´ 0.8V  
R1=  
=
= 12kW  
VOUT -VREF  
1.8V-0.8V  
Choose R1=12kW.  
3. Set zero FZ2 = FLC and Fp1 =FESR  
4. Calculate C3 .  
power stage  
.
LC  
F
40dB/decade  
1
1
1
C3 =  
´ (  
-
)
2´ p ´ R2  
F
F
p1  
z2  
ESR  
F
1
1
1
=
´ (  
-
)
loop gain  
2´ p ´ 15kW 2.77kHz 8.16kHz  
=2.5nF  
Choose C3=2.7nF.  
5. Calculate R3 .  
20dB/decade  
1
R3 =  
compensator  
2´ p ´ F ´ C3  
P1  
1
=
2´ p ´ 8.16kHz´ 2.7nF  
= 7.22kW  
FZ1  
FO  
FP2  
FZ2  
FP1  
Choose R3 =7.32kW.  
6. Calculate R4 with FO=30kHz.  
VOSC 2´ p ´ FO ´ L R2 ´ R3  
R4 =  
´
´
Figure 5 - Bode plot of Type III compensator  
(FLC<FESR<FO)  
V
ESR  
R2 + R3  
in  
1.1V 2´ p ´ 30kHz ´ 2.2uH 15kW´ 7.32kW  
=
´
´
12V  
=14.3kW  
Choose R4=14.3kW.  
13mW  
15kW+ 7.32kW  
If electrolytic capacitors are used as output  
capacitors, typical design example of type III  
compensator in which the crossover frequency is  
selected as FLC<FESR<FO and FO<=1/10~1/5Fs is shown  
as the following steps. Here one SANYO MV-WG1500  
with 13 mW is chosen as output capacitor.  
5. Calculate C2 with zero Fz1 at 75% of the LC  
double pole by equation (11).  
1
C2 =  
2´ p ´ F ´ R4  
Z1  
1. Calculate the location of LC double pole FLC  
1
=
and ESR zero FESR  
.
2´ p ´ 0.75´ 2.77kHz´ 14.3kW  
= 3.9nF  
1
F
=
=
LC  
Choose C2=3.9nF.  
6. Calculate C1 by equation (14) with pole Fp2 at  
half the switching frequency.  
2´ p ´  
L
OUT ´ COUT  
1
2´ p ´ 2.2uH´ 1500uF  
1
= 2.77kHz  
C1 =  
2´ p ´ R4 ´ F  
P2  
1
1
F
=
ESR  
=
2´ p ´ ESR´ COUT  
2´ p ´ 14.3kW´ 150kHz  
= 74pF  
1
=
2´ p ´ 13mW´ 1500uF  
Choose C1=82pF.  
= 8.16kHz  
Rev.5.0  
08/19/08  
12  
NX2305  
B. Type II compensator design  
C2  
C1  
If the electrolytic capacitors are chosen as power  
stage output capacitors, usually the Type II compensa-  
tor can be used to compensate the system.  
For this type of compensator, FO has to satisfy  
FLC<FESR<<FO<=1/10~1/5Fs.  
Vout  
R3  
R2  
Fb  
Ve  
gm  
R1  
Vref  
Case 1:  
Type II compensator can be realized by simple  
RC circuit as shown in figure 7. R3 and C1 introduce a  
zero to cancel the double pole effect. C2 introduces a  
Figure 7 - Type II compensator with  
transconductance amplifier(case 1)  
pole to suppress the switching noise.  
To achieve the same effect as voltage amplifier,  
the compensator of transconductance amplifier must  
The following parameters are used as an ex-  
ample for type II compensator design, three 1500uF  
with 19mohm Sanyo electrolytic CAP 6MV1500WGL  
are used as output capacitors. Coilcraft DO5010P-  
152HC 1.5uH is used as output inductor. See figure  
19. The power stage information is that:  
satisfy this condition: R3>>1/gm and R1||R2>>1/gm. The  
following equations show the compensator pole zero lo-  
cation and constant gain.  
R3  
Gain=  
... (15)  
... (16)  
... (17)  
R2  
VIN=12V, VOUT=1.2V, IOUT =12A, FS=300kHz.  
1.Calculate the location of LC double pole FLC  
1
F =  
z
2´ p ´ R3 ´ C1  
1
and ESR zero FESR  
.
F »  
p
1
2´ p ´ R3 ´ C2  
F
=
=
LC  
2´ p ´  
L
OUT ´ COUT  
1
2´ p ´ 1.5uH´ 4500uF  
= 1.94kHz  
power stage  
loop gain  
1
40dB/decade  
20dB/decade  
F
=
ESR  
2´ p ´ ESR´ COUT  
1
=
2´ p ´ 6.33mW´ 4500uF  
= 5.6kHz  
2.Set crossover frequency FO=30kHz>>FESR  
.
3. Set R2 equal to10kW. Based on output voltage,  
using equation 21, the final selection of R1 is 20kW.  
4.Calculate R3 value by the following equation.  
compensator  
Gain  
VO S C 2 ´ p ´ FO ´ L  
R 3 =  
´
´ R 2  
Vin  
E S R  
1.1V 2 ´ p ´ 30kHz ´ 1.5uH  
=
´
´ 10kW  
P
F
F
F
Z
LCFESR  
FO  
12V  
=37.2kW  
6.33m W  
Choose R3 =37.4kW.  
Figure 6 - Bode plot of Type II compensator  
Rev.5.0  
08/19/08  
13  
NX2305  
5. Calculate C1 by setting compensator zero FZ  
at 75% of the LC double pole.  
power stage  
loop gain  
1
C1=  
2´ p ´ R3 ´ F  
z
40dB/decade  
1
=
2´ p ´ 37.4kW´ 0.75´ 1.94kHz  
=2.9nF  
Choose C1=2.7nF.  
F
6. Calculate C2 by setting compensator pole  
at half the swithing frequency.  
p
20dB/decade  
1
C 2  
=
=
p ´ R ´ Fs  
3
compensator  
1
Gain  
p ´ 3 7 . 4k W ´ 1 5 0 k H z  
= 5 7 p F  
Choose C2=56pF.  
Case 2:  
P
F
F
F
Z
LCFESR  
FO  
Type II compensator can also be realized by simple  
RC circuit without feedback as shown in figure 9. R3 and  
C1 introduce a zero to cancel the double pole effect. C2  
introduces a pole to suppress the switching noise. The  
following equations show the compensator pole zero lo-  
cation and constant gain.  
Figure 8 - Bode plot of Type II compensator  
Vout  
R2  
Fb  
Ve  
gm  
R1  
R3  
Vref  
R1  
Gain=gm ´  
´ R3  
... (18)  
... (19)  
... (20)  
R1+R2  
C2  
C1  
1
F =  
z
2´ p ´ R3 ´ C1  
1
F »  
p
2´ p ´ R3 ´ C2  
Figure 9 - Type II compensator with  
transconductance amplifier  
For this type of compensator, FO has to satisfy  
FLC<FESR<<FO<=1/10~1/5Fs.  
The following is parameters for type II compensa-  
tor design. Input voltage is 12V, output voltage is 3.3V,  
output inductor is 1.5uH, output capacitors are two 680uF  
with 41mW electrolytic capacitors.  
1.Calculate the location of LC double pole FLC  
and ESR zero FESR  
.
Rev.5.0  
08/19/08  
14  
NX2305  
Output Voltage Calculation  
1
F
=
=
Output voltage is set by reference voltage and ex-  
ternal voltage divider. The reference voltage is fixed at  
0.8V. The divider consists of two ratioed resistors so  
that the output voltage applied at the Fb pin is 0.8V when  
the output voltage is at the desired value. The following  
equation and picture show the relationship between  
VOUT , VREF and voltage divider.  
LC  
2´ p ´  
L
OUT ´ COUT  
1
2´ p ´ 1.5uH´ 1360uF  
= 3.5kHz  
1
F
=
ESR  
2´ p ´ ESR´ COUT  
1
=
Vout  
2´ p ´ 20.5mW´ 1360uF  
= 5.7kHz  
R2  
Fb  
2.Set R2 equal to10.2kW. Using equation 21, the  
final selection of R1 is 3.24kW.  
R1  
3. Set crossover frequency at 1/10~ 1/5 of the  
swithing frequency, here FO=30kHz.  
Vref  
4.Calculate R3 value by the following equation.  
Figure 10 - Voltage divider  
VOSC 2 ´ p ´ FO ´ L  
R1+R2  
R1  
1
R3 =  
´
´
´
V
RESR  
gm  
in  
R 2 ´ VREF  
R1=  
1.1V 2´ p ´ 30kHz´ 1.5uH  
1
...(21)  
VOUT -VREF  
=
´
´
12  
20.5W  
10.2kW+3.24kW  
3.24kW  
2mA/V  
where R2 is part of the compensator, and the  
value of R1 value can be set by voltage divider.  
See compensator design for R1 and R2 selection.  
´
=2.6kW  
Choose R3 =2.61kW.  
Input Capacitor Selection  
5. Calculate C1 by setting compensator zero FZ  
at 75% of the LC double pole.  
Input capacitors are usually a mix of high frequency  
ceramic capacitors and bulk capacitors. Ceramic ca-  
pacitors bypass the high frequency noise, and bulk ca-  
pacitors supply current to the MOSFETs. Usually 1uF  
ceramic capacitor is chosen to decouple the high fre-  
quency noise.The bulk input capacitors are decided by  
voltage rating and RMS current rating. The RMS current  
1
C1=  
2´ p ´ R3 ´ F  
z
1
=
2´ p ´ 2.61kW´ 0.75´ 3.5kHz  
=23nF  
in the input capacitors can be calculated  
as:  
Choose C1=22nF.  
F
6. Calculate C2 by setting compensator pole  
at half the swithing frequency.  
p
IRMS = IOUT ´ D ´ 1-D  
VOUT  
1
D =  
C 2 =  
V
p ´ R 3 ´ Fs  
IN  
...(22)  
1
VIN = 12V, VOUT=1.8V, IOUT=10A, using equation  
(22), the result of input RMS current is 3.6A.  
For higher efficiency, low ESR capacitors are  
recommended.  
=
p ´ 2 . 61k W ´ 3 0 0 k H z  
= 4 0 6 p F  
Choose C1=390pF.  
Rev.5.0  
08/19/08  
15  
NX2305  
One Sanyo OS-CON 16SVP180M 16V 180uF  
where QHGATE is the high side MOSFETs gate  
20mW with 3.64A RMS rating are chosen as input bulk charge,QLGATE is the low side MOSFETs gate charge,VHGS  
capacitors.  
is the high side gate source voltage, and VLGS is the low  
side gate source voltage.  
This power dissipation should not exceed maxi-  
mum power dissipation of the driver device.  
Power MOSFETs Selection  
The NX2305 requires two N-Channel power  
MOSFETs. The selection of MOSFETs is based on  
maximum drain source voltage, gate source voltage,  
maximum current rating, MOSFET on resistance and  
power dissipation. The main consideration is the power  
Soft Start and Enable  
NX2305 has digital soft start for switching control-  
ler and has one enable pin for this start up. When the  
Power Ready (POR) signal is high and the voltage at  
enable pin is above VENTHH, the internal digital counter  
starts to operate and the voltage at positive input of Error  
amplifier starts to increase, the feedback network will  
force the output voltage follows the reference and starts  
the output slowly. After 2048 cycles, the soft start is  
complete and the output voltage is regulated to the de-  
sired voltage decided by the feedback resistor divider.  
loss contribution of MOSFETs to the overall converter  
efficiency. In this design example, two IRFR3709Z are  
used. They have the following parameters: VDS=30V,RDSON  
=6.5mW,QGATE =17nC.  
There are two factors causing the MOSFET power  
loss:conduction loss, switching loss.  
Conduction loss is simply defined as:  
P
HCON =IOUT2 ´ D´ RDS(ON) ´ K  
LCON=IOUT2 ´ (1- D)´ RDS(ON) ´ K  
PTOTAL =P + P  
P
...(23)  
HCON  
LCON  
Vbus  
where the RDS(ON) will increases as MOSFET junc-  
tion temperature increases, K is RDS(ON) temperature  
dependency. As a result, RDS(ON) should be selected for  
the worst case, in which K approximately equals to 1.4  
at 125oC according to IRFR3709Z datasheet. Conduc-  
tion loss should not exceed package rating or overall  
system thermal budget.  
POR  
ENSW or  
ENLDO  
R1  
R2  
Digital  
start  
up  
OFF  
10k  
ON  
ENTHH  
V
ENTHL  
V
Figure 11 - Enable and Shut down the NX2305  
with Enable pin.  
Switching loss is mainly caused by crossover  
conduction at the switching transition. The total  
switching loss can be approximated.  
The start up of NX2305 can be programmed through  
resistor divider at Enable pin. For example, if the input  
bus voltage is 12V and we want NX2305 starts when  
Vbus is above 8V. We can select  
1
PSW  
=
´ V ´ IOUT ´ TSW ´ F  
IN S  
...(24)  
2
where IOUT is output current, TSW is the sum of TR  
and TF which can be found in mosfet datasheet, and FS  
is switching frequency. Switching loss PSW is frequency  
dependent.  
(8V - VENTHH )´ R2  
R1 =  
VENTHH  
The NX2305 can be turned off by pulling down the  
Enable pin by extra signal MOSFET as shown in the  
above Figure. When Enable pin is below VENTHL, the digi-  
tal soft start is reset to zero. In addition, all the high side  
and low side driver is off and no negative spike will be  
generated during the turn off.  
Also MOSFET gate driver loss should be consid-  
ered when choosing the proper power MOSFET.  
MOSFET gate driver loss is the loss generated by dis-  
charging the gate capacitor and is dissipated in driver  
circuits.It is proportional to frequency and is defined as:  
Pgate = (QHGATE ´ VHGS + QLGATE ´ VLGS )´ FS  
...(25)  
Rev.5.0  
08/19/08  
16  
NX2305  
RRDSON = (VLDOIN - VLDOOUT )´ ILOAD  
= (3.3V - 2.5V) / 2A = 0.4W  
Over Current Protection  
Over current protection for NX2305 is achieved by  
sensing current through the low side MOSFET. An inter-  
nal current source of 40uA flows through an external re-  
sistor connected from OCP pin to SW node sets the  
over current protection threshold. When synchronous FET  
is on, the voltage at node SW is given as  
VSW =-IL ´ RDSON  
Most of MOSFETs can meet the requirement. More  
important is that MOSFET has to be selected right pack-  
age to handle the thermal capability. For LDO, maxi-  
mum power dissipation is given as  
PLOSS = (VLDOIN - VLDOOUT )´ ILOAD  
= (3.3V - 2.5V)´ 2A =1.6W  
The voltage at pin OCP is given as  
Select IR MOSFET IRFR3706 with 9mW RDSON is  
IOCP ´ ROCP +VSW  
sufficient.  
When the voltage is below zero, the over current  
occurss as shown in figure 12.  
LDO Compensation  
The diagram of LDO controller including VCC regu-  
vbus  
lator is shown in figure 13.  
I
OCP  
40uA  
LDO input  
OCP  
R
SW  
OCP  
Vref  
OCP  
comparator  
R
f1  
Figure 12 - Over current protection  
ESR  
Co  
R
f2  
Rload  
Rc  
Cc  
The over current limit can be set by the following  
equation  
ISET = IOCP ´ ROCP/RDSON  
Figure 13 - NX2305 LDO controller.  
If the MOSFET RDSON=9mW, and the current limit  
is set at 15A, then  
For most low frequency capacitor such as electro-  
lytic, POSCAP, OSCON, etc, the compensation param-  
eter can be calculated as follows.  
I
SET ´ RDSON 15A´ 9mW  
ROCP  
=
=
= 3.375kW  
IOCP  
40uA  
Choose ROCP=4kW  
gm ´ ESR  
1
CC =  
´
LDO Selection Guide  
4´ p ´ FO ´ Rf1 1+gm ´ ESR  
NX2305 offers a LDO controller. The selection of  
MOSFET to meet LDO is more straight forward. The  
selection is that the Rdson of MOSFET should meet  
the dropout requirement. For example.  
VLDOIN =3.3V  
where FO is the desired crossover frequency.  
Typically, in this LDO compensation, crossover  
frequency FO has to be higher than zero caused by ESR.  
FO is typically around several tens kHz to a few hundred  
kHz. For this example, we select Fo=100kHz. gm is the  
forward trans-conductance of MOSFET.  
For IRFR3706, gm=53.  
VLDOOUT =2.5V  
ILoad =2A  
The maximum Rdson of MOSFET should be  
Select Rf1=5kohm.  
Output capacitor is Sanyo POSCAP 4TPE150MI  
with 150uF, ESR=18mohm.  
Rev.5.0  
08/19/08  
17  
NX2305  
channel for 2048 cycles and start to restart system again.  
1
53 ´ 18mW  
CC =  
´
=77pF  
4 ´ p ´ 100kHz ´ 5kW 1+53 ´ 18mW  
Layout Considerations  
Choose CC=82pF. For electrolytic or POSCAP, RC  
is typically selected to be zero.  
The layout is very important when designing high  
frequency switching converters. Layout will affect noise  
pickup and can cause a good design to perform with  
less than expected results.  
Rf2 is determined by the desired output voltage.  
Rf1 ´ VREF  
Rf2 =  
There are two sets of components considered in  
the layout which are power components and small sig-  
nal components. Power components usually consist of  
input capacitors, high-side MOSFET, low-side MOSFET,  
inductor and output capacitors. A noisy environment is  
generated by the power components due to the switch-  
ing power. Small signal components are connected to  
sensitive pins or nodes. A multilayer layout which in-  
cludes power plane, ground plane and signal plane is  
recommended .  
VLDOOUT - VREF  
5kW´ 0.8V  
=
1.6V - 0.8V  
=5kW  
Choose Rf2=5kW.  
When ceramic capacitors or some low ESR bulk  
capacitors are chosen as LDO output capacitors, the  
zero caused by output capacitor ESR is so high that  
crossover frequency FO has to be chosen much higher  
than zero caused by RC and CC and much lower than  
zero caused by ESR . For example, 10uF ceramic is  
used as output capacitor. We select Fo=100kHz,  
Rf1=5kohm and select MOSFET MTD3055(gm=5). RC  
and CC can be calculated as follows.  
Layout guidelines:  
1. First put all the power components in the top  
layer connected by wide, copper filled areas. The input  
capacitor, inductor, output capacitor and the MOSFETs  
should be close to each other as possible. This helps  
to reduce the EMI radiated by the power loop due to the  
high switching currents through them.  
2´ p ´ FO ´ CO  
RC =Rf1 ´  
0.5´ gm  
2´ p ´ 100kHz´ 10uF  
2. Low ESR capacitor which can handle input RMS  
ripple current and a high frequency decoupling ceramic  
cap which usually is 1uF need to be practically touch-  
ing the drain pin of the upper MOSFET, a plane connec-  
tion is a must.  
=5kW´  
0.5´ 5S  
=12.56kW  
Choose RC=12.7kW.  
10´ CO  
CC =  
3. The output capacitors should be placed as close  
as to the load as possible and plane connection is re-  
quired.  
RC ´ gm  
10´ 10uF  
=
12.7kW´ 5S  
4. Drain of the low-side MOSFET and source of  
the high-side MOSFET need to be connected thru a plane  
ans as close as possible.A snubber nedds to be placed  
as close to this junction as possible.  
=1.6nF  
Choose CC=1.5nF.  
5. Source of the lower MOSFET needs to be con-  
nected to the GND plane with multiple vias. One is not  
enough. This is very important. The same applies to the  
output capacitors and input capacitors.  
Current Limit for LDO  
Current limit of LDO is achieved by sensing the  
LDO feedback voltage. When LDO_FB pin is below 0.4V,  
the IC goes into hiccup mode. The IC will turn off all the  
6. Hdrv and Ldrv pins should be as close to  
MOSFET gate as possible. The gate traces should be  
Rev.5.0  
08/19/08  
18  
NX2305  
wide and short.A place for gate drive resistors is needed  
to fine tune noise if needed.  
7. Vcc capacitor, BST capacitor or any other by-  
passing capacitor needs to be placed first around the IC  
and as close as possible. The capacitor on comp to  
GND or comp back to FB needs to be place as close to  
the pin as well as resistor divider.  
8. The output sense line which is sensing output  
back to the resistor divider should not go through high  
frequency signals.  
9. All GNDs need to go directly thru via to GND  
plane.  
10. The feedback part of the system should be  
kept away from the inductor and other noise sources,  
and be placed close to the IC.  
11. In multilayer PCB, separate power ground and  
analog ground. These two grounds must be connected  
together on the PC board layout at a single point. The  
goal is to localize the high current path to a separate  
loop that does not interfere with the more sensitive ana-  
log control function.  
10  
R14  
C11  
open  
C12  
1uF  
C1  
1uF  
VCC  
5V REG  
PVCC  
BST  
R6  
10k  
0
L1 1uH  
VOUT1  
+1.8V  
1N4148  
VIN1  
+12V  
PGOOD  
C3  
100uF  
LDO OUT  
C2  
180uF  
C9  
47uF  
M5  
C10  
150pF  
C4  
0.1uF  
M1  
IR3709  
R7  
VOUT2  
+1.2V/2A  
HDRV  
SW  
LDO FB  
ENLDO  
C8  
R8  
5k  
L2 2.2uH  
R9  
5k  
VOUT1  
150uF  
25mohm  
+1.8V/10A  
C7  
VOUT1  
+1.8V  
R10  
1500uF  
13mohm  
OCP  
LDRV  
PGND  
R11  
1.4k  
M2  
IR3711  
0.75k  
R1  
5k  
M3  
R2  
22.1k  
R3  
49.9k  
HI=SD  
C6  
820pF  
R12  
6.8k  
VIN1  
+12V  
FB  
ENSW  
C5  
R5  
40.2k  
R4  
40.2k  
R13  
1.4k  
COMP  
M4  
1.8nF  
AGND  
HI=SD  
C13 27pF  
Figure 14 - Typical application of NX2305 with single power supply  
Rev.5.0  
08/19/08  
19  
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