NX2142/2142A
25V 56uF 28mW with 3.8A RMS rating are chosen
where QHGATE is the high side MOSFETs gate
charge,QLGATE is the low side MOSFETs gate
charge,VHGS
as input bulk capacitors.
Power MOSFETs Selection
is the high side gate source voltage, and VLGS is the
The NX2142 requires two N-Channel power
MOSFETs. The selection of MOSFETs is based on
maximum drain source voltage, gate source voltage,
maximum current rating, MOSFET on resistance and
power dissipation. The main consideration is the power
low side gate source voltage.
This power dissipation should not exceed maxi-
mum power dissipation of the driver device.
Over Current Limit Protection
Over current Limit for step down converter is
achieved by sensing current through the low side
MOSFET. For NX2142, the current limit is decided by
the RDSON of the low side mosfet. When synchronous
FET is on, and the voltage on SW pin is below 320mV,
the over current occurs. The over current limit can be
calculated by the following equation.
loss contribution of MOSFETs to the overall converter
efficiency. In this design example, two STM6912 are
used. They have the following parameters: VDS=30V, ID
=6A,RDSON =57mW,QGATE =6.3nC.
There are two factors causing the MOSFET
power loss:conduction loss, switching loss.
Conduction loss is simply defined as:
HCON =IOUT2 ´ D´ RDS(ON) ´ K
LCON=IOUT2 ´ (1- D)´ RDS(ON) ´ K
PTOTAL =P + P
ISET = 320mV/RDSON
P
The MOSFET RDSON is calculated in the worst
case situation, then the current limit for MOSFET
STM6912 is
P
...(23)
HCON
LCON
320mV
320mV
where the RDS(ON) will increases as MOSFET junc-
tion temperature increases, K is RDS(ON) temperature
dependency. As a result, RDS(ON) should be selected
for the worst case, in which K approximately equals to
1.4 at 125oC according to datasheet. Conduction loss
should not exceed package rating or overall system
thermal budget.
ISET
=
=
= 4.6A
RDSON 1.2´ 57mW
Layout Considerations
The layout is very important when designing high
frequency switching converters. Layout will affect noise
pickup and can cause a good design to perform with
less than expected results.
Switching loss is mainly caused by crossover con-
duction at the switching transition. The total switching
loss can be approximated.
There are two sets of components considered in
the layout which are power components and small sig-
nal components. Power components usually consist of
input capacitors, high-side MOSFET, low-side
MOSFET, inductor and output capacitors. A noisy en-
vironment is generated by the power components due
to the switching power. Small signal components are
connected to sensitive pins or nodes. A multilayer lay-
out which includes power plane, ground plane and sig-
nal plane is recommended .
1
PSW
=
´ V ´ IOUT ´ TSW ´ F
IN S
...(24)
2
where IOUT is output current, TSW is the sum of TR
and TF which can be found in mosfet datasheet, and
FS is switching frequency. Swithing loss PSW is fre-
quency dependent.
Also MOSFET gate driver loss should be consid-
ered when choosing the proper power MOSFET.
MOSFET gate driver loss is the loss generated by dis-
charging the gate capacitor and is dissipated in driver
circuits.It is proportional to frequency and is defined
as:
Layout guidelines:
1. First put all the power components in the top
layer connected by wide, copper filled areas. The input
capacitor, inductor, output capacitor and the MOSFETs
should be close to each other as possible. This helps
Pgate = (QHGATE ´ VHGS + QLGATE ´ VLGS )´ FS
...(25)
Rev. 1.1
10/28/07
17
