NX2423
Over Voltage Protection
T
SW is the sum of TR and TF which can be found in
mosfet datasheet, IOUT is output current, and FS is switch-
ing frequency. Swithing loss PSW is frequency depen-
dent.
Over voltage protection is achieved by sensing the
output voltage through resistor divider. The sensed volt-
age on FB pin is compared with 130%*VREF to generate
the OVP signal.
Soft Start and Enable Signal Operation
The NX2423's master channel will start operation
after 5VCC and REFIN have reached their threshold
voltages. Pulling down VCCDRV will cause 5VCC drop
below to its threshold, then shuts down NX2423.
The slave channel will start operation only when
EN2_B is less than 0.8V, 5VCC and REFIN have reached
their respective thresholds. For two phase opeartion,
EN2_B is preferred to be tied to GND. For one phase
opeartion, EN2_B is preferred to be tied to 5VCC. Dur-
ing the operation, it is not recommended to change EN2_B
voltage.
Power MOSFETs Selection
The NX2423 requires two N-Channel power
MOSFETs for each channels. The selection of
MOSFETs is based on maximum drain source voltage,
gate source voltage, maximum current rating, MOSFET
on resistance and power dissipation. The main consid-
eration is the power loss contribution of MOSFETs to
the overall converter efficiency. In this design example,
eight NTD60N02 are used. They have the following pa-
rameters: VDS=25V, ID =62A,RDSON =12mW,QGATE =9nC.
There are three factors causing the MOSFET power
loss:conduction loss, switching loss and gate driver loss.
Gate driver loss is the loss generated by discharg-
ing the gate capacitor and is dissipated in driver circuits.
It is proportional to frequency and is defined as:
Once the converter starts, there is a soft start se-
quence of 1024 steps between 0 and VREF. The ramp
rate is determined by the switching frequency.
dVO
dt
VO
=
...(25)
1024´ TS
Pgate = (QHGATE ´ VHGS + QLGATE ´ VLGS )´ FS
...(22)
Layout Considerations
where QHGATE is the high side MOSFETs gate
charge,QLGATE is the low side MOSFETs gate charge,VHGS
is the high side gate source voltage, and VLGS is
the low side gate source voltage. This power dissipation
should not exceed maximum power dissipation of the
driver device.
The layout is very important when designing high
frequency switching converters. Layout will affect noise
pickup and can cause a good design to perform with
less than expected results.
There are two sets of components considered in
the layout which are power components and small sig-
nal components. Power components usually consist of
input capacitors, high-side MOSFET, low-side MOSFET,
inductor and output capacitors. A noisy environment is
generated by the power components due to the switch-
ing power. Small signal components are connected to
sensitive pins or nodes. A multilayer layout which in-
cludes power plane, ground plane and signal plane is
recommended .
Conduction loss is simply defined as:
P
HCON =IOUT2 ´ D´ RDS(ON) ´ K
LCON=IOUT2 ´ (1- D)´ RDS(ON) ´ K
PTOTAL =P + P
P
...(23)
HCON
LCON
Where the RDS(ON) will increases as MOSFET jun-
ction temperature increases, K is RDS(ON) temperature
dependency and should be selected for the worst case.
Conduction loss should not exceed package rating or
overall system thermal budget.
Layout guidelines:
1. First put all the power components in the top
layer connected by wide, copper filled areas. The input
capacitor, inductor, output capacitor and the MOSFETs
should be close to each other as possible. This helps to
reduce the EMI radiated by the power loop due to the
Switching loss is mainly caused by crossover con-
duction at the switching transition. The total switching
loss can be approximated.
1
PSW
=
´ V ´ IOUT ´ TSW ´ F
IN S
...(24)
2
Rev. 2.1
12/01/08
17
