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NX25F011B-5V

型号：

NX25F011B-5V

描述：

1M位， 2M位和4M位串行闪存采用4引脚SPI接口[ 1M-BIT, 2M-BIT, AND 4M-BIT SERIAL FLASH MEMORIES WITH 4-PIN SPI INTERFACE ]

品牌：

ETC[ ETC ]

页数：

37 页

PDF大小：

545 K

下载PDF手册
PRELIMINARY  
DECEMBER2001  
NX25F011B, NX25F021B, NX25F041B  
1M-BIT, 2M-BIT, AND 4M-BIT  
SERIAL FLASH MEMORIESWITH 4-PIN SPI INTERFACE  
ThisdocumentcontainsPRELIMINARYINFORMATION.NexFlashreservestherighttomakechangestoitsproductatanytimewithoutnoticeinordertoimprovedesignandsupplythebestpossible  
product.Weassumenoresponsibilityforanyerrorswhichmayappearinthispublication.Copyright2001,NexFlashTechnologies,Inc.  
NexFlashTechnologies, Inc.  
1
PRELIMINARYNXSF016F-1201  
12/12/01 ©  
NX25F011B  
NX25F021B  
NX25F041B  
Table of Contents  
1M-BIT, 2M-BIT, AND 4M-BIT .........................................................................................................................................1  
SERIAL FLASH MEMORIESWITH 4-PIN SPI INTERFACE .......................................................................................... 1  
FEATURES..................................................................................................................................................................... 4  
DESCRIPTION ............................................................................................................................................................... 4  
FUNCTIONAL OVERVIEW ............................................................................................................................................. 5  
Pin Descriptions ....................................................................................................................................................... 5  
Package ............................................................................................................................................................... 5  
Serial Data Input (SI) ............................................................................................................................................6  
Serial Data Output (SO) ....................................................................................................................................... 6  
Serial Clock (SCK) ...............................................................................................................................................6  
Chip Select (CS) ..................................................................................................................................................6  
Write Protect (WP) ...............................................................................................................................................6  
Hold or Ready/Busy (HOLD or R/B) ...................................................................................................................... 6  
Power Supply Pins (Vcc and Gnd)........................................................................................................................ 6  
Serial Flash Memory Array ....................................................................................................................................... 7  
Serial SRAM............................................................................................................................................................. 8  
Using the SRAM Independent of Flash Memory ................................................................................................... 9  
Write Protection ........................................................................................................................................................9  
Configuration Register .............................................................................................................................................. 9  
Write Protect Range and Direction, WR[3:0], WD ................................................................................................ 10  
Read Clock Edge, RCE ...................................................................................................................................... 10  
Table 2A.Write Protect Range Sector Selection (Hex) ........................................................................................ 11  
Table 2B.Write Protect Range Sector Selection (Hex) ........................................................................................ 11  
Table 2C.Write Protect Range Sector Selection (Hex) ........................................................................................ 11  
HOLD-R/B, HR[1:0] ............................................................................................................................................ 11  
Status Register Bit Descriptions ............................................................................................................................. 12  
Compare Not Equal, CNE ................................................................................................................................... 12  
Power Detect, PD ............................................................................................................................................... 12  
Write Enable/Disable, WE................................................................................................................................... 12  
Command Set ........................................................................................................................................................ 13  
Command Set for the NX25F011B, NX25F021B and NX25F041B Serial Flash Memory ..................................... 15  
SERIAL FLASH SECTOR COMMANDS ....................................................................................................................... 16  
Read From Sector (52H) ......................................................................................................................................... 16  
Read From Sector with Auto Increment (50H) ......................................................................................................... 16  
Read From Sector Low Frequency (51H) and .......................................................................................................... 16  
Read From Sector Low Frequency with Auto Increment (5BH) ................................................................................ 16  
Write Enable (06H).................................................................................................................................................. 16  
Write Disable (04H)................................................................................................................................................. 16  
Write to SectorThrough SRAM (F3H) ..................................................................................................................... 18  
SERIAL SRAM COMMANDS ....................................................................................................................................... 19  
Write to SRAM Command (72H) ............................................................................................................................. 19  
Read from SRAM (71H) .......................................................................................................................................... 19  
Transfer All of SRAM to Sector (F3H) ..................................................................................................................... 20  
Transfer All of Sector to SRAM (53H) ..................................................................................................................... 20  
Compare Sector to SRAM (8DH) ............................................................................................................................ 21  
CONFIGURATION AND STATUS COMMANDS ............................................................................................................ 21  
Read Configuration Register (8CH) ......................................................................................................................... 21  
Write Non-Volatile Configuration  
Register (8AH) ........................................................................................................................................................ 22  
2
NexFlashTechnologies, Inc.  
PRELIMINARYNXSF016F-1201  
12/12/01 ©  
NX25F011B  
NX25F021B  
NX25F041B  
Table of Contents (cont’d)  
Read Status Register (84H) .................................................................................................................................... 22  
Clear Compare Status (89H) ................................................................................................................................... 23  
Set Power Detection Bit (03H) ................................................................................................................................ 23  
Reset Power Detection Bit (09H)............................................................................................................................. 23  
Read Device Information Sector (15H) .................................................................................................................... 24  
1
SPECIAL SECTOR COMMANDS ................................................................................................................................. 24  
Erase Sector (F1H)................................................................................................................................................. 24  
Erase Block (F4H) .................................................................................................................................................. 25  
Write-only to Sector (F2H) ...................................................................................................................................... 25  
2
COMPATIBILITY COMMANDS FOR 25xxxA SERIES DEVICES................................................................................. 26  
Read from SRAM (81H) .......................................................................................................................................... 26  
Read Configuration Register (8BH) ......................................................................................................................... 27  
Read Status Register (83H) .................................................................................................................................... 27  
Transfer Sector to SRAM Clocked (54H) ................................................................................................................. 28  
Compare Sector to SRAM Clocked (86H) ............................................................................................................... 28  
Sector Format ........................................................................................................................................................ 29  
High Data Integrity Applications.............................................................................................................................. 29  
Write/Verify Flow .................................................................................................................................................... 29  
Grouping Static and Frequently  
3
4
5
Updated Data.......................................................................................................................................................... 29  
ABOSOLUTE MINIMUM RATINGS .............................................................................................................................. 30  
OPERATING RANGES ................................................................................................................................................. 30  
DC ELECTRICAL CHARACTERISTICS (Preliminary) ................................................................................................. 30  
AC ELECTRICAL CHARACTERISTICS (Preliminary) ................................................................................................. 31  
SERIAL OUTPUTTIMING ............................................................................................................................................ 32  
SERIAL INPUTTIMING................................................................................................................................................ 32  
HOLDTIMING .............................................................................................................................................................. 32  
6
7
8
PACKAGING INFORMATION ........................................................................................................................................ 33  
200-mil Plastic SOIC Package Code:(S) ............................................................................................................ 33  
PACKAGING INFORMATION ........................................................................................................................................ 34  
330 mil Plastic SOIC Package Code: (J) ............................................................................................................ 34  
9
PACKAGING INFORMATION ........................................................................................................................................ 35  
Plastic TSOP - 28-pins Package Code:Type I (V)............................................................................................... 35  
PRELIMINARY DESIGNATION .................................................................................................................................... 36  
IMPORTANT NOTICE ................................................................................................................................................... 36  
ORDERING INFORMATION ......................................................................................................................................... 36  
LIFE SUPPORT POLICY ............................................................................................................................................. 36  
Trademarks: ................................................................................................................................................................. 36  
10  
11  
12  
NexFlashTechnologies, Inc.  
3
PRELIMINARYNXSF016F-1201  
12/12/01 ©  
NX25F011B  
NX25F021B  
NX25F041B  
FEATURES  
DESCRIPTION  
• Flash Storage for Resource-Limited Systems  
– Idealforportable/mobileandmicrocontroller-based  
applications that store voice, text, and data  
The NX25F011B, NX25F021B, and NX25F041B Serial  
Flash memories provide a storage solution for systems  
limited in power, pins, space, hardware, and firmware  
resources. They are ideal for applications that store voice,  
text, and data in a portable or mobile environment. Using  
NexFlash's patented single transistor EEPROM cell, the  
devices offer a high-density, low-voltage, low-power, and  
cost-effective non-volatile memory solution. The devices  
operate on a single 5V or 3V (2.7V-3.6V) supply for Read  
andErase/Writewithtypicalcurrentconsumptionaslowas  
2.5 mA active and less than 1 µA standby. Sector  
erase/write speeds as fast as 7.5 ms increase system  
performance, minimize power-on time, and maximize  
battery life.  
• 0.35µ NexFlashMemory Technology  
– 1M/2M/4M-bit with 512/1024/2048 sectors  
– Small 264-byte sectors  
– Erase/Write time of 7.5 ms/sector (typical)  
– Optional 8KB (32 sector) block erase for faster  
programming  
• Ultra-low Power for Battery-Operation  
– Single 5V or 3V supply for read and erase/write  
– 1 mA standby current, 2.5 mA active @ 3V (typical)  
– Lowfrequencyreadcommandforlowerpower  
TheNX25F011B, NX25F021B, andNX25F041Bprovide  
1M-bit,2M-bit,and4M-bitofflashmemoryorganizedas512,  
1024, or 2048 sectors of 264 bytes each. Each sector is  
individually addressable through basic serial-clocked com-  
mands. The 4-pin SPI serial interface works directly with  
popular microcontrollers. Special features include: on-chip  
serial SRAM, byte-level addressing, double-buffered sector  
writes, transfer/compare sector to SRAM, hardware and  
softwarewriteprotection,alternateoscillatorfrequency,elec-  
tronic part number, and removable Serial Flash Module  
package option. Development is supported with the  
PC-based SFK-SPI Serial Flash Development Kit.  
• 4-pin SPI Serial Interface  
– Easily interfaces to popular microcontrollers  
– Clock operation as fast as 20 MHz  
• On-chip Serial SRAM  
– Single 264-byte Read/Write SRAM buffer  
– Use in conjunction with or independent of Flash  
– Off-loadsRAM-limitedmicrocontrollers  
• Special Features for Media-Storage Applications  
– Byte-level addressing for reads and SRAM writes  
– Transfer or compare sector to SRAM  
– Versatilehardwareandsoftwarewrite-protection  
– In-system electronic part number option  
– Removable Serial Flash Module package option  
– Serial Flash Development Kit  
4
NexFlashTechnologies, Inc.  
PRELIMINARYNXSF016F-1201  
12/12/01 ©  
NX25F011B  
NX25F021B  
NX25F041B  
FUNCTIONAL OVERVIEW  
Pin Descriptions  
Package  
An architectural block diagram of the NX25F011B,  
NX25F021B, and NX25F041B is shown in Figure 2. Key  
elements of the architecture include:  
The NX25F011B, NX25F021B, and NX25F041B are  
availableina28-pinTSOP(TypeI) surfacemountpackage.  
TheNX25F011BandNX25F021Bareavailableineitheran  
8-pinSOICanda14-pinTSOPpackage(contactNexFlash  
for information on the 14-pin TSOP package). The  
NX25F041B is also available in a 28-pin SOIC package.  
See Figure 3A, 3B and Table 1 for pin assignments. All  
interface and supply pins are on one side of the TSOP  
package.The“NoConnect”(NC)pinsarenotconnectedto  
the device, allowing the pads and the area around them to  
be used for routing PCB system traces. The devices are  
also available in a cost-effective and space-efficient  
removable Serial Flash Module package.  
1
•
•
•
•
•
•
SPI Interface and Command Set Logic  
Serial Flash Memory Array  
2
Serial SRAM and Program Buffer  
Write Protection Logic  
3
ConfigurationandStatusRegisters  
Device Information Sector  
4
DEVICE INFORMATION SECTOR (DIS)  
(READ ONLY)  
5
NexFlash  
6
1, 2 AND 4 M-BIT  
SERIAL FLASH MEMORY ARRAY  
WRITE CONTROL  
LOGIC  
WP  
512, 1024 AND 2048  
BYTE-ADDRESSABLE  
16  
7
SECTORS OF 264 BYTES EACH  
ORGANIZED IN 16, 32, AND 64  
BLOCKS OF 32 SECTORS PER BLOCK  
HOLD OR  
READ/BUSY  
LOGIC  
HOLD  
OR R/B  
8
CONFIGURATION  
REGISTER  
2112  
STATUS  
REGISTER  
9
SRAM (264 BYTES)  
HIGH-VOLTAGE  
GENERATORS  
10  
11  
12  
SECTOR-ADDRESS  
LATCH  
8
8
SCK  
CS  
SI  
8
SPI  
COMMAND  
AND  
CONTROL  
LOGIC  
COLUMN DECODE, SENSE AMP LATCH  
AND DATA COMPARE LOGIC  
DATA  
SO  
BYTE-ADDRESS  
LATCH/COUNTER  
9
Figure2.NX25F011B,NX25F021B,andNX25F041BArchitecturalBlockDiagram  
NexFlashTechnologies, Inc.  
5
PRELIMINARYNXSF016F-1201  
12/12/01 ©  
NX25F011B  
NX25F021B  
NX25F041B  
Serial Data Input (SI)  
TheSPIbusSerialDataInput(SI)providesameansfordata  
to be written to (shifted into) the device.  
the SO pin will enter a high-impedance state and power  
consumption will decrease to standby levels unless pro-  
gramming is in process, in which case standby will resume  
whenprogrammingiscomplete.  
Serial Data Output (SO)  
TheSPIbusSerialDataOutput(SO)providesameansfor  
datatobereadfrom(shiftedoutof)thedeviceduringaread  
operation.Whenthedeviceisdeselected(CS=1orHOLD=0)  
the SO pin is in a high-impedance state.  
WriteProtect(WP)  
The Write Protect input (WP) works in conjunction with the  
write protect range set in the configuration register bits.  
WhenWPisasserted(activelow)theentireFlashmemory  
array is write protected. When high, any Flash memory  
sectorcanbewrittentounlessitsaddressiswithinthewrite  
protect range that is set in the configuration register.  
SerialClock(SCK)  
All commands and data written to the Serial Input (SI) are  
clockedrelativetotherisingedgeoftheSerialClock(SCK).  
All data read from the Serial Data Output (SO) is clocked  
relative to the falling or rising edge of SCK as specified in  
the non-volatile configuration register. The data output  
clock edge is factory-programmed to the default condition  
ofthefallingedge,allowingcompatibilitywithstandardSPI  
systems. Clock rates of up to 20 MHz are supported.  
Hold or Ready/Busy (HOLD or R/B)  
This multifunction pin can serve either as a Hold input  
(HOLD) or as a Ready-Busy output (R/B). The pin function  
isuser-programmablethroughthenon-volatileconfiguration  
register.Factory-programmedasano-connect,thepincan  
be reconfigured as a Ready-Busy output or as a Hold input  
by setting the configuration register. See the configuration  
register section of this data sheet for further details.  
Chip Select (CS)  
The NX25F011B, NX25F021B, and NX25F041B are  
selected for operation when the Chip Select input (CS) is  
asserted low. SCK must be low when (CS) is asserted to a  
lowstate.Uponpower-up,aninitiallow-to-hightransitionof  
CS is required before any command sequence will be  
acknowledged. The device can be deselected to a  
non-activestatewhenCSisbroughthigh.Oncedeselected,  
Power Supply Pins (Vcc and GND)  
The NX25F011B, NX25F021B, and NX25F041B support  
singlepowersupplyReadandErase/Writeoperationsin5V  
and 3V versions. Typical active power is as low as 2.5 mA  
for the 3V version with standby current less than 1 µA.  
1
2
3
4
5
6
7
8
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
GND  
NC  
NC  
CS  
SCK  
SI  
SO  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
VCC  
NC  
NC  
WP  
NC  
HOLD-R/B  
NC  
NC  
NC  
NC  
NC  
1
2
3
4
8
7
6
5
SI  
SCK  
SO  
GND  
VCC  
WP  
Hold R/B  
CS  
9
10  
11  
12  
13  
14  
Figure3A.NX25F011BandNX25F021B  
Pin Assignments, 8-Pin SOIC  
NC  
NC  
NC  
Figure3C.NX25F041B  
Pin Assignments, 28-Pin SOIC  
1
2
3
4
5
6
7
8
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
HOLD-R/B  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
WP  
NC  
NC  
VCC  
GND  
NC  
NC  
NC  
Table 1. Pin Descriptions  
SI  
SO  
SCK  
CS  
Serial Data Input  
9
Serial Data Output  
Serial Clock Input  
Chip Select Input  
10  
11  
12  
13  
14  
CS  
SCK  
SI  
SO  
WP  
Write Protect Input  
Hold Input or Read Busy Output  
PowerSupply  
Hold, R/B  
Vcc  
Figure3B.NX25F011B,NX25F021B,andNX25F041B  
Pin Assignments, 28-Pin TSOP (Type I)  
6
NexFlashTechnologies, Inc.  
PRELIMINARYNXSF016F-1201  
12/12/01 ©  
NX25F011B  
NX25F021B  
NX25F041B  
Serial Flash Memory Array  
mand. No pre-erase is needed. Instead, the device  
incorporates an auto-erase-before-write feature that  
automaticallyerasestheaddressedsectoratthebeginning  
of the write operation. After a sector has been written, the  
memoryarraywillbecomebusywhileitisprogrammingthe  
specified non-volatile memory cells of that sector. This  
busy time will not exceed tWP during which time the Flash  
array is unavailable for read or write access. The device  
can be tested to determine the array’s availability using  
the Ready/Busy status that is available during most read  
commands, through the status register, or on the  
Ready/Busy pin.  
The NX25F011B, NX25F021B, and NX25F041B Serial  
Flashmemoryarraysareorganizedas512,1024,and2048  
sectors of 264-bytes (2,112 bits) each, as shown in  
Figure4.Theblocksizeofthedeviceis32sectors,yielding  
16,32and64blocksfortheNX25F011B,NX25F021B,and  
NX25F041B.  
1
2
TheSerialFlashmemoryoftheNX25F011B,NX25F021B,  
and NX25F041B is byte-addressable for read operations.  
This allows a single byte, or specified sequence of bytes,  
tobereadwithouthavingtoclockanentire264-bytesector  
out of the device. Data can be read directly from a sector  
in the Flash memory array by using a Read from Sector  
command.  
3
After sector programming is complete and the device is  
ready, it is recommended to verify the data in the sector  
with the data in the SRAM using the compare command,  
(see Write/ Verify Flow towards the end of this data sheet).  
4
Data can be written to the Flash memory array one sector  
(264-bytes)atatimethroughtheSerialSRAMusingaWrite  
to Sector command or a Transfer SRAM to Sector com-  
5
6
Sector Address:  
25F041  
25F011  
25F021  
S[10:0]  
S[8:0]  
S[9:0]  
Byte Address: B[8:0]  
7
Block 16  
Sector 511  
1FFH  
Block 32  
Sector 1023  
3FFH  
Block 64  
Sector 2047  
7FFH  
Byte 0  
000H  
Byte1  
001H  
Byte 263  
107H  
Byte 262  
106H  
Byte 2-261  
002H-105H  
8
Byte 0  
000H  
Byte 263  
107H  
Byte1  
001H  
Byte 262  
106H  
Sector 480  
1E0H  
Sector 992  
3E0H  
Sector 2016  
7E0H  
Byte 2-261  
002H-105H  
1M-bit, 2M-bit, or 4M-bit Serial Flash Memory Array  
512, 1024, and 2048 Byte-Addressable Sectors  
of 264-Bytes each.  
9
Organized in 16, 32 and 64  
blocks of 32 sectors per block.  
10  
11  
12  
Block 0  
Sector 31  
1FH  
Block 0  
Sector 31  
1FH  
Block 0  
Sector 31  
1FH  
Byte 0  
000H  
Byte 2-261  
002H-105H  
Byte 262 Byte 263  
106H 107H  
Byte 1  
001H  
Byte 0  
000H  
Byte 1  
001H  
Byte 2-261  
002H-105H  
Byte 262 Byte 263  
106H  
107H  
Sector 0  
000H  
Sector 0  
000H  
Sector 0  
000H  
Figure 4. NX25F011B, NX25F021B, and NX25F041B Serial Flash Memory Array  
NexFlashTechnologies, Inc.  
7
PRELIMINARYNXSF016F-1201  
12/12/01 ©  
NX25F011B  
NX25F021B  
NX25F041B  
Serial SRAM  
One of the most powerful features of the NX25F011B,  
NX25F021B, and NX25F041B is the integrated Serial  
SRAM. The main purpose of the Serial SRAM is to serve  
as the primary buffer for sector data to be written into the  
Serial Flash memory array. Using the Write to Sector  
command, data is first shifted into the SRAM from the SPI  
bus.Whenthecommandsequencehasbeencompleted,the  
entire 264-bytes is written to the selected sector. See  
Erase/Write cycle timing (tWP).  
theSRAM.Thiscanbeusefulwhenonlyaportionofasector  
needstobealtered.Inthiscasethesectorisfirsttransferred  
totheSRAM,wheremodificationsaremadeusingtheWrite  
to SRAM command. Once complete, a Transfer SRAM to  
Sector command is used to update the sector.  
The Compare Sector command allows the contents of the  
SRAMtobecomparedwiththespecifiedsectorinmemory.  
The result of the compare is set in the status register. This  
command is useful for performing a fast verify of the last  
sector write operation (see Write/ Verify Flow towards the  
end of this data sheet). This command can be useful when  
re-writing multi-sector files that have only minor changes  
from the previous write. If the new data in the SRAM is the  
same as the previously written data, the sector write can  
be skipped. Used in this way, the command saves time  
that would have been used for re-programming. It also  
extends the endurance of the Flash memory cells.  
The SRAM is fully byte-addressable. Thus, the entire  
264-bytes,asinglebyte,orasequenceofbytescanberead  
from, or written to the SRAM. This allows the SRAM to be  
used as a temporary work area for read-modify-write  
operations prior to a sector write.  
The Transfer Sector to SRAM command allows the con-  
tents of a specified sector of Flash memory to be moved to  
DEVICE INFORMATION SECTOR  
READ FROM  
DEVICE INFORMATION  
SECTOR  
READ FROM  
SECTOR  
SERIAL FLASH MEMORY ARRAY  
512, 1024 AND 2048 BYTE-ADDRESSABLE  
SECTORS OF 264-BYTES EACH  
CONFIGURATION  
REGISTER  
TRANSFER  
SECTOR TO  
SRAM  
STATUS  
REGISTER  
SPI  
COMMAND  
SCK  
AND  
CONTROL  
CS  
SI  
LOGIC  
SO  
COMPARE SECTOR  
TO SRAM  
READ FROM  
OR WRITE TO  
SRAM  
WRITE TO SECTOR  
(VIA SRAM)  
SERIAL SRAM  
Note:  
1. A single byte, several bytes, or all bytes of a Flash sector, the SRAM, or Program Buffer may be addressed.  
2. All double lines represent implied connections or actions.  
Figure 5. Command Relationships of the SPI Interface, Serial Flash Memory Array and SRAM  
8
NexFlashTechnologies, Inc.  
PRELIMINARYNXSF016F-1201  
12/12/01 ©  
NX25F011B  
NX25F021B  
NX25F041B  
Using the SRAM Independent of Flash Memory  
The SRAM can be used independently of Flash memory  
operations for lookup tables, variable storage, or scratch  
pad purposes. If the Flash memory needs to be written to  
while SRAM is being used for a different purpose, the  
contents can be temporarily stored to a sector and then  
transferred back again when needed. The SRAM can be  
especially useful for RAM-limited microcontroller-based  
systems, eliminating the need for external SRAM and  
freeingpinsforotherpurposes. Itcanalsomakeitpossible  
to use small pin-count microcontrollers, since only a few  
pins are needed for the interface instead of the 20-40 pins  
requiredforparallelbus-orientedFlashdevices.  
1
System Power-up  
2
Read Device Information Sector,  
Verify Device Density and Type  
3
Read Configuration Register  
Verify bits are Set as Needed  
Write Protection  
4
TheNX25F011B,NX25F021B,andNX25F041Bprovidead-  
vanced software and hardware write protection  
features. Software-controlled write protection of the entire  
array is handled using the Write Enable and Write Disable  
commands. Hardware write protection is possible using the  
Write Protect pin (WP). Write-protecting a portion of Flash  
memory is accommodated by programming a write protect  
range in the configuration register. For applications  
needing a portion of the memory to be permanently  
write-protected or a fixed configuration register value, a  
onetimeprogrammablewriteprotectionfeatureissupported.  
Contact NexFlash for further information.  
Configuration  
Setting is Correct?  
Yes  
5
No  
Write Configuration Register  
to Correct Setting  
6
7
Configuration Register  
TheConfigurationRegisterstoresthecurrentconfiguration  
of the HOLD-R/B pin, read clock edge and write protect  
range (Figure 7). The configuration register is accessed  
using the Write and Read Configuration Register  
commands. The non-volatile configuration register will  
maintain its setting even when power is removed.  
Application Routines  
8
Figure 6. Flow Chart for Checking the Configuration  
RegisteruponPower-up  
9
To avoid unnecessary programming of the configuration  
register,andtosavetimeduringpower-up,theconfiguration  
registershouldbereaduponpower-upandcomparedtothe  
intended setting before sending a Write Configuration  
Registercommand(Figure6).  
10  
11  
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PRELIMINARYNXSF016F-1201  
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NX25F011B  
NX25F021B  
NX25F041B  
The factory default setting for the configuration register is  
CF8-CF0is:000001001B(writeprotectrange=none,read  
usesfallingedgeoftheclock, andpin1=noconnect).Bits  
CF15-CF9 arereserved. Whenwritingtotheconfiguration  
registerCF15-CF9shouldbe0.Whenreading,thesettings  
ofCF15-CF9shouldbeignored.  
Once protected, all further writes to sectors within the  
rangewillbeignored. Thefactorydefaultsettingiswithno  
write protected sectors, WR=[0,0,0,0] and WD=1.  
Read Clock Edge, RCE  
TheReadClockEdgebit(RCE)islocatedatconfiguration  
bitlocationCF[2]. Itselectswhichedgeoftheclock(SCK)  
is used while reading data out of the device. Although the  
SPI protocol specifies that data is written during the rising  
edge and read on the falling edge of the clock, if required,  
the output can be driven on the rising edge of the clock by  
settingtheconfigurationregistersRCEbittoa1.Usingthe  
risingedgeofclockfordatareadsmaybebeneficialtothe  
timing of some high-speed systems. The factory default  
setting is the falling edge of SCK for standard SPI.  
WriteProtectRangeandDirection, WR[3:0], WD  
ThewriteprotectrangeanddirectionbitsWR[3:0]andWD  
arelocatedatconfigurationbitsCF[7:4]andCF[3]respec-  
tively.Thewriteprotectrangeanddirectionbitsselecthow  
the array is protected. They work in conjunction with the  
WP input pin, valid only if WP is inactive (high). WR[3:0]  
can select write protection of all sectors, none of the  
sectors, or specific sectors grouped in blocks of 32  
(~8KB). TheWDbitspecifieswhethertheprotectedblock  
rangestartsfromthefirstsector,address0(000H),orfrom  
the last sector (1FFH for the NX25F011B, 3FFH for the  
NX25F021B, and 7FF for the NX25F041B). Table 2A, 2B  
and 2C lists the write protect sector range for the devices.  
RCE=0 Read data is output on the falling edge of SCK  
(StandardSPI).  
RCE=1 Read data is output on the rising edge of SCK  
(Fast SPI).  
CF15:8  
CF7  
CF6  
CF5  
CF4  
CF3  
CF2  
CF1 CF0  
(RESERVED)  
WR3 WR2 WR1 WR0 WD  
RCE  
HR1  
HR0  
WRITE PROTECT  
RANGE  
WRITE PROTECT  
DIRECTION  
READ DATA  
CLOCK EDGE  
HOLD-READY/BUSY  
PIN FUNCTION  
Figure 7. Configuration Register Bit Locations  
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NX25F021B  
NX25F041B  
Table 2A. Write Protect Range Sector Selection (Hex)  
Table 2C. Write Protect Range Sector Selection (Hex)  
Write Protect  
(NX25F011B)  
Write Protect  
(NX25F041B)  
Range Config. Bits  
Write Protected Sectors  
Range Config. Bits  
Write Protected Sectors  
1
WR3 WR2 WR1 WR0  
WD=0  
WD=1  
WR3 WR2 WR1 WR0  
WD=0  
WD=1  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
None  
None  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
None  
None  
000 - 01FH  
000 - 03FH  
000 - 05FH  
000 - 07FH  
000 - 09FH  
000 - 0BFH  
000 - 0DFH  
000 - 0FFH  
000 - 11FH  
000 - 13FH  
000 - 15FH  
000 - 17FH  
000 - 19FH  
000 - 1BFH  
ALL  
1 E0 - 1FF  
1 C0 - 1FF  
1 A0 - 1FF  
1 80 - 1FF  
1 60 - 1FF  
1 40 - 1FF  
1 20 - 1FF  
1 00 - 1FF  
0 E0 - 1FF  
0 C0 - 1FF  
0 A0 - 1FF  
0 80 - 1FF  
0 60 - 1FF  
0 40 - 1FF  
ALL  
000 - 01FH  
000 - 03FH  
000 - 05FH  
000 - 07FH  
000 - 09FH  
000 - 0BFH  
000 - 0DFH  
000 - 0FFH  
000 - 11FH  
000 - 13FH  
000 - 15FH  
000 - 17FH  
000 - 19FH  
000 - 1BFH  
ALL  
7 E0 - 7FFH  
7 C0 - 7FFH  
7 A0 - 7FFH  
7 80 - 7FFH  
7 60 - 7FFH  
7 40 - 7FFH  
7 20 - 7FFH  
7 00 - 7FFH  
6 E0 - 7FFH  
6 C0 - 7FFH  
6 A0 - 7FFH  
6 80 - 7FFH  
6 60 - 7FFH  
6 40 - 7FFH  
ALL  
2
3
4
5
6
HOLD-R/B,HR[1:0]  
Table 2B. Write Protect Range Sector Selection (Hex)  
7
The Hold-Ready/Busy (HOLD-R/B) bits HR1 and HR0 are  
located at bits CF[1:0] of the configuration register. These  
two bits select one of four possible functions: No Connect,  
HOLDinput,R/BOutput,orR/BOutputwithopendrain.The  
factory setting for the pin is “No Connect”.  
Write Protect  
(NX25F021B)  
Range Config. Bits  
Write Protected Sectors  
WR3 WR2 WR1 WR0  
WD=0  
WD=1  
8
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
None  
None  
000 - 01FH  
000 - 03FH  
000 - 05FH  
000 - 07FH  
000 - 09FH  
000 - 0BFH  
000 - 0DFH  
000 - 0FFH  
000 - 11FH  
000 - 13FH  
000 - 15FH  
000 - 17FH  
000 - 19FH  
000 - 1BFH  
ALL  
3 E0 - 3FF  
3 C0 - 3FF  
3 A0 - 3FF  
3 80 - 3FF  
3 60 - 3FF  
3 40 - 3FF  
3 20 - 3FF  
3 00 - 3FF  
2 E0 - 3FF  
2 C0 - 3FF  
2 A0 - 3FF  
2 80 - 3FF  
2 60 - 3FF  
2 40 - 3FF  
ALL  
HR1  
HR0  
PinConfiguration  
0
0
1
1
0
1
0
1
HOLDinput  
NoConnect  
R/BOutput(OpenDrain)  
R/B Output  
9
10  
11  
12  
ConfiguredasaR/B output, thepincanserveasasystem  
interrupt. When R/B is high, the array is ready to be  
programmed. When R/B is low, it is busy programming. If  
configuredwithanopen-drain,anexternalpull-upresistor  
should be used.  
As a HOLD input, the pin can be used in conjunction with  
the CS and SCK pin to suspend a serial command  
sequence without resetting the command. This can be  
useful if a command is in process and a higher priority  
task on the same SPI bus needs to be attended to. To  
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NX25F041B  
suspend a command, HOLD must be brought low while  
CS and SCK are low. With HOLDlow, further data on the  
SI pin is ignored (even while SCK is clocked) and the SO  
pin goes to a high-impedance state. To resume the  
command sequence, HOLD must be brought high when  
CS and SCK are low. See timing diagrams.  
SRAM Transfer All or Compare All, TR  
The TR status bit is located at bit ST[6] of the status  
register. The bit provides status primarily for use during  
the Transfer AllSectortoSRAM command and Compare  
All Sector to SRAM command. An active state 1 indi-  
cates a transfer is in process and the SRAM Array is not  
available for use. The device will indicate a BUSY state  
whiletheTRbitisactive. UponpoweruptheTRbitresets  
to 0.  
Status Register Bit Descriptions  
The status register provides status of the Flash array’s  
Ready/Busycondition(R/B),transfersbetweentheSRAM  
andprogrambuffer(TX),Write-Enable/Disable(WE),and  
CompareNotEqual(CNE).Theregistercanbereadusing  
the Read Status Register command (Figure 8).  
TR=1 Transfer or Compare All in Process.  
TR=0 Transfer or Compare All not in Process.  
Write Enable/Disable, WE  
The WE status bit is located at bit ST[4] of the status  
register.ThebitprovideswriteprotectstatusofglobalWrite  
EnableandWriteDisablecommands. Uponpower-upthe  
WE bit resets to 0.  
Ready/Busy Status, BUSY  
The BUSY status bit is located at bit ST[7] of the status  
register. Testing the BUSY bit is one of several ways to  
check Ready/Busy status of the array. At power-up the  
BUSY bit is reset to 0.  
WE=1 Write Enabled, array can be written to.  
WE=0 Write Disabled, array can not be written to.  
BUSY=1 The device is busy programming.  
BUSY=0 The deivce is ready for further use.  
ST7 ST6 ST5 ST4 ST3 ST2 ST1 ST0  
X
Busy TR  
X
WE CNE  
X
PD  
x =RESERVED  
READ/BUSY  
SRAM TRANSFER OR COMPARE  
POWER DETECT  
SECTOR-SRAM COMPARE NOT EQUAL  
FLASH ARRAY WRITE ENABLE/DISABLE  
Figure 8. Status Register Bit Locations  
PowerDetect,PD  
Compare Not Equal, CNE  
The CNE status bit is located at bit ST[3] of the status  
register. The bit provides a cumulative comparison result  
during a Compare Sector with SRAM command. The CNE  
bitisresettoa0uponpower-uporafteraClearCompareBit  
command is executed.  
The Power Detect bit works in conjunction with the Set  
Power Detection and Reset Power Detection Commands  
andisprimarilyusedforremovablemediaapplications.The  
SetPowerDetectCommandmustbeissuedbeforethePD  
bit can be used for power detection.  
PD=0 Power has been removed  
PD=1 Power has not been removed  
CNE=1 Sector and SRAM contents are not equal.  
CNE=0 Sector and SRAM are equal or CNE bit reset.  
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NX25F011B  
NX25F021B  
NX25F041B  
Command Set  
The NX25F011B, NX25F021B, and NX25F041B have a  
powerful command set that is fully controlled through the  
SPI bus. Command relations are shown in Figure 5 and a  
list of commands and their associated address, status,  
clock, anddatabytesareshowninTable3. Detailedclock  
timing of the Read Sector and Write Sector command  
sequences are shown in Figures 9 and 10.  
1
2
After power up, a device enters an idle state that will  
maintain until CS pin is asserted low. All commands are  
enteredfromtheSPIserialdatainput(SI)pinontherising  
edge of SCK while CS is asserted low. All command,  
address, and configuration bits are shifted into the device  
with most-significant-bit-first. Data bits read from the  
device are shifted out with least significant byte first  
(i.e., byte-00H, byte-01H,...). The bit order within each  
byte is most-significant-bit first (i.e.,D7,...D0). All com-  
mands are completed by asserting the CS pin high.  
3
4
5
Note that the entire 264-byte contents of a Flash sector or  
theSRAMdoesnothavetobeaccessedallatonce.Read,  
Write, Transfer Clocked, and Compare Clocked com-  
mands allow for byte addressing. Thus a single byte, or  
clocked sequence of bytes, can be accessed at any  
startinglocationwithinthe264-byteboundaryasspecified  
by the byte-address field.  
6
7
8
9
10  
11  
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NX25F011B  
NX25F021B  
NX25F041B  
CS  
C[7:0] Command  
S[15:0] Sector Address  
Idle  
SCK  
SI  
C7 C6 C5 C4 C3 C2 C1 C0  
0
0
0
0
0 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0  
SO Output is Driven  
B[15:0] Byte Address  
16 Clocks  
SCK  
SI  
0
0
0
0
0
0
0
B8 B7 B6 B5 B4 B3 B2 B1 B0  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SO  
High-Z  
RB[15:0] Ready/Busy Status (9999H=Ready)  
1
st Byte of Data  
2nd Byte of Data  
SCK  
SO  
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D4 D5 D3 D2 D1 D0  
Last Byte of Data  
Idle  
n-Bytes of Data  
CS  
SCK  
SO  
D7 D6 D5 D4 D3 D2 D1 D0  
High-Z  
Figure 9. Read from Sector Command Sequence  
CS  
C[7:0] Command  
S[15:0] Sector Address  
Idle  
SCK  
SI  
C7 C6 C5 C4 C3 C2 C1 C0  
0
0
0
0
0 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0  
B[15:0] Byte Address  
1st Byte of Data  
2nd Byte of Data  
SCK  
SI  
0
0
0
0
0
0
0
B8 B7 B6 B5 B4 B3 B2 B1 B0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0  
Last Byte of Data  
8 Clocks  
n-Bytes of Data  
CS  
tWP Program Time  
SCK  
SI  
D7 D6 D5 D4 D3 D2 D1 D0  
0
0
0
0
0
0
0
0
Figure 10. Write to Sector Command Sequence  
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NX25F011B  
NX25F021B  
NX25F041B  
Command Set for the NX25F011B, NX25F021B and NX25F041B Serial Flash Memory  
n-bytes  
CommandName  
Byte0 Byte1-2  
Byte3-4  
(Italicsindicatedeviceoutput)  
1
SectorCommands  
ReadFromSector  
ReadFromSectorw/AutoInc(3)  
52H  
50H  
51H  
Sectoraddress Byteaddress  
Sectoraddress 0000H  
0000H  
Ready/Busy  
Ready/Busy  
Ready/Busy  
Ready/Busy  
ReadData  
0000H  
0000H  
0000H  
Read Data  
ReadData  
ReadData  
2
ReadFromSectorLowFreq.  
Sectoraddress Byteaddress  
ReadFromSector  
5BH Sectoraddress 0000H  
w/AutoIncLowFreq(3)  
WriteEnable(1)  
WriteDisable(1)  
WritetoSector(throughSRAM) (2)  
Serial SRAM Commands  
WritetoSRAM(2),(3)  
06H  
04H  
00H  
00H  
3
F3H Sectoraddress Byteaddress  
WriteData 00H  
4
72H  
71H  
Byteaddress  
Byteaddress  
Writedata  
00H  
00H  
ReadfromSRAM (1),(3)  
ReadData  
TransferallofSRAMtoSector  
TransferallofSectortoSRAM(3)  
CompareSectortoSRAM(3)  
F3H Sectoraddress 0000H  
53H Sectoraddress 0000H  
8DH Sectoraddress Byteaddress  
0000H  
0000H  
5
ConfigurationandStatusCommands  
ReadConfiguration(1),(3)  
8CH Configuration  
8AH Configuration  
6
WriteNon-Volatile  
0000H  
Configuration Register(1)  
ReadStatusRegister(1),(3)  
ClearCompareStatus(1)  
SetPowerDetectionBit(1),(3)  
ResetPowerDetectionBit(1),(3)  
ReadDeviceInformationSector  
Special Sector Commands (3),(4)  
EraseSector  
84H  
89H  
03H  
09H  
15H  
Status(8bits)  
7
0000H  
Byteaddress  
0000H  
Ready/Busy  
DISData  
8
F1H Sectoraddress 0000H  
F4H Blockaddress 0000H  
F2H Sectoraddress Byteaddress  
EraseBlock  
9
Write-OnlytoSectorthroughSRAM  
WriteData 00H  
CompatibilityCommandsfor25xxxASeriesDevices  
ReadfromSRAM  
81H  
82H  
0000H  
0000H  
Byteaddress  
Byteaddress  
0000H  
0000H  
Read/Busy  
ReadData  
WritetoSRAM  
Writedata 00H  
10  
11  
12  
ReadConfigurationRegister  
ReadStatusRegister  
8BH 0000H  
0000H  
0000H  
N*00H  
0000H  
Ready/Busy  
Configuration  
Status  
83H  
54H  
86H  
0000H  
0000H  
Ready/Busy  
00H  
TransferSectortoSRAMClocked  
CompareSectortoSRAMClocked  
Sectoraddress Byteaddress  
Sectoraddress Byteaddress  
Ready/BusyBitcompareofdata  
Notes:  
1. Command may be used when device is busy  
2. Command may not be used when device is busy and TR bit=0  
3. New “B” series command  
4. Warning: Read description of these commands before using to ensure reliable operation.  
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NX25F011B  
NX25F021B  
NX25F041B  
SERIAL FLASH SECTOR COMMANDS  
Read From Sector (52H)  
Reading from a sector is accomplished by first bringing  
CS low then shifting in the Read from Sector command  
(52H) followed by its 16-bit “sector-address” field.  
Although the sector-address field is 16-bits, only bits  
S[8:0] for the NX25F011B (0-1FFH), S[9:0] for the  
NX25F021B (0-3FFH), S[10:0] for the NX25F041B  
(0-7FFH) are used. The uppermost sector address bits  
are not used but must be clocked using 0 for data. Next  
a 16-bit “byte-address” field is clocked into the device to  
designate the starting location within the 264-byte  
sector. Only B[8:0] of the byte-address field are used;  
the uppermost bits are not used but must be clocked in  
(use 0 for data). Only byte-addresses of 0 to 107H  
(264 bytes) are valid. Following the byte-address field,  
16 control clocks are required with data=0.  
byte-address is internally incremented to the next higher  
byte address as the clock continues. When the highest  
byte-address (107H) is reached, the address counter  
rolls over to byte-0H and continues to increment. Assert-  
ing the CS pin high completes (or terminates) the  
command. Detailed timing for the Read from Sector  
command is shown in Figure 10.  
Read From Sector with Auto Increment (50H)  
The Read from sector with Auto Increment command  
operates similar to the standard Read from Sector com-  
mand except that after the last bit of the current sector is  
clocked the next sequentially addressed sector will be  
automaticallyselectedforreadingwithoutrequiringthenine  
byte command sequence to be issued. This allows the  
entiredeviceoralargenumberofsectorstobereadoutwith  
a single command.  
The Serial Data Output (SO) will change from a  
high-impedance state and begin to drive the output with  
Ready/Busy status RB[15:0]. If SO uses the rising edge  
of clock (configuration register RCE=1), the output will  
be driven after the last control clock. If SO uses the  
falling edge of clock (RCE=0), the output will be driven  
on the next falling edge of clock. If the array is not busy,  
the output status will be 9999H, followed by the sector  
data on the SO pin. If the array is busy, the status will be  
6666H, and the command should be terminated and  
restarted after a ready state occurs. The data field is  
shifted out with the least significant byte first (i.e.,  
byte-00H, byte-01H, ...). The bit order within each byte  
is the most significant bit first (i.e.,D7,...D0). The  
Read From Sector Low Frequency (51H) and  
Read From Sector Low Frequency with Auto  
Increment (5BH)  
The Read From Sector at Low Frequency command (51H)  
andReadFromSectorLowFrequencywithAutoIncrement  
command(5BH)canreducepowerconsumptionduringread  
operations by 25%-40% when the system clock frequency  
is1MHzorlower. Thecommandsequencesareidenticalto  
thestandardcommands.  
Read from  
Sector  
Sector  
Byte  
Address**  
Address*  
Command  
16 Clocks  
0000H  
SI  
52H, 50H, 51H, 53H  
S[15:0]  
B[15:0]  
SO  
RB[15:0]  
First Byte - Last Byte  
Read Sector Data  
Read/Busy  
Status  
*The sector address only uses bits [8:0], [9:0] or [10:0] Depending on the density  
**The byte address only uses bits [8:0]. Byte address must be 0000h for Auto Increment commands  
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Write Enable (06H)  
Uponpower-up,theFlashmemoryarrayiswrite-protected  
untiltheWriteEnablecommand(06H)hasbeenissued.The  
WP pin must be inactive while writing the command for the  
writeenabletobeaccepted.Thestatusofthedevice’swrite  
protect state can be read in the status register. The Write  
Enable command sequence is completed by asserting CS  
high after eight additional clocks.  
Write Enable  
Command  
8 Clocks  
00H  
1
06H  
SI  
SO  
2
3
4
Write Disable (04H)  
The Write Disable command (04H) protects the Flash  
memory array from being programmed. Once issued, fur-  
therWritetoSectororTransferSRAMtoSectorcommands  
will be ignored. The status of the write protect state can be  
read in the status register. The Write Disable command  
sequence is completed by asserting CS high after eight  
additional clocks.  
Write Disable  
Command  
8 Clocks  
00H  
5
04H  
SI  
SO  
6
7
8
9
10  
11  
12  
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Write to Sector Through SRAM (F3H)  
After the byte-address has been loaded, data is shifted  
into the 264-byte SRAM, which serves as a temporary  
storage buffer. Existing data in the SRAM will be written  
over. The byte order of the data shifted into the SRAM is  
least significant byte first (i.e., byte-00H, byte-01H,...).  
The bit order within each byte is most significant bit first  
(i.e., D7,...D0). The byte-address is automatically incre-  
mented to the next higher byte address as the clock  
continues. When the last byte address to be written is  
reached, the command can be completed with an  
additional eight control clocks (with data=0) followed by  
asserting CS high. If the clock continues to increment  
pastthehighestbyte-address(107H),theaddresscounter  
will roll over to byte 0H.  
Before writing to a sector in the Flash memory array, all  
hardware and software write protection must be in an  
enabled state. This means that the WP pin must be in a  
high state, a Write Enable command must have previ-  
ously been issued, and the sector location that is to be  
written to must be outside the write protect range set in  
the configuration register. Additionally, the Ready/Busy  
status should be checked to confirm that the memory  
array is available to be written to.  
Writing to a sector is accomplished by first bringing CS  
low and shifting in the Write to Sector command (F3H)  
followed by a 16-bit “sector-address” field. Although the  
sector-address field is 16-bits, only bits S[8:0] for the  
NX25F011B (0-1FFH), S[9:0] for the NX25F021B  
(0-3FFH), or S[10:0] for the NX25F041B (0-7FFH) are  
used. The uppermost sector address bits are not used  
but must be clocked in (use 0 data). Following the sector  
address, a 16-bit “byte-address” field is clocked into the  
deviceto designatethestartinglocationwithinthe264-byte  
sector. Only bits B[8:0] of the byte-address field are used  
and only values of 0-107H (264 bytes) are valid.  
After the CS pin is brought high, the data in the SRAM is  
transferred to the specified sector in memory array. See  
tWP timing specifications. During this time the array and  
SRAMwill be “busy” and will ignore further array-related  
commands until complete. All Ready/Busy status indi-  
cators will indicate a busy status. Detailed clock timing  
for the Write to Sector command is shown in Figure 11.  
Write to  
Sector  
Command  
Sector  
Address*  
Byte  
Address**  
Program  
Time  
8 Clocks  
00H  
Write Sector Data  
SI  
F3H  
S[15:0]  
B[15:0]  
First Byte - Last Byte  
(tWP)  
SO  
*The sector address only uses bits [8:0], [9:0] or [10:0]  
**The byte address only uses bits [8:0]  
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SERIAL SRAM COMMANDS  
Write to SRAM Command (72H)  
1
The Write to SRAM command (72H) provides access to  
the 264-Byte SRAM independently of any Flash memory  
array operation. When CS is asserted high to complete  
the command, the contents of the SRAM will be main-  
tained until overwritten through another command or the  
power is removed. Using the Write to SRAM command,  
data can be loaded in preparation of writing to a sector in  
memory and then transferred to a selected sector using  
the Transfer SRAM to Sector command. TheTRbitinthe  
status register should be checked first if Transfer Sector to  
SRAM or Compare Sector to SRAM commands are used.  
2
3
Write to  
SRAM  
Byte  
Command  
Address*  
Write Sector Data  
First Byte - Last Byte  
8 Clocks  
00H  
SI  
72H  
B[15:0]  
4
SO  
*The byte address only uses bits [8:0]  
5
6
7
Read from SRAM (71H)  
TheReadfromSRAMcommand(71H)providesaccessto  
the 264-Byte SRAM independent of any Flash memory  
arrayoperations.TheTRbitinthestatusregistershouldbe  
checkedfirstifTransferSectortoSRAMorCompareSector  
to SRAM commands are used.  
8
9
Read from  
SRAM  
Command  
Byte  
Address*  
10  
11  
12  
8 Clocks  
00H  
SI  
71H  
B[15:0]  
SO  
First Byte-Last Byte  
Read SRAM Data  
*The byte address only uses bits [8:0]  
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Transfer All of SRAM to Sector (F3H)  
Transfer SRAM  
to Sector  
Command  
The Transfer SRAM to Sector command (F3H) will  
write the existing contents of the SRAM to the speci-  
fied sector in memory. The command sequence is  
identical to that of the Write to Sector command  
except that immediately after the sector address field  
S[15:0] and 16 control clocks, the CS pin is asserted  
high. This automatically transfers the 264-bytes of  
SRAM data to the specified sector in the memory array.  
During this time, the array will be busy. Since the entire  
264-bytes are transferred, the byte-address field B[15:0]  
is not used.  
Sector  
Address*  
16 Clocks  
0000H  
Program Time  
SI  
F3H  
S[15:0]  
(tWP)  
SO  
*The sector address only uses bits [8:0], [9:0] or [10:0]  
Depending on device density  
Transfer All of Sector to SRAM (53H)  
Transfer Sector  
to SRAM  
Command  
The Transfer Sector to SRAM command (53H) allows the  
contents of a sector to be transferred directly to the SRAM  
without having to clock or read the sector out of the device  
and rewrite it into the SRAM. During the transfer, the SO  
output is in a high-impedance state and the TR bit in the  
status register will be set to a "1" state. When the last byte  
addressistransferredtheTRbitinthestatusregisterwillbe  
cleared. Note that the Transfer Sector to SRAM Clocked  
command (54H) can also be used if partial transfers are  
required.  
Sector  
Address*  
32  
Clocks  
Transfer Time  
tXS  
SI  
53H  
S[15:0]  
0000 0000H  
(
)
SO  
*The sector address only uses bits [8:0], [9:0] or [10:0]  
Depending on device density  
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Compare Sector to SRAM (8DH)  
The Compare Sector to SRAM command (8DH) does a  
bit-by-bit comparison of the data stored in the addressed  
sectoragainstdataintheSRAM.TheTRbitwillbe1during  
thetransfercompareoperation.Ifanyofthecomparedbits  
arenotequal, thentheCompareNotEqual(CNE)bitinthe  
StatusRegisterissettoa1.ThisbitwillstaysetuntilaClear  
Compare Status command has been issued. Note that the  
CompareSectortoSRAMClockedcommandcanbeused  
if partial compares are required. This command is very  
useful for performing a fast verify of the Last Sector write  
operation.Thisverifyprovidesforthehighestdataintegrity.  
1
2
Compare Sector  
Sector  
Address*  
Sector  
Address*  
with SRAM  
Command  
Compare Time  
16 Clocks  
0000H  
3
SI  
8DH  
S[15:0]  
B[15:0]  
(tXS)  
SO  
4
*The sector address only uses bits [8:0], [9:0] or [10:0]  
Depending on device density  
5
6
7
CONFIGURATION AND STATUS  
COMMANDS  
8
Read Configuration Register (8CH)  
Read Configuration  
Register  
The Read Configuration Register command provides  
access to the configuration register, which stores the  
current configuration of the HOLD-R/B pin, read clock  
edge, write protect range, and alternate oscillator  
frequency (Figure 7). A 16-bit Configuration Data field  
CF[15:0] provides the contents of the Configuration  
Register. Although the field is 16-bits long, only bits  
CF[7:0] are used. All other upper bits are reserved for  
future features.  
9
Command  
SI  
8CH  
10  
11  
12  
SO  
CF{15:0}*  
Read Configuration Bits  
*The CF Register only uses bits [7:0]  
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Write Non-Volatile Configuration  
Register (8AH)  
The Write Configuration Register command provides ac-  
cess to the configuration register which stores the current  
configurationoftheHOLD-R/Bpin, read-dataclockedge,  
writeprotectrange,andalternateoscillatorfrequency.The  
configuration register is non-volatile. Once set using the  
Write Configuration Register command, the contents will  
maintain even when power is removed. Because the  
register’s state is stored in non-volatile memory, there is  
a finite endurance limit to the number of times it can be  
writtento.Tolimitthenumberofwrites,itisrecommended  
that before writing to the configuration register it should  
first be read from using the Read Configuration Register  
command.Ifnochangeisrequired,theWriteConfiguration  
Registercommandcanbeskipped. Thisprocesswillhelp  
extendtheenduranceoftheconfigurationregisterbitsand  
eliminate additional programming “busy” time.  
The Write Configuration Register command sequence  
starts with the command byte (8AH) followed by a 16-bit  
field that specifies configuration register bit settings.  
Although the field is 16-bits long, only bits CF[7:0] are  
used. All other upper bits are reserved and must be  
clocked using 0 for data. After an additional 16 control  
clocks using 0 for data, the command can be completed  
by asserting CS high. The device will become busy for a  
short time (tWP) while the non-volatile memory cells of the  
configurationregisterareprogrammed.  
Write  
Configuration  
Register  
Command  
Configuration  
Bits*  
Program Time  
16 Clocks  
8AH  
CF[15:0]  
0000H  
(
tWP  
)
SI  
SO  
*The CF Register only uses bits [7:0]  
Read Status Register (84H)  
The Read Status Register command provides access to  
the status register and its status flags for Ready/Busy  
(R/B),SRAMandprogrambuffertransferoperations(TX),  
WriteEnable/Disable(WE),andCompareNotEqual(CNE)  
(Figure 8). An 8-bit Status field ST[7:0] provides the  
contents of the Status Register.  
Read Status  
Register  
Command  
SI  
84H  
SO  
ST[7:0]  
Read Status Register Bits  
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Clear Compare Status (89H)  
The Clear Compare Status command (89H) works in con-  
junction with the Compare Sector to SRAM command and  
the Status Register. If any of the compared bits are not  
equal, then the Compare Not Equal (CNE) bit in the Status  
Registerissettoa1.TheClearCompareStatuscommand  
must be executed to reset the CNE bit to a 0.  
Clear Compare  
Status  
Command  
1
8 Clocks  
00H  
89H  
SI  
2
SO  
3
4
Set Power Detection Bit (03H)  
5
The Set Power Detection Bit command (03H) can be used  
to detect if power has been removed from the device. The  
commandworksinconjunctionwiththePowerDetect(PD)  
statusbit. UponpowerupthePDbitisclearedto0. ThePD  
bit can be set to a 1 using the Set Power Detection Bit  
command. Once set, if a power down condition occurs  
(Vcc voltage < 2V) the PD bit will reset to 0. This function  
is especially useful for applications using NexFlash Serial  
Flash Modules or other removable media.  
Set Power  
Detection  
Bit  
8 Clocks  
00H  
03H  
SI  
6
SO  
7
8
9
Reset Power Detection Bit (09H)  
10  
11  
12  
Reset Power  
Detection  
Bit  
TheResetPowerDetectionBitcommand(09H)canbeused  
toforcethePowerDetectStatusbitinthestatusregisterto  
a 0 state. (see Set Power Detection Bit command (03H).  
8 Clocks  
00H  
09H  
SI  
SO  
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Read Device Information Sector (15H)  
The Read Device Information command provides access  
to a read-only sector that can be used to electronically  
identify the NexFlash Serial Flash device being inter-  
faced to. Information available includes: part number,  
density, voltage, temperature range, package type, and  
any special options. This can be extremely useful for  
systems that need to accommodate optional densities  
(e.g., both1M-bitor2M-bit). Inthiscasethefirmwarecan  
interrogate the Device Information Sector and  
determine the density. The Device Information Sector  
also includes a list of any restricted sectors that might  
exist in the device. Contact NexFlash for more detailed  
information on the Device Information Sector format.  
Read Device  
Info. Sector  
Command  
Byte  
Address*  
16 Clocks  
0000H  
16 Clocks  
0000H  
SI  
15H  
B[15:0]  
SO  
RB[15:0]  
First Byte - Last Byte  
Read Sector Data  
Read/Busy  
Status  
*The byte address only uses bits [8:0]  
SPECIAL SECTOR COMMANDS  
Erase Sector (F1H)  
The Erase Sector command (F1H) will erase a sector to an  
“all 1s” state, during this time the array will be "busy." This  
command can be used in conjunction with the Write only to  
Sector through SRAM command (F2H) to achieve faster  
program performance in applications that can accommo-  
date pre-erase. (see TEO in AC Characteristics for  
erase timing).  
Erase  
Sector  
Command  
Sector  
Address*  
16  
Clocks  
Transfer Time  
(tEO)  
SI  
F1H  
S[15:0]  
0000H  
SO  
*The sector address only uses bits [8:0], [9:0] or [10:0]  
Depending on device density  
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Erase Block (F4H)  
The Erase Block command (F4H) will erase a block of 32  
sectors to an “all 1s” state, during this time the array will be  
"busy."This command can be used in conjunction with the  
Write only to Sector through SRAM command (F2H) to  
achieve faster program performance in applications that  
can accommodate pre-erase.(seeTEO in AC Characteris-  
tics for erase and write timing).  
Erase  
Block  
Block  
Address*  
16  
Clocks  
Transfer Time  
1
(tEO)  
SI  
F4H  
BLK[15:0]  
0000H  
SO  
2
*The Block address only uses bits [8:5], [9:5] or [10:5]  
Depending on device density. Lowest four bit [4:0] must be 0h  
3
4
5
6
Write-only to Sector (F2H)  
The Write-Only to Sector through SRAM command (F2H)  
will write a pre-erased sector in about half the time of the  
standard Write to Sector through SRAM command (F3H),  
during this time the array will be "busy." This command  
can be used in conjunction with the Erase Sector com-  
mand (F1H) or Erase Block command (F4H) to achieve  
faster program performance in applications that can  
accommodate pre-erase. (see TWO inAC Characteristics  
for erase and write timing). Warning: to ensure data integ-  
rity this command should only be issued after an erase  
command.  
7
8
Write only  
to Sector  
Command  
9
Sector  
Address*  
Byte  
Address**  
Program  
Time  
8 Clocks  
00H  
Write Sector Data  
SI  
F2H  
S[15:0]  
B[15:0]  
First Byte - Last Byte  
(tWP)  
10  
11  
12  
SO  
*The sector address only uses bits [8:0], [9:0] or [10:0] Depending on device density  
**The byte address only uses bits [8:0]  
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COMPATIBILITY COMMANDS FOR 25xxxA  
SERIES DEVICES  
Read from SRAM (81H)  
TheReadfromSRAMcommand(81H)providesaccessto  
the 264-Byte SRAM independent of any Flash memory  
arrayoperations.ThecommandissimilartotheReadfrom  
Sector command except for the sector address field  
S[15:0] which is replaced with all 0 bits.  
Read from  
SRAM  
Byte  
Command  
Address*  
16 Clocks  
0000H  
16 Clocks  
0000H  
SI  
81H  
B[15:0]  
SO  
RB[15:0]  
First Byte - Last Byte  
Read SRAM Data  
Read/Busy  
Status  
*The byte address only uses bits [8:0]  
Write to SRAM (82H)  
The Write to SRAM command (82H) provides access to  
the 264-Byte SRAM independently of any Flash memory  
array operation. The command is similar to the Write to  
Sector command sequence except that the sector  
address field S[15:0] is replaced by all 0 bits. When CS  
is asserted high to complete the command, the contents  
of the SRAM will be maintained until overwritten through  
another command or the power is removed. Using the  
Write to SRAM command, data can be loaded in prepara-  
tion of writing to a sector in memory and then transferred  
to a selected sector using the Transfer SRAM to Sector  
command.  
Write to  
SRAM  
Command  
Byte  
Address*  
16 Clocks  
0000H  
8 Clocks  
00H  
Write Sector Data  
SI  
82H  
B[15:0]  
First Byte - Last Byte  
SO  
*The byte address only uses bits [8:0]  
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Read Configuration Register (8BH)  
The Read Configuration Register command provides  
access to the configuration register, which stores the  
current configuration of the HOLD-R/B pin, read clock  
edge, write protect range, and alternate oscillator  
frequency (Figure 7). The command sequence is similar  
to the Read from Sector command except that the sector  
address field S[15:0] and the byte-address field B[15:0]  
are replaced with all 0 bits. After 16 control clocks and  
after the Ready/Busy status field has been clocked  
through, a 16-bit Configuration Data field CF[15:0]  
provides the contents of the Configuration Register.  
Although the field is 16-bits long, only bits CF[7:0] are  
used. All other upper bits are reserved for future  
features.  
1
2
Read Configuration  
Register  
3
16 Clocks  
Command  
16 Clocks  
0000H  
16 Clocks  
0000H  
SI  
8BH  
0000H  
4
SO  
RB[15:0]  
CF{15:0}*  
Read Configuration Bits  
Read/Busy  
Status  
*The CF Register only uses bits [7:0]  
5
6
7
Read Status Register (83H)  
8
The Read Status Register command provides access to  
the status register and its status flags for Ready/Busy  
(R/B),SRAMandprogrambuffertransferoperations(TX),  
WriteEnable/Disable(WE),andCompareNotEqual(CNE)  
(Figure 8). The command sequence is similar to the Read  
From Sector command except that the sector address  
fieldS[15:0]andthebyte-addressfieldB[15:0]arereplaced  
byall0bits.After16clocksandtheReady/Busystatusfield  
RB[15:0] has been read, an 8-bit Status field ST[7:0]  
provides the contents of the Status Register.  
9
Read Status  
Register  
Command  
10  
11  
12  
16 Clocks  
0000H  
16 Clocks  
0000H  
16 Clocks  
0000H  
SI  
83H  
SO  
RB[15:0]  
ST[7:0]  
Read Status  
Register Bits  
Read/Busy  
Status  
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Transfer Sector to SRAM Clocked (54H)  
mended to write data bytes of 00H in order to support the  
clockingrequirements.Duringthetransfer,theSOoutputis  
in a high-impedance state. When the last byte address is  
transferred, the command can be completed by issuing  
eightmorecontrolclocksandassertingCShigh.Iftheclock  
continues to increment past the highest byte-address  
(107H), the address counter will roll over to byte-0H. This  
command can also be used to load partial sectors into  
SRAM  
The Transfer Sector to SRAM Clocked command (54H)  
allows the contents of a sector to be transferred directly to  
theSRAMwithouthavingtoreadthesectoroutofthedevice  
andrewriteitintotheSRAM.Thecommandissimilartothe  
Write to Sector command except that instead of inputting  
data from the SI pin, the data is taken from the specified  
sector and is transferred to the SRAM. Every eight clocks  
on SCK, a byte from the specified sector to the SRAM will  
be transferred. Although data on SI is ignored, it is recom-  
Transfer Sector  
8 Clocks per Byte Trasnfered  
to SRAM  
Sector  
Byte  
from First Byte to Last Byte  
Command  
Address*  
Address**  
8 Clocks  
00H  
SI  
54H  
S[15:0]  
B[15:0]  
SI=00H During Byte Ttansfers  
SO  
*The sector address only uses bits [8:0], [9:0] or [10:0] Depending on device density  
**The byte address only uses bits [8:0]  
Compare Sector to SRAM Clocked (86H)  
The Compare Sector to SRAM command does a bit-by-bit  
comparison of the data stored in the addressed sector  
against data in the SRAM. The command is similar to the  
ReadfromSectorcommandexceptthatdataisnotreadout  
of the Serial Output pin (SO). Instead, the SO pin provides  
abit-by-bitcompareofeachsectorandSRAMbit.Ahigh(1)  
perbitwillbeoutputifthebitcompareisequal.Alow(0)per  
bitwillbeoutputifthebitcompareisnotequal.Thecompare  
can start from any location in the 264-byte range as  
specified by the byte-address field B[15:0]. The  
byte-addresscounterisautomaticallyincrementedandwill  
wrap around to the first address (0H) if it passes the last  
address (107H). If any of the compared bits are not equal,  
thentheCompareNotEqual(CNE)bitintheStatusRegister  
is set to a 1. This bit will stay set until a Clear Compare  
Statuscommandhasbeenissued.Thiscommandcanalso  
be used to load partial sectors into SRAM  
Compare Sector  
with SRAM  
Command  
Sector  
Address*  
Byte  
Address**  
16 Clocks  
0000H  
SI  
86H  
S[15:0]  
B[15:0]  
SO  
RB[15:0]  
First Byte - Last Byte  
Bit Compare of Sector  
and SRAM  
Read/Busy  
Status  
*The sector address only uses bits [8:0], [9:0] or [10:0] Depending on device density  
**The byte address only uses bits [8:0]  
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Sector Format  
Grouping Static and Frequently  
Updated Data  
The memory array of standard Serial Flash devices are  
factory programmed to a full erase state with all bits set to  
“1” (FFH). NexFlash also offers restricted sector devices  
(with “-R” suffix) which may provide a more cost effective  
alternative to standard devices that have 100% valid  
sectors. Restricted sector devices have a limited number  
of sectors that do not meet manufacturing programming  
criteria over the specified operating range. The first bye of  
eachgoodsectorina“-R”deviceispre-programmedduring  
manufacturing with a tag/sync value of C9H. Although this  
byte location of the sector can be changed, it is recom-  
mended that it be maintained and incorporated into the  
application’ssectorformatting. Thetag/syncvaluesserve  
two purposes. First, they provide a sync-detect that can  
help verify if the command sequence was clocked into the  
device properly. Secondly, they serve as a tag to identify  
a fully functional (valid) sector. For defective sectors, the  
firstbyteistaggedwithapatternotherthanC9H. Inaddition  
toindividualsectortagging,allrestrictedsectorsforagiven  
devicearelistedintheDeviceInformationSector. Formore  
information see the latest version of Device Information  
Sector Application Note SFAN-02.  
In the NX25F011B/021B/041B a data block is every 32  
sectors starting from sector 0; that is, block 0 is sector  
0 - 31, block 1 is sector 32 - 63 and so on. Refer to figure  
4. For the highest data integrity, it is important to separate  
static data (configuration settings, tables) and frequently  
updated data (streaming voice/image or data acquisition)  
into separate blocks. Following this convention optimizes  
the environment for the data stored in the flash cells within  
each block.  
1
2
3
4
Write Verify  
5
Write to SRAM Command  
6
Transfer SRAM to Sector Command  
High Data Integrity Applications  
Data storage applications that use Flash memory or other  
non-volatile media must take into consideration the possi-  
bility of noise or other adverse system conditions that may  
affect data integrity. For those applications that require  
higher levels of data integrity it is a recommended practice  
to use Error Correcting Code (ECC) techniques. The  
NexFlashSerialFlashDevelopmentKitprovidesasoftware  
routine for a 32-bit ECC that can detect up to two bit errors  
and correct one. The ECC not only minimizes problems  
causedbysystemnoisebutcanalsoextendFlashmemory  
endurance.  
7
Ready?  
NO  
Programming  
Done?  
8
YES  
Compare Sector with SRAM Command  
9
Write/VerifyFlow  
NO  
Equivalent  
For those systemswithouttheprocessingpowertohandle  
ECCalgorithms,asimple“verificationafterwrite”isrecom-  
mended.Thewriteverifycanbedonequickly(lessthantXS)  
using the Compare Sector command. The compare result  
can be checked in the Status Register. If compare is not  
equal (CNE=1) then a sector rewrite should be done using  
theTransfertoSectorcommand(Figure12). Asingleretry  
is adequate for most applications. However, if an applica-  
tion requires extended endurance additional retrys can be  
added.TheSerialFlashDevelopmentKitsoftwareincludes  
a simple Write/Verify routine that will compare data written  
to a given sector and rewrite the sector if the compare is  
not correct.  
10  
11  
12  
Retry  
Retry  
Counter  
No More  
Retries  
YES  
Return  
Error  
Figure 12. Write/Verify Flow  
NexFlashTechnologies, Inc.  
29  
PRELIMINARYNXSF016F-1201  
12/12/01 ©  
NX25F011B  
NX25F021B  
NX25F041B  
ABOSOLUTE MINIMUM RATINGS (1)  
Symbol  
Vcc  
Parameters  
Conditions  
Range  
0 to 7.0  
Unit  
V
SupplyVoltage  
VIN, VOUT  
TSTG  
Voltage Applied to Any Pin  
StorageTemperature  
LeadTemperature  
RelativetoGround  
Soldering10Seconds  
–0.5 to Vcc + 0.5  
–65 to +150  
+300  
V
°C  
°C  
TLEAD  
Note:  
1. This device has been designed and tested for the specified operation ranges. Proper operation outside of these levels is not  
guaranteed. Exposure beyond absolute maximum ratings (listed above) may cause permanent damage.  
OPERATING RANGES  
Symbol  
Parameter  
Supply Voltage (1)  
Conditions  
Min  
Max  
Unit  
Vcc  
5.0Vprograming  
3.0V or 3.3 V programing  
Commercial  
Extended  
Industrial  
4.5  
2.7  
0
–20  
–40  
5.5  
3.6  
+70  
+70  
+85  
V
V
°C  
°C  
°C  
TA  
AmbientTemperature,Operating  
PowerRampTime  
TRVCC  
—
10  
ms  
Note:  
1. Vcc voltage during Read can operate across the min and max range but should not exceed 10% of the programming  
(erase/write) voltage.  
(2)  
DC ELECTRICAL CHARACTERISTICS (Preliminary)  
Symbol  
VIL  
VIH  
Parameter  
Conditions  
Min  
–0.4  
Vccx0.6  
—
2.4  
—
VCC–0.3  
–10  
–10  
Typ  
—
—
—
—
—
—
—
—
Max  
Vccx0.2  
Vcc+0.5  
0.45  
—
0.15  
—
+10  
+10  
Unit  
Input Low Voltage  
Input High Voltage  
OutputLowVoltage  
OutputHighVoltage  
Output Low Voltage CMOS VCC = Min, IOL = 10 µA  
Output High Voltage CMOS VCC = Min, IOH = –10 µA  
V
V
V
V
V
V
µA  
µA  
VOL  
IOL = 2 mA  
IOH = –400 µA  
VCC = 4.5V  
VCC = 4.5V  
VOH  
VOLC  
VOHC  
IIL  
InputLeakage  
I/OLeakage  
0 < VIN < Vcc  
0 < VIN < Vcc  
IOL  
ICC  
(active)  
Active Power Supply Current fCLK @ 8 MHz (1/tCP) VCC = 5V  
VCC = 3V  
5
2
6
2.5  
8
4
mA  
mA  
ICCLF  
Active Current Low  
Frequency.Read  
fCLK @1 MHz (1/tCP) VCC = 5V  
VCC = 3V  
2
1
4
1.5  
5
2
mA  
mA  
(low  
frequency)  
ICCSB  
Standby Vcc Supply Current CS = VCC,  
VIN = Vcc or 0  
Vcc = 5V  
Vcc = 3V  
—
—
—
5
1
—
10  
5
10  
µA  
µA  
pF  
(standby)  
CIN  
Input Capacitance (1)  
TA = 25°C, VCC = 5V or 3V  
Frequency = 1 MHz  
TA = 25°C, VCC = 5V or 3V  
Frequency = 1 MHz  
COUT  
Output Capacitance (1)  
—
—
10  
pF  
Notes:  
1. Tested on a sample basis or specified through design or characterization data.  
2. See Preliminary Designation page 31  
30  
NexFlashTechnologies, Inc.  
PRELIMINARYNXSF016F-1201  
12/12/01 ©  
NX25F011B  
NX25F021B  
NX25F041B  
(4)  
AC ELECTRICAL CHARACTERISTICS (Preliminary)  
Fast SPI  
(RCE=1)  
Standard SPI  
(RCE = 0)  
1
Symbol  
Description  
Min Typ Max  
Min Typ Max  
Unit  
FREQ  
ClockFrequency  
Vcc = 5V  
Vcc = 3V  
0
0
—
—
20  
20  
0
0
—
—
12  
10  
MHz  
MHz  
2
tCYC  
SCK Serial Clock Period (1)  
Vcc = 5V  
Vcc = 3V  
50  
50  
—
—
—
—
80  
100 —  
—
—
—
ns  
ns  
tWH  
tWL  
tRI  
SCK Serial Clock High or Low Time  
24  
—
—
24  
—
—
—
ns  
3
SCK Serial Clock Rise or Fall Time (2)  
Data Input Setup Time to SCLK  
—
—
5
—
5
ns  
tFI  
tSU  
Vcc = 5V  
Vcc = 3V  
14  
25  
—
—
—
—
14  
25  
—
—
—
—
ns  
ns  
4
tIH  
tOH  
tV  
Data Input Hold Time from SCLK  
Data Output Hold Time from SCLK  
Data Output Valid after SCLK (1,3)  
0
0
—
—
—
—
0
0
—
—
—
—
ns  
ns  
Vcc = 5V  
Vcc = 3V  
—
—
—
—
35  
45  
—
—
—
—
35  
45  
ns  
ns  
5
tCSS  
tCSH  
tWP  
CS Setup Time to Command  
CS Hold Time after Command  
Erase/WriteProgramTime  
(see Write to Sector Command)  
Erase Only Time  
100  
100  
—
—
—
—
—
100 —  
100 —  
—
—
ns  
ns  
6
7.5 20  
— 7.5 20  
ms  
tEO  
tWO  
tXS  
—
—
—
2
4
—
2
4
ms  
ms  
µs  
(see Erase Sector/Block Commands)  
Write Only Time  
7
5.5 16  
— 5.5 16  
— 100 150  
(see Write Only to Sector Command)  
TransferorCompareSector  
(seeTransfer/CompareAllCommand)  
SCK Setup Time to HOLD  
SCK Hold Time from HOLD  
CS Deselect Time  
100 150  
8
tHD  
tCD  
tCS  
tRB  
tDIS  
tHZ  
10  
30  
—
—
—
—
—
—
—
—
—
—
60  
60  
10  
30  
—
—
—
—
—
—
60  
60  
ns  
ns  
ns  
ns  
ns  
ns  
9
160  
160  
—
160 —  
160 —  
READY / BUSY Valid Time  
Data Output Disable Time  
DataDisable/EnablefromHOLD  
—
—
—
—
—
10  
11  
12  
Notes:  
1. To achieve maximum clock performance, the read clock edge will need to be set for rising edge operation in the configuration  
register (RCE=1).  
2. Test points are 10% and 90% points for rise/fall times. All others timings are measured at 50% point.  
3. With 30 pF (16 MHz) load SO to GND.  
4. See Preliminary Designation page 31  
NexFlashTechnologies, Inc.  
31  
PRELIMINARYNXSF016F-1201  
12/12/01 ©  
NX25F011B  
NX25F021B  
NX25F041B  
SERIAL OUTPUT TIMING  
CS  
t
CYC  
tWH  
t
CSH  
DIS  
SCK  
t
OH  
MSB-1  
t
WL  
t
V
t
SO  
SI  
MSB  
LSB+1  
LSB  
SERIAL INPUT TIMING  
tCS  
CS  
tCSS  
tRI  
tFI  
tCSH  
SCK  
t
IH  
MSB  
(High Impedance)  
tSU  
SI  
LSB+1  
MSB-1  
LSB  
tRB  
SO  
t
t
XS  
WP  
R/B  
HOLD TIMING  
CS  
t
CD  
tHD  
tHD  
tCD  
SCK  
SO  
t
HZ  
tHZ  
SI  
HOLD  
32  
NexFlashTechnologies, Inc.  
PRELIMINARYNXSF016F-1201  
12/12/01 ©  
NX25F011B  
NX25F021B  
NX25F041B  
PACKAGING INFORMATION  
200-mil Plastic SOIC  
PackageCode:(S)  
1
N
2
E
H
3
4
1
SEATING PLANE  
D
A
5
6
A1  
B
e
L
C
7
200 mil Plastic SOIC (S)  
Millimeters  
8
Inches  
Min  
Symbol  
Min  
Max  
Max  
No.Leads  
8
9
A
A1  
B
C
D
E
e
1.780  
0.102  
0.305  
0.178  
5.160  
5.210  
2.030  
0.330  
0.508  
0.254  
5.380  
5.410  
0.070  
0.004  
0.012  
0.007  
0.203  
0.205  
0.080  
0.013  
0.020  
0.010  
0.212  
0.213  
10  
11  
12  
Notes:  
1. Controlling dimensions: inches, unless otherwise  
specified.  
2. BSC = Basic lead spacing between centers.  
3. Dimensions D and E1 do not include mold flash  
protrusions and should be measured from the  
bottom of the package.  
4. Formed leads shall be planar with respect to one  
another within .0004 inches at the seating plane.  
1.27BSC  
0.050 BSC  
H
L
7.62  
0.508  
0o  
8.38  
0.889  
8o  
0.300  
0.020  
0o  
0.330  
0.035  
8o  
α
NexFlashTechnologies, Inc.  
33  
PRELIMINARYNXSF016F-1201  
12/12/01 ©  
NX25F011B  
NX25F021B  
NX25F041B  
PACKAGING INFORMATION  
330 mil Plastic SOIC  
PackageCode:(J)  
N
E
H
1
D
SEATING PLANE  
A
L
α
e
B
C
A1  
330 Mil Plastic SOIC (J)  
Millimeters  
Min Max  
Inches  
Symbol  
Min  
Max  
Ref. Std.  
No.Leads  
28  
A
A1  
B
C
D
E
H
e
2.388 2.794  
0.051 0.508  
0.051 0.356  
0.203 0.305  
7.983 8.288  
8.585 8.788  
11.68 12.19  
1.27 BSC  
0.094 0.110  
0.002 0.020  
0.002 0.014  
0.008 0.0012  
0.709 0.720  
0.338 0.346  
0.460 0.480  
0.050 BSC  
Notes:  
1. Controlling dimension: inches, unless  
otherwise specified.  
2. BSC = Basic lead spacing between centers.  
3. Dimensions D and E do not include mold  
flash protrusions and should be measured  
from the bottom of the package.  
4. Formed leads shall be planar with respect  
to one another within 0.004 inches at the  
seating plane.  
L
a
0.762 1.270  
0.030 0.050  
0°  
8°  
0°  
8°  
34  
NexFlashTechnologies, Inc.  
PRELIMINARYNXSF016F-1201  
12/12/01 ©  
NX25F011B  
NX25F021B  
NX25F041B  
PACKAGING INFORMATION  
Plastic TSOP - 28-pins  
Package Code: Type I (V)  
1
1
2
3
E
H
4
5
N
D
6
SEATING PLANE  
A
7
L
α
e
B
C
A1  
8
Plastic TSOP Type I (V)  
Millimeters  
Symbol Min Max  
No.Leads  
Inches  
Min Max  
9
28  
A
A1  
B
C
D
E
H
e
L
1.00 1.20  
0.05 0.20  
0.15 0.25  
0.10 0.20  
7.90 8.10  
11.60 11.80  
13.30 13.50  
0.55 BSC  
0.039 0.047  
0.002 0.008  
0.006 0.010  
0.004 0.008  
0.311 0.319  
0.457 0.465  
0.524 0.531  
0.022 BSC  
10  
11  
12  
Notes:  
1. Controlling dimension: millimeters, unless  
otherwise specified.  
2. BSC = Basic lead spacing between centers.  
3. Dimensions D and E do not include mold flash  
protrusions and should be measured from the  
bottom of the package.  
4. Formed leads shall be planar with respect to one  
another within 0.004 inches at the seating plane.  
0.50 0.70  
0.020 0.028  
α
0°  
5°  
0°  
5°  
NexFlashTechnologies, Inc.  
35  
PRELIMINARYNXSF016F-1201  
12/12/01 ©  
NX25F011B  
NX25F021B  
NX25F041B  
PRELIMINARY DESIGNATION  
LIFE SUPPORT POLICY  
The “Preliminary” designation on an NexFlash data sheet  
indicates that the product is not fully characterized. The  
specifications are subject to change and are not guaran-  
teed. NexFlash or an authorized sales representative  
shouldbeconsultedforcurrentinformationbeforeusingthis  
product.  
NexFlash does not recommend the use of any of it's  
products in life support applications where the failure or  
malfunctionoftheproductcanreasonablybeexpectedto  
cause failure in the life support system or to significantly  
affect its safety or effectiveness. Products are not  
authorized for use in such applications unless NexFlash  
receives written assurances, to it’s satisfaction, that:  
IMPORTANT NOTICE  
(a) the risk of injury or damage has been minimized;  
(b) the user assumes all such risks; and  
NexFlash reserves the right to make changes to the  
products contained in this publication in order to improve  
design, performance or reliability. NexFlash assumes no  
responsibility for the use of any circuits described herein,  
conveys no license under any patent or other right, and  
makesnorepresentationthatthecircuitsarefreeofpatent  
infringement. Charts and schedules contained herein re-  
flect representative operating parameters, and may vary  
depending upon a user’s specific application. While the  
informationinthispublicationhasbeencarefullychecked,  
NexFlash shall not be liable for any damages arising as a  
result of any error or omission.  
(c) potential liability of NexFlash is adequately pro-  
tected under the circumstances.  
Trademarks:  
NexFlash is a trademark of NexFlash Technologies, Inc. All  
other marks are the property of their respective owner.  
ORDERING INFORMATION  
Size  
Order Part No.  
NX25F011B-3V*  
NX25F011B-3S*  
NX25F011B-5V*  
NX25F011B-5S*  
Package  
1M-bit  
1M-bit  
1M-bit  
1M-bit  
SPI, 28-pin, TSOP (Type I)3V  
SPI, 8-pin, SOIC 3V  
SPI, 28-pin, TSOP (Type I) 5V  
SPI, 8-pin, SOIC 5V  
2M-bit  
2M-bit  
2M-bit  
2M-bit  
NX25F021B-3V*  
NX25F021B-3S*  
NX25F021B-5V*  
NX25F021B-5S*  
SPI, 28-pin, TSOP (Type I) 3V  
SPI, 8-pin, SOIC 3V  
SPI, 28-pin, TSOP (Type I) 5V  
SPI, 8-pin, SOIC 5V  
4M-bit  
4M-bit  
4M-bit  
4M-bit  
NX25F041B-3V*  
NX25F041B-3J  
NX25F041B-5V*  
NX25F041B-5J  
SPI, 28-pin, TSOP (Type I) 3V  
SPI, 28-pin, SOIC 3V  
SPI, 28-pin, TSOP (Type I) 5V  
SPI, 28-pin, SOIC 5V  
*Note:  
Add -R for Restricted Sector Device (See Serial Flash Application Note SFAN-2 for more information on  
restricted sector devices).  
36  
NexFlashTechnologies, Inc.  
PRELIMINARYNXSF016F-1201  
12/12/01 ©  
NX25F011B  
NX25F021B  
NX25F041B  
1
2
3
4
5
6
7
8
9
10  
11  
12  
NexFlashTechnologies, Inc.  
37  
PRELIMINARYNXSF016F-1201  
12/12/01 ©  
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