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NX2710CSTR

型号:

NX2710CSTR

描述:

与NMOS LDO控制器与5V偏置稳压器单通道PWM控制器[ SINGLE CHANNEL PWM CONTROLLER WITH NMOS LDO CONTROLLER AND 5V BIAS REGULATOR ]

品牌:

MICROSEMI[ Microsemi ]

页数:

23 页

PDF大小:

747 K

NX2710  
SINGLE CHANNEL PWM CONTROLLER WITH NMOS LDO  
CONTROLLER AND 5V BIAS REGULATOR  
ADVANCE DATA SHEET  
Pb Free Product  
FEATURES  
DESCRIPTION  
n
n
n
Bus voltage operation from 9V to 24V  
5V bias regulator available  
The NX2710 controller IC is a compact synchronous  
Buck controller IC with 16 lead SOIC package designed  
for step down DC to DC converter applications with  
feedforward functionality. Voltage feedforward provides  
fast response, good line regulation and nearly constant  
power stage gain under wide voltage input range. The  
NX2710 controller is optimized to convert single sup-  
ply up to 24V bus voltage to as low as 0.8V output  
voltage. Internal UVLO keeps the regulator off until the  
supply voltage exceeds 9V where internal digital soft  
starts get initiated to ramp up output. The NX2710 em-  
ploys programmable current limiting and FB UVLO  
followed by HICCUP feature. Other features include:  
5V gate drive, Programmable frequency from 300kHz  
to 1MHz, Adaptive deadband control, Internal digital  
soft start; Vcc under voltage lockout and shutdown ca-  
pability via comp pin.  
Excellent dynamic response with input voltage  
feed-forward and voltage mode control  
Programmable switching frequency up to 1MHz  
Internal Digital Soft Start Function  
Programmable hiccup current limit  
Shutdown by pulling COMP pin low  
NMOS LDO controller available  
n
n
n
n
n
n
n
Start into precharged output  
Pb-free and RoHS compAlianPt PLICATIONS  
n
n
n
Notebook PC  
Graphic Card on board converters  
On board DC to DC such as  
12V to 3.3V, 2.5V or 1.8V  
Set Top Box and LCD Display  
n
TYPICAL APPLICATION  
DO3316P-102  
VIN1  
+12V  
MBR0530T1  
1
2*16SVP330M  
8
VIN  
BST  
1uF  
0.1uF  
1ohm  
2
Q1  
HDRV  
0.75uH  
VOUT1  
16  
12  
9
SW  
REGCS  
+1.2V@25A  
8.06k  
OCP  
3.3nF  
1.2k  
2*(560uF,7mohm)  
4
3
7.5k  
LDRV  
GND  
Q2  
10  
13  
REGOUT  
VCC  
+5V  
14  
15  
Fb  
10uF  
1uF  
2.5k  
15nF  
Comp  
15k  
5k  
680pF  
VIN2  
+3.3V  
11  
5
REGFB  
RT  
1.65k  
6
7
MTD3055  
LDO OUT  
LDO FB  
0
82pF  
5k  
VOUT2  
+1.6V@2A  
5k  
150uF  
18mohm  
Figure1 - Typical application of NX2710  
ORDERING INFORMATION  
Device  
NX2710CSTR  
Temperature  
0 to 70o C  
Package  
SOIC -16L  
Frequency  
300kHz to 1MHz  
Pb-Free  
Yes  
Rev. 1.3  
08/07/07  
1
NX2710  
ABSOLUTE MAXIMUM RATINGS  
VCC to GND & BST to SW voltage ...................... -0.3V to 6.5V  
VIN to GND .......................................................... -0.3V to 25V  
BST, HDRV, REGCS to GND Voltage .................. -0.3V to 35V  
SW to GND ......................................................... -2V to 35V  
REGOUT to GND ................................................. 0.2 to 16V  
All other pins ....................................................... -0.3V to 6.5V  
Storage Temperature Range ................................. -65oC to 150oC  
Operating Junction Temperature Range ................ -40oC to 125oC  
ESD Susceptibility .............................................. 2kV  
CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent  
damage to the device. This is a stress only rating and operation of the device at these or any other conditions  
above those indicated in the operational sections of this specification is not implied.  
PACKAGE INFORMATION  
16-LEAD PLASTIC SOIC  
qJA » 83oC/W  
1
2
3
4
16  
15  
BST  
HDRV  
GND  
SW  
COMP  
14 FB  
13  
12  
11  
10  
9
VCC  
LDRV  
RT 5  
OCP  
LDO-OUT  
6
REGSEN  
REGOUT  
REGCS  
LDO-FB 7  
VIN  
8
ELECTRICAL SPECIFICATIONS  
Unless otherwise specified, these specifications apply over Vcc =5V, VIN=12V and TA = 0 to 70oC. Typical  
values refer to TA = 25oC.  
PARAMETER  
Reference Voltage  
Ref Voltage  
SYM  
Test Condition  
Min  
TYP  
MAX Units  
VREF  
0.8  
0.2  
V
Ref Voltage line regulation  
Supply Voltage(Vcc)  
VCC Voltage Range  
Operating quiescent current  
Vcc UVLO  
%
VCC  
IQ  
V
4.75  
5.25  
5
switching is off  
3
mA  
VCC-Threshold  
VCC_UVLO VCC Rising  
VCC_Hyst VCC Falling  
4.4  
0.2  
V
V
VCC-Hysteresis  
Supply Voltage(Vin)  
Vin Voltage Range  
Vin  
V
9
25  
10  
Input Voltage Current  
Vin=24V  
9
mA  
Rev. 1.3  
08/07/07  
2
NX2710  
PARAMETER  
Vin UVLO  
SYM  
Test Condition  
Min  
TYP  
MAX Units  
Vin-Threshold  
Vin_UVLO Vin Rising  
Vin_Hyst Vin Falling  
8.8  
0.8  
V
V
Vin-Hysteresis  
Oscillator (Rt)  
Frequency  
FS  
RT=open  
Vin=20V  
300  
KHz  
Frequency Over Vin  
Ramp-Amplitude Voltage  
Ramp Offset  
%
V
-5  
5
VRAMP  
2
0.8  
0.1  
90  
V
Ramp/Vin Gain  
Max Duty Cycle  
Min on time  
V/V  
%
nS  
150  
100  
Error Amplifiers  
Transconductance  
Input Bias Current  
Comp SD threshold  
Vref and Soft Start  
Soft Start time  
2500  
0.3  
umho  
nA  
Ib  
V
Tss  
Fs=300kHz  
6.8  
mS  
High Side Driver  
(CL=3300pF)  
Output Impedance , Sourcing Rsource(Hdrv)  
Current  
I=200mA  
1
ohm  
ohm  
Output Impedance , Sinking  
Current  
Rsink(Hdrv)  
I=200mA  
0.8  
Rise Time  
THdrv(Rise)  
THdrv(Fall)  
10% to 90%  
90% to 10%  
50  
50  
30  
ns  
ns  
ns  
Fall Time  
Deadband Time  
Tdead(L to Ldrv going Low to Hdrv going  
H)  
High, 10% to 10%  
LowNSide Driver  
(CL=3300pF)  
Output Impedance, Sourcing Rsource(Ldrv)  
Current  
I=200mA  
I=200mA  
1
ohm  
ohm  
Output Impedance, Sinking  
Current  
Rsink(Ldrv)  
0.5  
Rise Time  
TLdrv(Rise)  
TLdrv(Fall)  
10% to 90%  
90% to 10%  
50  
50  
30  
ns  
ns  
ns  
Fall Time  
Deadband Time  
Tdead(H to SW going Low to Ldrv going  
L) High, 10% to 10%  
OCP Adjust  
OCP current setting  
FBUVLO  
32  
70  
uA  
%
Feedback UVLO threshold  
percent of nominal  
65  
75  
Over temperature  
Threshold  
150  
20  
°C  
°C  
Hysteresis  
Rev. 1.3  
08/07/07  
3
NX2710  
PARAMETER  
LDO Controller  
SYM  
Test Condition  
Min  
TYP  
MAX Units  
FB Pin- Bias Current  
LDO FB Voltage  
LDO FB UVLO  
100  
75  
nA  
V
%
V
LDO_OUT=LDO_FB  
percent of nominal  
VIN=12V, LDO_FB=0.7V  
IO_SOURCE=1.4mA  
0.8  
70  
10.2  
65  
High Output Voltage  
Low Output Voltage  
VIN=12V, LDO_FB=0.9V  
IO_SINK=1.4mA  
0.2  
3
V
High Output Source Current  
5V AUX REG  
mA  
Current limit threshold  
FB Pin- Bias Current  
RegFb Voltage  
100  
0
1.25  
11  
mV  
uA  
V
Regout=RegFb  
VIN=12V,  
Regout Output Voltage High  
RegFb=1.1V  
V
IO_SOURCE=1.4mA  
Regout Output Voltage Low  
Open Loop Gain  
VIN=12V,  
IO_SINK=1.4mA  
RegFb=1.4V  
0.2  
V
GBNT(Note1)  
50  
DB  
Note 1: This parameter is guaranteed by design but not tested in production(GBNT).  
Rev. 1.3  
08/07/07  
4
NX2710  
PIN DESCRIPTIONS  
PIN SYMBOL  
PIN DESCRIPTION  
This pin supplies the internal 5V bias circuit. . A high freq 1uF ceramic capacitor is placed  
as close as possible to and connected to this pin and ground pin.  
VCC  
This pin supplies voltage to high side FET driver. A high freq minimum 0.1uF ceramic  
capacitor is placed as close as possible to and connected to this pin and SW pin.  
BST  
GND  
Power ground.  
This pin is the error amplifiers inverting input. This pin is connected via resistor divider to  
the output of the switching regulator to set the output DC voltage.  
FB  
This pin is the output of the error amplifier and together with FB pin is used to compensate  
the voltage control feedback loop.  
COMP  
SW  
This pin is connected to source of high side FETs and provide return path for the high  
side driver.  
High side gate driver output.  
Low side gate driver output.  
HDRV  
LDRV  
VIN  
Bus voltage input provides power supply to oscillator, VIN UVLO signal and 5V regulator  
controller.  
RT  
Oscillator's frequency can be set by using an external resistor from this pin to GND.  
LDO controller feedback input. If the LDOFB pin is pulled below 0.7*Vref, an internal  
comparator after certain delay and pulls down LDOOUT pin and initiates the HICCUP  
circuitry.  
LDO FB  
LDO OUT  
LDO controller output. This pin is controlling the gate of an external NCH MOSFET. The  
maximum rating of this pin is 16V.  
This pin is 5V regulator current limit pin. It compares the voltage drop on the resistor  
which is connected between Vin and REGCS pin with internal offset 100mV. 1ohm  
resistor sets the current limit 100mA.  
REGCS  
The output of the 5V regulator controller that drives a low current low cost external  
bipolar transistor or an external MOSFET to regulate the voltage at Vcc pin derived from  
bus voltage. This eliminates an otherwise external regulator needed in applications where  
5V is not available.  
REGOUT  
REGSEN  
OCP  
Feedback pin of the 5V regulator controller. A resistor divider is connected from the  
output of the 5V regulator to this pin to complete the loop.  
This pin is connected to the drain of the external low side MOSFET and is the input of the  
over current protection(OCP) comparator. An internal current source is flown to the  
external resistor which sets the OCP voltage across the Rdson of the low side MOSFET.  
Current limit point is this voltage divided by the Rds-on.  
Rev. 1.3  
08/07/07  
5
NX2710  
BLOCK DIAGRAM  
RegCs  
VIN  
Regout  
Ref  
EN  
100mV  
Regsen  
BST  
4.4/4.2  
1.25V  
Bias  
Generator  
VCC  
POR  
0.8V  
START  
6/5.75  
COMP  
START  
LDIN  
three  
cycle  
delay  
Reset dominant  
Hiccup  
START  
DrvH  
SW  
0.3V  
R
Q
S
FET Drivers  
VCC  
VIN  
START  
SS_1/4_done  
Dis_EA  
HDin  
OSC  
Digital  
start Up  
DRVL  
SS_half_done  
Disable  
RT  
S
R
Q
SS_done  
70%*Vp  
FB  
3 cycle  
filter  
Vp  
HDIN  
Vp  
POR  
R
Hiccup  
3 cycle  
filter  
FB  
Hiccup logic  
OCP  
0.6V  
CLAMP  
32uA  
LDIN  
START  
VCC  
COMP  
GND  
Dis_EA  
EN  
0.6V  
70%*Vp  
SS_1/4_done  
3 cycle  
filter  
VpLDO  
Vp  
LDO_out  
LDO_FB  
Figure 2 - Simplified block diagram of the NX2710  
Rev. 1.3  
08/07/07  
6
NX2710  
DO3316P-102  
16MV1500WG  
VIN1  
+12V  
2 *  
10uF  
MBR0530T1  
1
8
VIN  
BST  
1uF  
0.1uF  
2
1ohm  
Q1  
Q2  
HDRV  
0.75uH  
VOUT1  
16  
12  
9
SW  
REGCS  
+1.2V@25A  
6k  
OCP  
3.3nF  
7.5k  
2*(560uF,7mohm)  
4
3
5k  
LDRV  
GND  
10  
13  
2N3904  
1uF  
REGOUT  
VCC  
1.2k  
10  
1uF  
+5V  
14  
15  
Fb  
2.5k  
15nF  
Comp  
15k  
5k  
680pF  
VIN2  
+3.3V  
11  
5
REGFB  
100uF  
1.65k  
6
7
MTD3055  
LDO OUT  
LDO FB  
RT  
150pF  
VOUT2  
+2.5V@2A  
1k  
220uF  
39mohm  
470  
Figure 3 - Simplified Demo board schematic  
Rev. 1.3  
08/07/07  
7
NX2710  
BUS  
R23  
12V  
1
0
C18  
47u  
R24  
GND  
J1  
1
0
1
2
3.3V  
3.3V  
3.3V  
1
2
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
3.3V1  
3.3V  
-12V  
L3  
DO3316H-102  
3.3V2  
GND  
C20  
VCC  
R29  
1
3
J2  
GND3  
PS_ON  
GND4  
GND5  
GND6  
-5V  
C25  
0.1u  
R5  
1k  
op  
5V  
5V  
12V  
12V  
4
1
2
4
3
5V1  
GND1  
GND2  
12V1  
12V2  
C21  
D1  
5
C12  
C11  
GND1  
5V  
MBR0530T1  
1u  
16MV1500WG  
6
ATX-12V  
R22  
0
7
open  
C9  
GND2  
PWR_OK  
5VSB  
12V1  
U1  
8
C10  
10u  
9
1
2
REG_CS  
BST  
5V  
5V  
9
5V2  
10u  
Q1  
MBR3904  
12V  
10  
5V3  
R25  
R12  
UG1  
M6  
op  
10  
M1  
NTD70N03R  
REG_OUT  
HDRV  
ATX con  
JVOUT  
4.99k  
0
1
R26  
op  
R34  
op  
NTD70N03R  
M2  
R13  
UG2  
C17  
0.1u  
0
C7  
op  
SW  
C2  
0.1u  
D5  
op  
R27  
5k  
L1  
VCC  
11  
1
2
2
REG_SENSE  
4SEPC560MX 4SEPC560MX op  
VOUT  
PG0077.801  
SW  
VOUT  
C26  
1u  
16  
12  
SW  
R28  
1.65k  
L2  
1
D2  
D3  
D4  
C14  
C15  
C19  
R4  
OP  
R18  
1k  
OCP  
6k  
GNDOUT  
R14  
3.3V  
LG1  
LG2  
LG3  
M3  
NTD110N02R  
R1  
10  
13  
VCC  
0
C1  
1u  
R15  
M4  
R17 NTD110N02R  
10  
LDO_IN  
JP1  
2
0
VDD  
C22  
R16  
100u  
M7  
4
M5  
NTD110N02R  
LDRV  
0
VOUT  
6
C13  
470p  
LDO_OUT  
MTD3055  
M11  
M12  
UG1  
UG2  
SW  
LDO_OUT  
GNDLDO  
4
4
LDO_OUT  
panasonic FM 220uF  
R31  
0
JLDO  
C23  
1
R33  
1k  
C8  
150p  
R20  
7.5k  
14  
15  
FB  
7
5
C3  
op  
C24  
0.1u  
LDO_FB  
RT  
C16  
3.3n  
R19  
1.2k  
C4  
R2  
R32  
474  
COMP  
2.5k  
15n  
SW  
R30  
op  
R3  
open  
R21  
15k  
C5  
680p  
M13  
M14  
M15  
LG1  
LG2  
LG3  
4
4
4
C6  
open  
Title  
Size  
NX2710 HC APPLICATION  
Document Number  
Rev  
2710-SO-02A  
A
Date:  
Thursday , September 14, 2006  
Sheet  
1
of  
1
Figure 4 - Demo board schematic based on ORCAD  
Rev. 1.3  
08/07/07  
8
NX2710  
Bill of Materials  
Item  
Quantity  
Reference  
Part  
1
2
3
4
5
6
7
8
3 C1,C21,C26  
4 C2,C17,C24,C25  
1 C4  
1 C5  
1 C8  
2 C9,C10  
1 C11  
1 C13  
1u  
0.1u  
15n  
680p  
150p  
10u  
16MV1500WG  
470p  
9
2 C14,C15  
1 C16  
4SEPC560MX  
3.3n  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
1 C18  
1 C22  
1 C23  
1 D1  
1 L1  
1 L3  
2 M1,M2  
3 M3,M4,M5  
1 M7  
47u  
100u  
panasonic FM 220uF  
MBR0530T1  
PG0077.801  
DO3316H-102  
NTD70N03R  
NTD110N02R  
MTD3055  
MBR3904  
10  
2.5k  
6k  
1k  
0
1 Q1  
2 R1,R17  
1 R2  
1 R4  
3 R5,R18,R33  
9 R12,R13,R14,R15,R16,R22,  
R23,R24,R31  
1 R19  
1 R20  
1 R21  
1 R25  
1 R27  
1 R28  
1 R29  
1.2k  
7.5k  
15k  
4.99k  
5k  
1.65k  
1
474  
28  
29  
30  
31  
32  
33  
34  
1 R32  
1 U1  
NX2710  
Rev. 1.3  
08/07/07  
9
NX2710  
Demoboard waveforms  
Figure 6 - Transient response @ 1.2 output  
Figure 5 - Output ripple  
Figure 7 - Transient response @ LDO  
Figure 8 - Soft start  
Figure 9 - 1.2V over current proteciton  
Figure 10 - LDO over current protection  
Rev. 1.3  
08/07/07  
10  
NX2710  
APPLICATION INFORMATION  
V -VOUT VOUT  
1
IN  
IRIPPLE  
=
´
´
´
LOUT  
V
F
S
IN  
...(2)  
Symbol Used In Application Information:  
12V-1.2V 1.2V  
1
=
´
= 4.8A  
0.75uH  
12V 300kHz  
VIN  
- Input voltage  
- Output voltage  
- Output current  
VOUT  
IOUT  
Output Capacitor Selection  
VRIPPLE - Output voltage ripple  
Output capacitor is basically decided by the  
amount of the output voltage ripple allowed during  
steady state(DC) load condition as well as specifica-  
tion for the load transient. The optimum design may  
require a couple of iterations to satisfy both condition.  
Based on DC Load Condition  
FS  
- Switching frequency  
- Inductor current ripple  
IRIPPLE  
Design Example  
Power stage design requirements:  
VIN=12V  
The amount of voltage ripple during the DC load  
condition is determined by equation(3).  
VOUT=1.2V  
DIRIPPLE  
IOUT =25A  
DVRIPPLE = ESR´ DIRIPPLE  
+
...(3)  
8´ F ´ COUT  
VRIPPLE <=20mV  
VTRAN<=60mV @ 10A step  
FS=300kHz  
S
Where ESR is the output capacitors' equivalent  
series resistance,COUT is the value of output capaci-  
tors.  
Typically when large value capacitors are selected  
such as Aluminum Electrolytic,POSCAP and OSCON  
types are used, the amount of the output voltage ripple  
is dominated by the first term in equation(3) and the  
second term can be neglected.  
Output Inductor Selection  
The selection of inductor value is based on in-  
ductor ripple current, power rating, working frequency  
and efficiency. Larger inductor value normally means  
smaller ripple current. However if the inductance is  
chosen too large, it brings slow response and lower  
efficiency. Usually the ripple current ranges from 20%  
to 40% of the output current. This is a design freedom  
which can be decided by design engineer according to  
various application requirements. The inductor value  
can be calculated by using the following equations:  
For this example, OSCON are chosen as output  
capacitors, the ESR and inductor current typically de-  
termines the output voltage ripple.  
DVRIPPLE  
DIRIPPLE  
15mV  
4.8A  
ESRdesire  
=
=
= 4.2mW  
...(4)  
If low ESR is required, for most applications, mul-  
tiple capacitors in parallel are better than a big capaci-  
tor. For example, for 15mV output ripple, OSCON  
4SEPC560MX with 7mW are chosen.  
V -VOUT VOUT  
1
IN  
LOUT  
=
´
´
IRIPPLE  
V
F
S
IN  
...(1)  
IRIPPLE =k ´ IOUTPUT  
E S R E ´ DIR IPPLE  
N =  
where k is between 0.2 to 0.4.  
Select k=0.2, then  
...(5)  
D VR IPPLE  
12V-1.2V 1.2V  
1
Number of Capacitor is calculated as  
LOUT  
=
´
´
0.2´ 25A 12V 300kHz  
LOUT =0.72uH  
7m4.8A  
N =  
20mV  
Choose LOUT=0.75uH, then Pulse inductor  
PG0077.801 is a good choice.  
N =1.68  
The number of capacitor has to be round up to a  
integer. Choose N =2.  
Current Ripple is calculated as  
Rev. 1.3  
08/07/07  
11  
NX2710  
If ceramic capacitors are chosen as output ca-  
pacitors, both terms in equation (3) need to be evalu-  
ated to determine the overall ripple. Usually when this  
type of capacitors are selected, the amount of capaci-  
tance per single unit is not sufficient to meet the tran-  
sient specification, which results in parallel configura-  
output inductor is smaller than the critical inductance,  
the voltage droop or overshoot is only dependent on  
the ESR of output capacitor. For low frequency ca-  
pacitor such as electrolytic capacitor, the product of  
ESR and capacitance is high and L £ Lcrit is true. In  
that case, the transient spec is mostly like to depen-  
dent on the ESR of capacitor.  
tion of multiple capacitors. The amount of ceramic  
capacitor output ripple is :  
Most case, the output capacitor is multiple ca-  
pacitor in parallel. The number of capacitor can be cal-  
culated by the following  
DIRIPPLE  
DVRIPPLE = ESR´ DIRIPPLE  
+
8´ 300kHz´ COUT  
Using the above equations, although DC ripple  
spec can be met, however it needs to be studied for  
ESRE ´ DIstep  
VOUT  
N =  
where  
+
´ t 2  
...(9)  
DV  
2´ L´ CE ´ DV  
tran  
tran  
transient requirement.  
Based On Transient Requirement  
Typically, the output voltage droop during tran-  
sient is specified as  
0
if L £ Lcrit  
ì
ï
L´ DI  
t =  
í
ï
î
step  
...(10)  
- ESRE ´ CE  
if L ³ Lcrit  
VOUT  
DV  
< DV  
@step load I  
tran  
droop  
STEP  
During the transient, the voltage droop during  
the transient is composed of two sections. One sec-  
tion is dependent on the ESR of capacitor, the other  
section is  
For example, assume voltage droop during tran-  
sient is 60mV for 10A load step.  
If the OSCON 4SEPC560MX(560uF, 7mohm  
ESR) is used, the crticial inductance is given as  
a function of the inductor, output capacitance as well  
as input, output voltage. For example, for the  
overshoot when load from high load to light load  
with a ISTEP transient load, if assuming the band-  
width of system is high enough, the overshoot can  
be estimated as the following equation.  
ESRE ´ CE ´ VOUT  
Lcrit  
=
=
DIstep  
7m560mF´ 1.2V  
= 0.94mH  
5A  
The selected inductor is 0.75uH which is smaller  
than critical inductance. In that case, the output volt-  
age transient mainly dependent on the ESR.  
VOUT  
DVovershoot = ESR ´ DIstep  
+
´ t 2  
...(6)  
2´ L´ COUT  
number of capacitor is  
where  
is the a function of capacitor,etc.  
t
ESRE ´ DIstep  
N =  
0
if L £ Lcrit  
ì
ï
DV  
L´ DI  
t =  
í
ï
î
tran  
step  
...(7)  
...(8)  
- ESR ´ COUT  
if L ³ Lcrit  
7m5A  
VOUT  
=
60mV  
where  
ESR ´ COUT ´ VOUT ESRE ´ CE ´ VOUT  
=1.296  
The number of capacitors has to satisfied both  
Lcrit  
=
=
DIstep  
DIstep  
ripple and transient requirement. Overall, we choose  
N=2.  
where ESRE and CE represents ESR and capaci-  
tance of each capacitor if multiple capacitors are used  
in parallel.  
The above equation shows that if the selected  
Rev. 1.3  
08/07/07  
12  
NX2710  
It should be considered that the proposed equa- following figures and equations show how to realize  
tion is based on ideal case, in reality, the droop or over- the type III compensator by transconductance ampli-  
shoot is typically more than the calculation. The equa- fier.  
tion gives a good start. For more margin, more ca-  
1
pacitors have to be chosen after the test. Typically, for  
high frequency capacitor such as high quality POSCAP  
especially ceramic capacitor, 20% to 100% (for ce-  
ramic) more capacitors have to be chosen since the  
ESR of capacitors is so low that the PCB parasitic can  
affect the results tremendously. More capacitors have  
to be selected to compensate these parasitic param-  
eters.  
FZ1  
FZ2  
=
=
=
=
...(11)  
...(12)  
...(13)  
...(14)  
2´ p ´ R4 ´ C2  
1
2´ p ´ (R2 + R3 )´ C3  
1
F
P1  
2´ p ´ R3 ´ C3  
1
F
P2  
C1 ´ C2  
2´ p ´ R4 ´  
C1 + C2  
Compensator Design  
where FZ1,FZ2,FP1 and FP2 are poles and zeros in  
the compensator.  
Due to the double pole generated by LC filter of  
the power stage, the power system has 180o phase  
shift , and therefore, is unstable by itself. In order to  
achieve accurate output voltage and fast transient re-  
sponse, compensator is employed to provide highest  
possible bandwidth and enough phase margin. Ideally,  
the Bode plot of the closed loop system has crossover  
frequency between 1/10 and 1/5 of the switching fre-  
quency, phase margin greater than 50o and the gain  
crossing 0dB with -20dB/decade. Power stage output  
capacitors usually decide the compensator type. If  
electrolytic capacitors are chosen as output capacitors,  
type II compensator can be used to compensate the  
system, because the zero caused by output capacitor  
ESR is lower than crossover frequency. Otherwise type  
III compensator should be chosen.  
The transfer function of type III compensator for  
transconductance amplifier is given by:  
Ve  
1- gm ´ Zf  
=
VOUT  
1+ gm ´ Zin + Zin /R1  
For the voltage amplifier, the transfer function of  
compensator is  
Ve  
- Zf  
=
VOUT  
Zin  
To achieve the same effect as voltage amplifier,  
the compensator of transconductance amplifier must  
satisfy this condition: R4>>2/gm. And it would be de-  
sirable if R1||R2||R3>>1/gm can be met at the same  
time,  
Voltage feedforward compensation is used in  
NX2710 to compensate the output voltage variation  
caused by input voltage changing. The feedforward  
funtion is realized by using VIN pin voltage to program  
the oscillator ramp voltage VOSC=0.1VIN, which pro-  
vides nearly constant power stage gain under wide volt-  
age input range.  
Zf  
Vout  
Zin  
C1  
R3  
C2  
R4  
R2  
R1  
C3  
Fb  
Ve  
gm  
A. Type III compensator design  
For low ESR output capacitors, typically such as  
Sanyo oscap and poscap, the frequency of ESR zero  
caused by output capacitors is higher than the cross-  
over frequency. In this case, it is necessary to com-  
pensate the system with type III compensator. The  
Vref  
Figure 11 - Type III compensator using  
transconductance amplifier  
Rev. 1.3  
08/07/07  
13  
NX2710  
3. Calculate C2 with zero Fz1 at 75% of the LC  
double pole by equation (11).  
Case 1:  
FLC<FO<FESR(for most ceramic or low  
ESR POSCAP, OSCON)  
1
C2 =  
2´ p ´ FZ1 ´ R4  
1
power stage  
=
2´ p ´ 0.75 ´ 5.5kHz ´ 2.5kW  
= 15nF  
LC  
F
40dB/decade  
Choose C2=15nF.  
4. Calculate C1 by equation (14) with pole Fp2 at  
one third of the switching frequency.  
loop gain  
1
ESR  
C1 »  
F
2´ p ´ R4 ´ FP2  
1
20dB/decade  
»
2 ´ p ´ 2.5k100kHz  
» 639pF  
compensator  
Choose C1=680pF.  
5. Calculate C3 with the crossover frequency FO  
at 15kHz.  
FZ1  
FO  
FP2  
FZ2  
F
P1  
VOSC 2´ p ´ F ´ L´ COUT  
O
C3=  
=
´
V
R4  
IN  
1
2´ p ´ 15kHz´ 0.75uH´ 1120uF  
2.5kW  
´
Figure 12 - Bode plot of Type III compensator  
(FLC<FO<FESR  
10  
)
=3.2nF  
Choose C3=3.3nF.  
Typical design example of type III compensator  
in which the crossover frequency is selected as  
FLC<FO<FESR and FO<=1/10Fs is shown as the following  
steps.  
6. Calculate R3 by equation (13) with Fp1 =FESR  
.
1
R3 =  
2´ p ´ F ´ C3  
P1  
1
1. Calculate the location of LC double pole FLC  
=
2´ p ´ 40.6kHz´ 3.3nF  
and ESR zero FESR  
.
=1.18kW  
Choose R3 =1.2kW.  
1
F =  
LC  
7. Calculate R2 by setting compensator zero  
FZ2 at the LC double pole.  
2´ p ´ LOUT ´ COUT  
1
=
2´ p ´ 0.75uH´ 1120uF  
1
1
1
R2 =  
´ (  
-
)
= 5.5kHz  
2´ p ´ C3 FZ2  
F
P1  
1
1
1
1
F
=
=
´ (  
-
)
ESR  
2´ p ´ ESR´ COUT  
2´ p ´ 3.3nF 5.5kHz 40.6kHz  
= 7.6kW  
1
=
2´ p ´ 3.5m1120uF  
Choose R2 =7.5kW.  
8. Calculate R1 .  
= 40.6kHz  
2. Set R4 equal to 2.5kW.  
Rev. 1.3  
08/07/07  
14  
NX2710  
R2 ´ VREF  
7.5k0.8V  
1
R1=  
=
= 15kW  
FLC<FESR<FO(for electrolytic capacitors)  
power stage  
F
=
=
LC  
VOUT -VREF  
1.2V-0.8V  
2´ p ´  
L
OUT ´ COUT  
Choose R1=15kW.  
1
2´ p ´ 2.2uH´ 2000uF  
Case 2:  
= 2.4kHz  
1
F
=
ESR  
2´ p ´ ESR ´ COUT  
1
=
LC  
F
2´ p ´ 9m2000uF  
= 8.8kHz  
40dB/decade  
2. Set R4 equal to 2.5kW.  
3. Calculate C2 with zero Fz1 at 75% of the LC  
double pole by equation (11).  
ESR  
F
loop gain  
1
C2 =  
2 ´ p ´ FZ1 ´ R4  
20dB/decade  
1
=
2´ p ´ 0.75 ´ 2.4kHz ´ 2.5kW  
= 35nF  
compensator  
Choose C2=33nF.  
4. Calculate C1 by equation (14) with pole Fp2 at  
one third of the switching frequency.  
FZ1  
FO  
FP2  
FZ2  
F
P1  
1
C1 »  
2´ p ´ R4 ´ F  
P2  
1
»
Figure 13 - Bode plot of Type III compensator  
(FLC<FESR<FO)  
2´ p ´ 2.5k66.7kHz  
» 959pF  
Choose C1=1nF.  
If electrolytic capacitors are used as output  
capacitors, typical design example of type III  
compensator in which the crossover frequency is  
selected as FLC<FESR<FO and FO<=1/10Fs is shown as  
the following steps. Here two SANYO MV-WF1000 with  
18 mW is chosen as output capacitor, output inductor  
is 2.2uH, output voltage is 1.2V, switching frequency  
is 200kHz.  
5. Calculate R3 with the crossover frequency FO at  
15kHz.  
V
ESR´ R4  
IN  
R3 =  
´
VOSC 2´ p ´ FO ´ L  
9mohm´ 2.5kW  
=10´  
2´ p ´ 15kHz´ 1uH  
=1.08kW  
1. Calculate the location of LC double pole FLC  
Choose R3=1.2kW.  
and ESR zero FESR  
.
6. Calculate C3 by equation (13) with Fp1 =FESR  
.
Rev. 1.3  
08/07/07  
15  
NX2710  
1
power stage  
loop gain  
C3 =  
2´ p ´ F ´ R3  
P1  
40dB/decade  
1
=
2´ p ´ 8.8kHz´ 1.2kW  
= 14nF  
Choose C3 =15nF.  
20dB/decade  
7. Calculate R2 by setting compensator zero  
FZ2 at the LC double pole.  
1
1
1
R2 =  
´ (  
-
)
compensator  
2 ´ p ´ C3  
1
FZ2 FP1  
1
2.4kHz 8.8kHz  
Gain  
1
=
´ (  
-
)
2 ´ p ´ 15nF  
= 3.2kW  
F
F
P
F
Z
LCFESR  
FO  
Choose R2 =4kW.  
8. Calculate R1 .  
R2 ´ VREF  
7.5k0.8V  
Figure 14 - Bode plot of Type II compensator  
Vout  
R1=  
=
= 15kW  
VOUT -VREF  
1.2V-0.8V  
Choose R1=15kW.  
R2  
B. Type II compensator design  
Fb  
Ve  
If the electrolytic capacitors are chosen as power  
stage output capacitors, usually the Type II compensa-  
tor can be used to compensate the system.  
gm  
R1  
R3  
Vref  
C2  
C1  
For this type of compensator, FO need to  
satisfy FLC<FESR<<FO<=1/10Fs.  
Type II compensator can also be realized by  
simple RC circuit without feedback as shown in the  
following figure. R3 and C1 introduce a zero to cancel  
the double pole effect. C2 introduces a pole to sup-  
press the switching noise. The following equations show  
the compensator pole zero location and constant gain.  
Figure 15 - Type II compensator with  
transconductance amplifier  
The following is parameters for type II compen-  
sator design. Input voltage is 12V, output voltage is  
2.5V, output inductor is 2.2uH, output capacitors are  
two680uFwith41mW electrolytic capacitors.  
R1  
Gain=gm ´  
´ R3  
... (15)  
... (16)  
... (17)  
R1+R2  
1
F =  
z
1.Calculate the location of LC double pole FLC  
2´ p ´ R3 ´ C1  
and ESR zero FESR  
.
1
F »  
p
2´ p ´ R3 ´ C2  
1
F
=
LC  
2´ p ´  
L
OUT ´ COUT  
1
=
2´ p ´ 2.2uH´ 1360uF  
= 2.9kHz  
Rev. 1.3  
08/07/07  
16  
NX2710  
The following equation applies to figure16, which  
shows the relationship between VOUT , VREF and volt-  
age divider.  
1
F
=
=
ESR  
2´ p ´ ESR´ COUT  
1
2´ p ´ 20.5m1360uF  
Vout  
= 5.7kHz  
2.Set R2 equal to10kW. Using equation 18, the  
final selection of R1 is 4.7kW.  
R2  
Fb  
3. Set crossover frequency at 1/10 of the  
swithing frequency, here FO=30kHz.  
R1  
4.Calculate R3 value by the following equation.  
Vref  
VOSC 2 ´ p ´ FO ´ L  
VOUT  
1
R3 =  
´
´
´
V
RESR  
gm VREF  
in  
Figure 16 - Voltage Divider  
2´ p ´ 30kHz´ 2.2uH  
1
=0.1´  
´
20.5mW  
2.5V  
2.5mA/V  
R 2 ´ VREF  
´
R1=  
0.8V  
=2.53kW  
...(18)  
VOUT -VREF  
where R2 is part of the compensator, and the value  
of R1 value can be set by voltage divider.  
Choose R3 =2.55kW.  
5. Calculate C1 by setting compensator zero FZ  
at 75% of the LC double pole.  
Input Capacitor Selection  
Input capacitors are usually a mix of high fre-  
quency ceramic capacitors and bulk capacitors. Ce-  
ramic capacitors bypass the high frequency noise, and  
bulk capacitors supply switching current to the  
MOSFETs. Usually 1uF ceramic capacitor is chosen  
to decouple the high frequency noise.The bulk input  
capacitors are decided by voltage rating and RMS cur-  
rent rating. The RMS current in the input capacitors  
1
C1=  
2´ p ´ R3 ´ F  
z
1
=
2´ p ´ 2.55k0.75´ 2.9kHz  
=28nF  
Choose C1=27nF.  
F
6. Calculate C2 by setting compensator pole  
at half the swithing frequency.  
p
can be calculated  
as:  
1
C 2 =  
p ´ R 3 ´ Fs  
IRMS = IOUT ´ D ´ 1-D  
1
VOUT  
=
D =  
p ´ 2 .55k W ´ 3 0 0 k H z  
= 2 0 7 p F  
V
IN  
...(19)  
VIN = 12V, VOUT=1.2V, IOUT=25A, the result of input  
RMS current is 7.5A.  
Choose C2=220pF.  
For higher efficiency, low ESR capacitors are  
recommended. Two Sanyo OS-CON 16SVP330M  
16V330uF 16mW with 4.72A RMS rating are chosen  
as input capacitors.  
Output Voltage Calculation  
Output voltage is set by reference voltage and  
external voltage divider. The reference voltage is fixed  
at 0.8V. The divider consists of two ratioed resistors  
so that the output voltage applied at the Fb pin is 0.8V  
when the output voltage is at the desired value.  
Rev. 1.3  
08/07/07  
17  
NX2710  
charge,VHGS is the high side gate source voltage, and  
Power MOSFETs Selection  
VLGS is the low side gate source voltage.  
This power dissipation should not exceed maxi-  
mum power dissipation of the driver device.  
The NX2710 requires at least two N-Channel  
power MOSFETs. The selection of MOSFETs is based  
on maximum drain source voltage, gate source volt-  
age, maximum current rating, MOSFET on resistance  
and power dissipation. The main consideration is the  
power loss contribution of MOSFETs to the overall con-  
verter efficiency. In 25A output application, five  
IRFR3706 can be used, two for high side, three for low  
side. They have the following parameters: VDS=30V, ID  
=75A,RDSON =9mW,QGATE =23nC.  
Over Current Limit Protection  
Over current protection is achieved by sensing  
current through the low side MOSFET. An internal cur-  
rent source of 32uA flows through an external resistor  
connected from OCP pin to SW node sets the over  
current protection threshold. When synchronous FET  
is on, the voltage at node SW is given as  
VSW =-IL ´ RDSON  
There are two factors causing the MOSFET  
power loss:conduction loss, switching loss.  
The voltage at pin OCP is given as  
Conduction loss is simply defined as:  
I
OCP ´ ROCP +VSW  
P
HCON =IOUT2 ´ D´ RDS(ON) ´ K  
LCON=IOUT2 ´ (1- D)´ RDS(ON) ´ K  
PTOTAL =P + P  
When the voltage is below zero, the over current  
occurss as shown in figure 17.  
P
...(20)  
HCON  
LCON  
vbus  
where the RDS(ON) will increases as MOSFET junc-  
tion temperature increases, K is RDS(ON) temperature  
dependency. As a result, RDS(ON) should be selected  
for the worst case, in which K approximately equals to  
1.4 at 125oC according to IRFR3706 datasheet. Con-  
duction loss should not exceed package rating or overall  
system thermal budget.  
I
OCP  
32uA  
OCP  
R
SW  
OCP  
OCP  
comparator  
Switching loss is mainly caused by crossover  
conduction at the switching transition. The total  
switching loss can be approximated.  
Figure 17 - Over Current Protection  
The over current limit can be set by the following  
equation:  
1
I
OCP ´ ROCP  
PSW  
=
´ V ´ IOUT ´ TSW ´ F  
IN S  
...(21)  
ISET  
=
2
K ´ RDSON  
where IOUT is output current, TSW is the sum of TR  
and TF which can be found in mosfet datasheet, and  
FS is switching frequency. Swithing loss PSW is fre-  
quency dependent.  
If two MOSFETs RDSON=6.5mW, the worst case  
thermal consideration K=1.5 and the current limit is  
set at 40A, then  
I
SET ´ K ´ RDSON 40A ´ 1.5´ 6.5mW  
ROCP  
=
=
= 6.1k W  
Also MOSFET gate driver loss should be consid-  
ered when choosing the proper power MOSFET.  
MOSFET gate driver loss is the loss generated by dis-  
charging the gate capacitor and is dissipated in driver  
circuits.It is proportional to frequency and is defined  
as:  
IOCP  
32uA ´ 2  
Choose ROCP=6kW.  
For NX2710, if switching channel goes into hic-  
cup current limit, the LDO will go to hiccup too.  
LDO Selection Guide  
NX2710 offers a LDO controller. The selection  
of MOSFET to meet LDO is more straight forward.  
The selection is that the Rdson of MOSFET should  
Pgate = (QHGATE ´ VHGS + QLGATE ´ VLGS )´ FS  
...(22)  
where QHGATE is the high side MOSFETs gate  
charge,QLGATE is the low side MOSFETs gate  
Rev. 1.3  
08/07/07  
18  
NX2710  
meet the dropout requirement. For example.  
gm is the forward trans-conductance of MOSFET.  
VLDOIN =3.3V  
For IRF3706, gm=53.  
VLDOOUT =2.5V  
Select Rf1=5kohm.  
ILoad =2A  
Output capacitor is Sanyo POSCAP 4TPE150M  
with 150uF, ESR=25mohm.  
The maximum Rdson of MOSFET should be  
RRDSON = (VLDOIN - VLDOOUT )´ ILOAD  
= (3.3V - 2.5V) / 2A = 0.4W  
1
53´ 25mW  
CC =  
´
=91pF  
4´ p ´ 100kHz ´ 5kW 1+53´ 25mW  
Most of MOSFETs can meet the requirement.  
Moreimportant is that MOSFET has to be selected right  
package to handle the thermal capability. For LDO,  
maximum power dissipation is given as  
Choose CC=100pF. For electrolytic or POSCAP,  
RC is typically selected to be zero.  
Rf2 is determined by the desired output voltage.  
Rf1 ´ VREF  
Rf2 =  
PLOSS = (VLDOIN - VLDOOUT )´ ILOAD  
= (3.3V - 2.5V)´ 2A =1.6W  
VLDOOUT - VREF  
5k0.8V  
=
Select IR MOSFET IRFR3706 with 9mW RDSON  
1.6V - 0.8V  
is sufficient.  
=5kW  
Choose Rf2=5kW.  
When ceramic capacitors or some low ESR bulk  
capacitors are chosen as LDO output capacitors, the  
zero caused by output capacitor ESR is so high that  
crossover frequency FO has to be chosen much higher  
than zero caused by RC and CC and much lower than  
zero caused by ESR . For example, 10uF ceramic is  
used as output capacitor. We select Fo=100kHz,  
Rf1=5kohm and select MOSFET MTD3055(gm=5S).  
RC and CC can be calculated as follows.  
LDO Compensation  
The diagram of LDO controller including VCC  
regulator is shown in the following figure.  
LDO input  
Vref  
R
f1  
ESR  
Co  
R
f2  
Rload  
Rc  
Cc  
2´ p ´ FO ´ CO  
RC =Rf1 ´  
0.5´ gm  
2´ p ´ 100kHz´ 10uF  
=5kW´  
0.5´ 5S  
Figure 18 - NX2710 LDO controller.  
=12.56kW  
Choose RC=12.7kW.  
For most low frequency capacitor such as elec-  
trolytic, POSCAP, OSCON, etc, the compensation pa-  
rameter can be calculated as follows.  
10´ CO  
CC =  
RC ´ gm  
10´ 10uF  
=
gm ´ ESR  
1
12.7k5S  
CC =  
´
4´ p ´ FO ´ Rf1 1+gm ´ ESR  
=1.6nF  
where FO is the desired crossover frequency.  
Typically, in this LDO compensation, crossover  
frequency FO has to be higher than zero caused by  
ESR. FO is typically around several tens kHz to a few  
hundred kHz. For this example, we select Fo=100kHz.  
Choose CC=1.5nF.  
Rev. 1.3  
08/07/07  
19  
NX2710  
enough. This is very important. The same applies to  
the output capacitors and input capacitors.  
6. Hdrv and Ldrv pins should be as close to  
MOSFET gate as possible. The gate traces should be  
wide and short. A place for gate drv resistors is needed  
to fine tune noise if needed.  
Current Limit for LDO  
Current limit of LDO is achieved by sensing the  
LDO feedback voltage. When LDO_FB pin is below  
70% of VREF, the IC goes into hiccup mode. The IC will  
turn off all the channel for 4096 cycles and start to  
restart system again.  
7. Vcc capacitor, BST capacitor or any other by-  
passing capacitor needs to be placed first around the  
IC and as close as possible. The capacitor on comp to  
GND or comp back to FB needs to be place as close to  
the pin as well as resistor divider.  
Layout Considerations  
The layout is very important when designing high  
frequency switching converters. Layout will affect noise  
pickup and can cause a good design to perform with  
less than expected results.  
8. The output sense line which is sensing output  
back to the resistor divider should not go through high  
frequency signals.  
There are two sets of components considered in  
the layout which are power components and small sig-  
nal components. Power components usually consist of  
input capacitors, high-side MOSFET, low-side  
MOSFET, inductor and output capacitors. A noisy en-  
vironment is generated by the power components due  
to the switching power. Small signal components are  
connected to sensitive pins or nodes. A multilayer lay-  
out which includes power plane, ground plane and sig-  
nal plane is recommended .  
9. All GNDs need to go directly thru via to GND  
plane.  
10. The feedback part of the system should be  
kept away from the inductor and other noise sources,  
and be placed close to the IC.  
11. In multilayer PCB, separate power ground and  
analog ground. These two grounds must be connected  
together on the PC board layout at a single point. The  
goal is to localize the high current path to a separate  
loop that does not interfere with the more sensitive ana-  
log control function.  
Layout guidelines:  
1. First put all the power components in the top  
layer connected by wide, copper filled areas. The input  
capacitor, inductor, output capacitor and the MOSFETs  
should be close to each other as possible. This helps  
to reduce the EMI radiated by the power loop due to  
the high switching currents through them.  
2. Low ESR capacitor which can handle input  
RMS ripple current and a high frequency decoupling  
ceramic cap which usually is 1uF need to be practi-  
cally touching the drain pin of the upper MOSFET, a  
plane connection is a must.  
3. The output capacitors should be placed as close  
as to the load as possible and plane connection is re-  
quired.  
4. Drain of the low-side MOSFET and source of  
the high-side MOSFET need to be connected thru a  
plane ans as close as possible. A snubber nedds to be  
placed as close to this junction as possible.  
5. Source of the lower MOSFET needs to be con-  
nected to the GND plane with multiple vias. One is not  
Rev. 1.3  
08/07/07  
20  
NX2710  
SOIC16 PACKAGE OUTLINE DIMENSIONS  
Rev. 1.3  
08/07/07  
21  
NX2710  
Rev. 1.3  
08/07/07  
22  
NX2710  
Customer Service  
NEXSEM Inc.  
500 Wald  
Irvine, CA 92618  
U.S.A.  
Tel: (949)453-0714  
Fax: (949)453-0713  
WWW.NEXSEM.COM  
Rev. 1.3  
08/07/07  
23  
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