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NX2715CMTR

型号:

NX2715CMTR

描述:

单通道手机PWM控制器,带有NMOS LDO控制器, PGOOD指示器和启用[ SINGLE CHANNEL MOBILE PWM CONTROLLER WITH NMOS LDO CONTROLLER, PGOOD INDICATOR AND ENABLE ]

品牌:

MICROSEMI[ Microsemi ]

页数:

21 页

PDF大小:

715 K

NX2715  
SINGLE CHANNEL MOBILE PWM CONTROLLER WITH NMOS  
LDO CONTROLLER, PGOOD INDICATOR AND ENABLE  
ADVANCE DATA SHEET  
Pb Free Product  
FEATURES  
DESCRIPTION  
n
n
n
Bus voltage operation from 7V to 24V  
The NX2715 controller IC is a compact synchronous  
Buck controller IC with 16 lead MLPQ package de-  
signed for step down DC to DC converter applica-  
tions with feedforward functionality. Voltage  
feedforward provides fast response, good line regula-  
tion and nearly constant power stage gain under wide  
voltage input range. The NX2715 controller is optimized  
to convert single supply up to 24V bus voltage to as  
low as 0.8V output voltage. Internal UVLO keeps the  
controller off until the bus supply voltage exceeds 7V  
where internal digital soft starts get initiated to ramp  
up output. The NX2715 employs NMOS LDO control-  
ler, programmable current limiting and FB UVLO fol-  
lowed by latchout feature. Other features include: 5V  
gate drive, programmable frequency, over voltage pro-  
tection, adaptive deadband control and Vcc under volt-  
age lockout.  
Less than 1uA shutdown current with Enable low  
Excellent dynamic response with input voltage  
feed-forward and voltage mode control  
Programmable switching frequency  
Internal digital soft start function  
Programmable current limit triggers latch out  
FB UVLO followed by latch out feature  
NMOS LDO controller available  
n
n
n
n
n
n
n
n
Power Good indicator available  
Start into precharged output  
Pb-free and RoHS compliant  
APPLICATIONS  
Notebook PC  
Graphic Card on board converters  
On board DC to DC such as  
12V to 3.3V, 2.5V or 1.8V  
n
n
n
n
Set Top Box and LCD Display  
TYPICAL APPLICATION  
VIN1  
+7V to 20V  
33uF(25V POSCAP)  
MBR0530T1  
8
16  
1
VIN  
BST  
1uF  
1uF  
0.1uF  
Q1  
Q2  
HDRV  
1.5uH  
VOUT1  
+1.25V@10A  
15  
10  
VIN3  
+5V  
13  
SW  
PVCC  
VCC  
6k  
OCP  
3.9nF  
2*2R5TPE330MC  
3
2
LDRV  
PGND  
10  
6.98k  
14  
1k  
11  
12  
FB  
1uF  
2.49k  
18nF  
12.4k  
COMP  
1nF  
9
4
EN  
RT  
6
7
MTD3055  
LDO OUT  
LDO FB  
100k  
5
PGOOD  
AGND  
2.7k  
2.7nF  
4.22k  
VOUT2  
+1V@2A  
(PAD)  
1k  
22uF ceramic  
Figure1 - Typical application of NX2715  
ORDERING INFORMATION  
Device  
NX2715CMTR  
Temperature  
0 to 70o C  
Package  
MLPQ -16L  
Frequency  
200kHz to 1MHz  
Pb-Free  
Yes  
Rev. 1.4  
01/08/08  
1
NX2715  
ABSOLUTE MAXIMUM RATINGS  
VCC to GND & BST to SW voltage ...................... -0.3V to 6.5V  
VIN to GND ........................................................ -0.3V to 25V  
BST to GND Voltage ......................................... -0.3V to 35V  
SW to GND ....................................................... -2V to 35V  
All other pins ..................................................... -0.3V to 6.5V  
Storage Temperature Range ................................ -65oC to 150oC  
Operating Junction Temperature Range ................ -40oC to 125oC  
ESD Susceptibility ............................................ 2kV  
CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent  
damage to the device. This is a stress only rating and operation of the device at these or any other conditions  
above those indicated in the operational sections of this specification is not implied.  
PACKAGE INFORMATION  
16-LEAD PLASTIC MLPQ  
qJA » 46oC/W  
16 15 14 13  
HDRV  
COMP  
FB  
1
2
3
4
12  
11  
10  
9
PGND  
LDRV  
RT  
17  
AGND  
OCP  
EN  
7
8
5
6
ELECTRICAL SPECIFICATIONS  
Unless otherwise specified, these specifications apply over Vcc =5V, VIN=15V and TA = 0 to 70oC. Typical  
values refer to TA = 25oC.  
PARAMETER  
Reference Voltage  
Ref Voltage  
SYM  
Test Condition  
Min  
TYP  
MAX Units  
VREF  
0.8  
0.2  
V
Ref Voltage line regulation  
Supply Voltage(Vcc)  
VCC Voltage Range  
Operating quiescent current  
Shut down current  
Vcc UVLO  
%
VCC  
IQ  
V
4.75  
5.25  
5
EN=HIGH  
EN=LOW  
3
mA  
uA  
ISD  
1
VCC-Threshold  
VCC_UVLO VCC Rising  
VCC_Hyst VCC Falling  
4.4  
0.2  
V
V
VCC-Hysteresis  
Rev. 1.4  
01/08/08  
2
NX2715  
PARAMETER  
Supply Voltage(Vin)  
Vin Voltage Range  
SYM  
Test Condition  
Min  
TYP  
MAX Units  
Vin  
V
7
25  
40  
1
Input Voltage Current  
Shut Down Current  
Vin=24V  
EN=LOW  
24  
uA  
uA  
Vin UVLO  
Vin-Threshold  
Vin_UVLO Vin Rising  
Vin_Hyst Vin Falling  
6
V
V
Vin-Hysteresis  
0.5  
Oscillator (Rt)  
Frequency  
FS  
RT=open  
Vin=20V  
200  
KHz  
%
Frequency Over Vin  
Ramp-Amplitude Voltage  
Ramp Offset  
-5  
5
VRAMP  
2
V
0.8  
0.1  
88  
V
Ramp/Vin Gain  
Max Duty Cycle  
Min on time  
V/V  
%
nS  
150  
100  
Error Amplifiers  
Transconductance  
2500  
0.3  
umho  
Input Bias Current  
Comp SD threshold  
Ib  
nA  
V
Vref and Soft Start  
Soft Start time  
High Side  
Tss  
RT=open  
10  
1
mS  
ohm  
ohm  
Output Impedance , Sourcing Rsource(Hdrv)  
Current  
I=200mA  
I=200mA  
Output Impedance , Sinking  
Current  
Rsink(Hdrv)  
0.8  
Rise Time  
THdrv(Rise)  
THdrv(Fall)  
10% to 90%  
90% to 10%  
50  
50  
30  
ns  
ns  
ns  
Fall Time  
N
Deadband Time  
Tdead(L to Ldrv going Low to Hdrv going  
H)  
High, 10% to 10%  
Low Side Driver  
Output Impedance, Sourcing Rsource(Ldrv)  
Current  
I=200mA  
I=200mA  
1
ohm  
ohm  
ns  
Output Impedance, Sinking  
Current  
Rsink(Ldrv)  
0.5  
50  
Rise Time  
TLdrv(Rise)  
TLdrv(Fall)  
10% to 90%  
90% to 10%  
Fall Time  
50  
30  
ns  
ns  
Deadband Time  
Tdead(H to SW going Low to Ldrv going  
L) High, 10% to 10%  
OCP Adjust  
OCP current setting  
Enable  
32  
uA  
Enable HI Threshold  
Enable LOW Threshold  
V
V
1.4  
0.4  
Rev. 1.4  
01/08/08  
3
NX2715  
PARAMETER  
SYM  
Test Condition  
Min  
TYP  
90  
5
MAX Units  
Power Good(Pgood)  
Threshold Voltage as % of  
Vref  
FB ramping up  
%
%
Hysteresis  
FBUVLO  
Feedback UVLO threshold  
Over temperature  
Threshold  
percent of nominal  
65  
70  
75  
%
oC  
oC  
150  
20  
Hysteresis  
LDO Controller  
FB Pin- Bias Current  
LDO FB Voltage  
LDO FB UVLO  
High Output Voltage  
Low Output Voltage  
High Output Source Current  
Over Voltage Protection  
Threshold Voltage as % of  
Vref  
100  
75  
nA  
V
%
V
V
mA  
0.8  
70  
10.2  
0.2  
3
percent of nominal  
VIN=12V  
65  
FB ramping up  
130  
45  
%
%
Hysteresis  
Rev. 1.4  
01/08/08  
4
NX2715  
PIN DESCRIPTIONS  
PIN SYMBOL  
PIN DESCRIPTION  
This pin supplies the internal 5V bias circuit. . A high freq 1uF ceramic capacitor is placed  
as close as possible to and connected to this pin and ground pin.  
VCC  
This pin supplies voltage to high side FET driver. A high freq minimum 0.1uF ceramic  
capacitor is placed as close as possible to and connected to this pin and SW pin.  
BST  
AGND  
Analog ground.  
This pin is the error amplifiers inverting input. This pin is connected via resistor divider to  
the output of the switching regulator to set the output DC voltage.  
FB  
This pin is the output of the error amplifier and together with FB pin is used to compensate  
the voltage control feedback loop.  
COMP  
This pin is connected to source of high side FETs and provide return path for the high  
side driver.  
SW  
HDRV  
LDRV  
VIN  
High side gate driver output.  
Low side gate driver output.  
Bus voltage input provides power supply to oscillator and VIN UVLO signal.  
Pull up this pin to Vcc for normal operation. Pulling this pin down below 0.4V shuts down  
the controller and resets the soft start.  
EN  
LDO FB  
LDO controller feedback input. If the LDOFB pin is pulled below 0.7*Vref, an internal  
comparator after certain delay and pulls down LDOOUT pin and initiates the HICCUP  
circuitry.  
LDO OUT  
LDO controller output. This pin is controlling the gate of an external NCH MOSFET. The  
maximum rating of this pin is 16V.  
An open drain output that requires a pull up resistor to Vcc or a voltage lower than Vcc.  
When FB pin reaches 90% of the reference voltage PGOOD transitions from LO to HI  
state.  
PGOOD  
OCP  
This pin is connected to the drain of the external low side MOSFET and is the input of the  
over current protection(OCP) comparator. An internal current source is flown to the  
external resistor which sets the OCP voltage across the Rdson of the low side MOSFET.  
Current limit point is this voltage divided by the Rds-on.  
PGND  
PVCC  
Power ground.  
Ldrv supply voltage. A 1uF high frequency cap must be connected from this pin to GND  
directly.  
Oscillator's frequency can be set by using an external resistor from this pin to GND.  
When RT pin is open, the frequency is 200kHz.  
RT  
Rev. 1.4  
01/08/08  
5
NX2715  
BLOCK DIAGRAM  
PGOOD  
FB  
0.85Vref  
/0.90Vref  
4.4/4.2  
1.25V  
Bias  
Generator  
VCC  
VIN  
POR  
EN  
0.8V  
6/5.75  
COMP  
BST  
START  
START  
Reset dominant  
Hiccup  
DrvH  
SW  
0.3V  
DISABLE  
RT  
OVP  
FB  
1.30Vref  
/0.85Vref  
FET Drivers  
VIN  
PVCC  
DRVL  
START  
PWM  
SS_1/4_done  
Dis_EA  
OSC  
Digital  
start Up  
SS_half_done  
PGND  
S
R
Q
SS_half_done  
70%*Vp  
Vp  
FB  
Vp  
POR  
R
latch  
FB  
Latchout logic  
OCP  
0.6V  
CLAMP  
32uA  
VCC  
COMP  
AGND  
START  
Dis_EA  
EN  
0.6V  
70%*Vp  
SS_1/4_done  
VpLDO  
DISABLE  
EN  
Vp  
LDO OUT  
LDO FB  
Figure 2 - Simplified block diagram of the NX2715  
Rev. 1.4  
01/08/08  
6
NX2715  
VIN1  
+7V to 20V  
33uF(25V POSCAP)  
MBR0530T1  
16  
8
VIN  
BST  
1uF  
1uF  
0.1uF  
1
Q1 FDS8878  
1.5uH  
HDRV  
VOUT1  
+1.25V@10A  
15  
10  
VIN3  
+5V  
13  
SW  
PVCC  
VCC  
6k  
OCP  
3.9nF  
Q2 FDS6676AS  
1k  
2*2R5TPE330MC  
3
2
LDRV  
PGND  
10  
6.98k  
14  
11  
12  
FB  
1uF  
2.49k  
18nF  
COMP  
12.4k  
1nF  
9
4
EN  
RT  
6
7
MTD3055  
LDO OUT  
LDO FB  
100k  
5
PGOOD  
AGND  
2.7k  
2.7nF  
4.22k  
VOUT2  
+1V@2A  
(PAD)  
1k  
22uF ceramic  
Figure 3 - Simplified Demo board schematic  
Rev. 1.4  
01/08/08  
7
NX2715  
5V  
1
1
1
5V  
L1  
VDD  
VIN  
VIN  
C1  
1u  
R1  
10  
SHORT  
C8  
0.1u  
C7  
0.1u  
C9  
25TQC33M  
C12  
open  
C5  
1u  
GNDIN  
D1  
U1  
MBR0530T1  
4
M3B  
open  
8
5
9
16  
VIN  
VIN  
BST  
C11  
1u  
M1  
R5  
0
1
4
HDRV  
SW  
JVOUT  
1
R14  
5V  
PGOOD  
C2  
0.1u  
C15  
0.1u  
100k  
1.25V  
15  
10  
SW  
L2  
SW  
OUT  
VOUT  
R15  
R2  
6k  
DO5010P-152HC  
VIN  
EN  
OCSET  
C13  
C14  
R8  
1k  
100k  
OUT  
R16  
C19  
open  
open  
GNDOUT  
C20  
M2  
2R5TPE330MC 2R5TPE330MC  
R6  
0
10u (cer)  
3
4
LDRV  
R17  
M4  
MTD3055  
6
LDO_OUT  
0
C10  
C16  
JLDO_OUT  
470p  
3.9n  
1
C6  
2
R10  
2.7n  
M3A  
open  
R7  
10  
6.98k  
R9  
1k  
2
C17  
PGND  
1V  
R4  
2.7k  
0.1u  
LDO_OUT  
GNDLDO  
R13  
1k  
1
1
7
LDO_FB  
11  
FB  
C18  
22u (cer)  
R12  
4.22k  
C4  
R11  
12.4k  
18n  
C3  
1n  
R3  
2.49  
R18  
4
12  
5V  
RT  
COMP  
open  
R19  
open  
Figure 4 - Demo board schematic based on ORCAD  
Rev. 1.4  
01/08/08  
8
NX2715  
Bill of Materials  
Item  
1
2
3
4
5
6
7
8
Quantity  
Reference  
C1,C5,C11  
C2,C7,C8,C15,C17  
C3  
C4  
C6  
C9  
C10  
C13,C14  
C16  
C18  
C20  
D1  
L2  
M1  
M2  
M4  
R1,R7  
R2  
Part  
3
5
1
1
1
1
1
2
1
1
1
1
1
1
1
1
2
1
1
1
3
3
1
1
1
2
1
1u  
0.1u  
1n  
18n  
2.7n  
25TQC33M  
470p  
2R5TPE330MC  
9
3.9n  
22u  
10u  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
MBR0530T1  
DO5010P-152HC  
FDS8878  
FDS6676AS  
MTD3055  
10  
6k  
2.49  
2.7k  
0
R3  
R4  
R5,R6,R17  
R8,R9,R13  
R10  
R11  
R12  
1k  
6.98k  
12.4k  
4.22k  
100k  
R14,R15  
U1  
NX2715  
Rev. 1.4  
01/08/08  
9
NX2715  
Demoboard waveforms  
Fig.5 Startup  
Fig.6 Startup with preload  
Fig.7 Voltage Ripple of 1.25V output  
Fig.8 Output short into latch out  
Fig. 10 Dynamic response of LDO output  
Fig. 9 Dynamic response of 1.25V output  
Rev. 1.4  
01/08/08  
10  
NX2715  
APPLICATION INFORMATION  
V -VOUT VOUT  
1
IN  
IRIPPLE  
=
´
´
LOUT  
V
F
IN  
S
...(2)  
Symbol Used In Application Information:  
20V-1.25V 1.25V  
1
=
´
´
= 3.9A  
1.5uH  
20V 200kHz  
VIN  
- Input voltage  
- Output voltage  
- Output current  
VOUT  
IOUT  
Output Capacitor Selection  
VRIPPLE - Output voltage ripple  
Output capacitor is basically decided by the  
amount of the output voltage ripple allowed during  
steady state(DC) load condition as well as specifica-  
tion for the load transient. The optimum design may  
require a couple of iterations to satisfy both condition.  
Based on DC Load Condition  
FS  
- Switching frequency  
- Inductor current ripple  
IRIPPLE  
Design Example  
Power stage design requirements:  
VIN=7-20V  
The amount of voltage ripple during the DC load  
condition is determined by equation(3).  
VOUT=1.25V  
DIRIPPLE  
IOUT =10A  
DVRIPPLE = ESR´ DIRIPPLE  
+
...(3)  
8´ F ´ COUT  
VRIPPLE <=25mV  
VTRAN<=60mV @ 5A step  
FS=200kHz  
S
Where ESR is the output capacitors' equivalent  
series resistance,COUT is the value of output capaci-  
tors.  
Typically when large value capacitors are selected  
such as Aluminum Electrolytic,POSCAP and OSCON  
types are used, the amount of the output voltage ripple  
is dominated by the first term in equation(3) and the  
second term can be neglected.  
Output Inductor Selection  
The selection of inductor value is based on in-  
ductor ripple current, power rating, working frequency  
and efficiency. Larger inductor value normally means  
smaller ripple current. However if the inductance is  
chosen too large, it brings slow response and lower  
efficiency. Usually the ripple current ranges from 20%  
to 40% of the output current. This is a design freedom  
which can be decided by design engineer according to  
various application requirements. The inductor value  
can be calculated by using the following equations:  
For this example, POSCAP are chosen as output  
capacitors, the ESR and inductor current typically de-  
termines the output voltage ripple.  
DVRIPPLE  
DIRIPPLE  
25mV  
3.9A  
ESRdesire  
=
=
= 6.4mW  
...(4)  
If low ESR is required, for most applications, mul-  
tiple capacitors in parallel are better than a big capaci-  
tor. For example, for 25mV output ripple, POSCAP  
2R5TPE330MCC2 with 12mW are chosen.  
V -VOUT VOUT  
1
IN  
LOUT  
=
´
´
IRIPPLE  
V
F
S
IN  
...(1)  
IRIPPLE =k ´ IOUTPUT  
E S R E ´ DIR IPPLE  
N =  
where k is between 0.2 to 0.4.  
Select k=0.3, then  
...(5)  
D VR IPPLE  
20V-1.25V 1.25V  
1
Number of Capacitor is calculated as  
LOUT  
=
´
´
0.4´ 10A  
20V 200kHz  
12m3.9A  
N =  
LOUT =1.5uH  
25mV  
Choose LOUT=1.5uH, then coilcraft inductor  
DO5010P-152HC is a good choice.  
Current Ripple is calculated as  
N =1.9  
The number of capacitor has to be round up to a  
integer. Choose N =2.  
Rev. 1.4  
01/08/08  
11  
NX2715  
If ceramic capacitors are chosen as output ca-  
pacitors, both terms in equation (3) need to be evalu-  
ated to determine the overall ripple. Usually when this  
type of capacitors are selected, the amount of capaci-  
tance per single unit is not sufficient to meet the tran-  
sient specification, which results in parallel configura-  
output inductor is smaller than the critical inductance,  
the voltage droop or overshoot is only dependent on  
the ESR of output capacitor. For low frequency ca-  
pacitor such as electrolytic capacitor, the product of  
ESR and capacitance is high and L £ Lcrit is true. In  
that case, the transient spec is mostly like to depen-  
dent on the ESR of capacitor.  
tion of multiple capacitors. The amount of ceramic  
capacitor output ripple is :  
Most case, the output capacitor is multiple ca-  
pacitor in parallel. The number of capacitor can be cal-  
culated by the following  
DIRIPPLE  
DVRIPPLE = ESR´ DIRIPPLE  
+
8´ 200kHz´ COUT  
Using the above equations, although DC ripple  
spec can be met, however it needs to be studied for  
ESRE ´ DIstep  
VOUT  
N =  
where  
+
´ t 2  
...(9)  
DV  
2´ L´ CE ´ DV  
tran  
tran  
transient requirement.  
Based On Transient Requirement  
Typically, the output voltage droop during tran-  
sient is specified as  
0
if L £ Lcrit  
ì
ï
L´ DI  
t =  
í
ï
î
step  
...(10)  
- ESRE ´ CE  
if L ³ Lcrit  
VOUT  
DV  
< DV  
@step load I  
tran  
droop  
STEP  
For example, assume voltage droop during tran-  
sient is 60mV for 5A load step.  
During the transient, the voltage droop during  
the transient is composed of two sections. One sec-  
tion is dependent on the ESR of capacitor, the other  
section is  
If the POSCAP 2R5TPE330MCC2(330uF,  
12mohm ESR) is used, the crticial inductance is given  
as  
a function of the inductor, output capacitance as well  
as input, output voltage. For example, for the  
overshoot when load from high load to light load  
with a ISTEP transient load, if assuming the band-  
width of system is high enough, the overshoot can  
be estimated as the following equation.  
ESRE ´ CE ´ VOUT  
Lcrit  
=
=
DIstep  
12mW´ 330mF´ 1.25V  
= 0.99mH  
5A  
The selected inductor is 1.5uH which is bigger  
than critical inductance. In that case, the output volt-  
age transient not only dependent on the ESR, but also  
capacitance.  
VOUT  
DVovershoot = ESR ´ DIstep  
+
´ t 2  
...(6)  
2´ L´ COUT  
where  
is the a function of capacitor,etc.  
t
number of capacitors is  
0
if L £ Lcrit  
ì
L´ DIstep  
ï
t =  
- ESRE ´ CE  
L´ DI  
t =  
í
ï
î
step  
...(7)  
...(8)  
VOUT  
- ESR ´ COUT  
if L ³ Lcrit  
VOUT  
1.5mH ´ 5A  
=
- 12m330mF = 2.04us  
where  
ESR ´ COUT ´ VOUT ESRE ´ CE ´ VOUT  
1.25V  
Lcrit  
=
=
ESRE ´ DIstep  
DIstep  
DIstep  
VOUT  
N =  
+
´ t 2  
DV  
2´ L´ CE ´ DV  
tran  
tran  
where ESRE and CE represents ESR and capaci-  
tance of each capacitor if multiple capacitors are used  
in parallel.  
12m5A  
=
+
60mV  
1.25V  
´ 2.04us2  
The above equation shows that if the selected  
2´ 1.5mH´ 330mF´ 60mV  
=1.74  
Rev. 1.4  
01/08/08  
12  
NX2715  
pensate the system with type III compensator. The  
following figures and equations show how to realize  
the type III compensator by transconductance ampli-  
fier.  
The number of capacitors has to satisfy both ripple  
and transient requirement. Overall, we choose N=2.  
It should be considered that the proposed equa-  
tion is based on ideal case, in reality, the droop or over-  
shoot is typically more than the calculation. The equa-  
tion gives a good start. For more margin, more ca-  
pacitors have to be chosen after the test. Typically, for  
high frequency capacitor such as high quality POSCAP  
especially ceramic capacitor, 20% to 100% (for ce-  
ramic) more capacitors have to be chosen since the  
ESR of capacitors is so low that the PCB parasitic can  
affect the results tremendously. More capacitors have  
to be selected to compensate these parasitic param-  
eters.  
1
FZ1  
FZ2  
=
=
=
=
...(11)  
...(12)  
...(13)  
...(14)  
2´ p ´ R4 ´ C2  
1
2´ p ´ (R2 + R3 )´ C3  
1
F
P1  
2´ p ´ R3 ´ C3  
1
F
P2  
C1 ´ C2  
2´ p ´ R4 ´  
C1 + C2  
where FZ1,FZ2,FP1 and FP2 are poles and zeros in  
the compensator.  
Compensator Design  
The transfer function of type III compensator for  
transconductance amplifier is given by:  
Due to the double pole generated by LC filter of  
the power stage, the power system has 180o phase  
shift , and therefore, is unstable by itself. In order to  
achieve accurate output voltage and fast transient re-  
sponse, compensator is employed to provide highest  
possible bandwidth and enough phase margin. Ideally,  
the Bode plot of the closed loop system has crossover  
frequency between 1/10 and 1/5 of the switching fre-  
quency, phase margin greater than 50o and the gain  
crossing 0dB with -20dB/decade. Power stage output  
capacitors usually decide the compensator type. If  
electrolytic capacitors are chosen as output capacitors,  
type II compensator can be used to compensate the  
system, because the zero caused by output capacitor  
ESR is lower than crossover frequency. Otherwise type  
III compensator should be chosen.  
Ve  
1- gm ´ Zf  
=
VOUT  
1+ gm ´ Zin + Zin /R1  
For the voltage amplifier, the transfer function of  
compensator is  
Ve  
- Zf  
=
VOUT  
Zin  
To achieve the same effect as voltage amplifier,  
the compensator of transconductance amplifier must  
satisfy this condition: R4>>2/gm. And it would be de-  
sirable if R1||R2||R3>>1/gm can be met at the same  
time.  
Zf  
Vout  
Zin  
R3  
C3  
C1  
Voltage feedforward is used in NX2715 to com-  
pensate the output voltage variation caused by input  
voltage changing. The feedforward funtion is realized  
by using VIN pin voltage to program the oscillator ramp  
voltage VOSC at about 1/10 of VIN voltage, which pro-  
vides nearly constant power stage gain under wide volt-  
age input range.  
C2  
R4  
R2  
R1  
Fb  
Ve  
gm  
Vref  
A. Type III compensator design  
For low ESR output capacitors, typically such as  
Sanyo oscap and poscap, the frequency of ESR zero  
caused by output capacitors is higher than the cross-  
over frequency. In this case, it is necessary to com-  
Figure 11 - Type III compensator using  
transconductance amplifier  
Rev. 1.4  
01/08/08  
13  
NX2715  
Case 1:  
FLC<FO<FESR(for most ceramic or low  
2. Set R4 equal to 2.5kW.  
ESR POSCAP, OSCON)  
3. Calculate C2 with zero Fz1 at 75% of the LC  
double pole by equation (11).  
1
C2 =  
2´ p ´ FZ1 ´ R4  
power stage  
LC  
F
1
=
2´ p ´ 0.75´ 5.06kHz´ 2.5kW  
= 17nF  
40dB/decade  
Choose C2=18nF.  
4. Calculate C1 by equation (14) with pole Fp2 at  
one third of the switching frequency.  
loop gain  
ESR  
F
1
C1 =  
20dB/decade  
2´ p ´ R4 ´ F  
P2  
1
=
compensator  
2´ p ´ 2.5k66.7kHz  
= 959pF  
Choose C1=1nF.  
5. Calculate C3 with the crossover frequency FO  
at 15kHz.  
FZ1  
FO  
FP2  
FZ2  
FP1  
VOSC 2´ p ´ FO ´ L´ COUT  
C3 =  
=
´
Figure 12 - Bode plot of Type III compensator  
(FLC<FO<FESR  
V
R4  
IN  
)
1
2´ p ´ 15kHz´ 1.5uH´ 660uF  
2.5kW  
´
10  
Typical design example of type III compensator  
in which the crossover frequency is selected as  
FLC<FO<FESR and FO<=1/10~1/5Fs is shown as the  
following steps. In this example, output voltage is  
1.25V, output inductor is 1.5uH, output capacitors are  
two POSCAP 2R5TPE330MCC2 (330uF, 12mohm  
ESR)  
=3.7nF  
Choose C3=3.9nF.  
6. Calculate R3 by equation (13) with Fp1 =FESR  
.
1
R3 =  
2´ p ´ F ´ C3  
P1  
1
=
1. Calculate the location of LC double pole FLC  
2´ p ´ 40kHz´ 3.9nF  
= 1k W  
and ESR zero FESR  
.
1
Choose R3 =1kW.  
F
=
=
LC  
2´ p ´  
L
OUT ´ COUT  
7. Calculate R2 by setting compensator zero  
FZ2 at the LC double pole.  
1
2´ p ´ 1.5uH´ 660uF  
1
2´ p ´ C3  
1
1
1
= 5.06kHz  
R2 =  
´ (  
-
)
FZ2  
F
P1  
1
1
1
=
´ (  
-
)
FESR  
=
2´ p ´ 3.9nF 5.06kHz 40kHz  
2 ´ p ´ ESR ´ COUT  
1
= 7.05kW  
=
2 ´ p ´ 6m660uF  
Choose R2 =6.98kW.  
= 40kHz  
Rev. 1.4  
01/08/08  
14  
NX2715  
8. Calculate R1 .  
R2 ´ VREF  
1
F
=
=
ESR  
6.98k0.8V  
2´ p ´ ESR ´ COUT  
1
R1=  
=
= 12.41k W  
VOUT -VREF  
1.25V-0.8V  
2´ p ´ 9m2000uF  
Choose R1=12.4kW.  
Case 2: FLC<FESR<FO(for electrolytic capacitors)  
= 8.8kHz  
2. Set R4 equal to 2.5kW.  
3. Calculate C2 with zero Fz1 at 75% of the LC  
double pole by equation (11).  
power stage  
1
C2 =  
LC  
F
2 ´ p ´ FZ1 ´ R4  
40dB/decade  
1
=
2´ p ´ 0.75 ´ 2.4kHz ´ 2.5kW  
= 35nF  
ESR  
F
Choose C2=33nF.  
loop gain  
4. Calculate C1 by equation (14) with pole Fp2 at  
one third of the switching frequency.  
20dB/decade  
1
C1 »  
2´ p ´ R4 ´ F  
P2  
compensator  
1
»
2´ p ´ 2.5k66.7kHz  
» 959pF  
Choose C1=1nF.  
FZ1  
FO  
FP2  
FZ2  
FP1  
5. Calculate R3 with the crossover frequency FO  
at 15kHz.  
Figure 13 - Bode plot of Type III compensator  
(FLC<FESR<FO)  
V
ESR´ R4  
IN  
R3 =  
´
VOSC 2´ p ´ FO ´ L  
9mohm´ 2.5kW  
If electrolytic capacitors are used as output  
capacitors, typical design example of type III  
compensator in which the crossover frequency is  
selected as FLC<FESR<FO and FO<1/10Fs is shown as  
the following steps. Here two SANYO MV-WF1000 with  
18 mW is chosen as output capacitor, output inductor  
is 2.2uH, output voltage is 1.05V, switching frequency  
is 200kHz.  
=10´  
2´ p ´ 15kHz´ 1uH  
=1.08kW  
Choose R3=1.2kW.  
6. Calculate C3 by equation (13) with Fp1 =FESR  
.
1
C3 =  
2´ p ´ F ´ R3  
P1  
1. Calculate the location of LC double pole FLC  
1
=
and ESR zero FESR  
.
2´ p ´ 8.8kHz´ 1.2kW  
= 14nF  
1
F
=
LC  
Choose C3 =15nF.  
2´ p ´  
L
OUT ´ COUT  
7. Calculate R2 by setting compensator zero  
FZ2 at the LC double pole.  
1
=
2´ p ´ 2.2uH´ 2000uF  
= 2.4kHz  
Rev. 1.4  
01/08/08  
15  
NX2715  
The following equations show the compensator  
pole zero location and constant gain.  
1
1
1
R2 =  
´ (  
-
)
2 ´ p ´ C3  
1
FZ2 FP1  
1
2.4kHz 8.8kHz  
1
R1  
=
´ (  
-
)
Gain=gm ´  
´ R3  
...(15)  
... (16)  
... (17)  
2 ´ p ´ 15nF  
= 3.2kW  
R1+R2  
1
F =  
z
Choose R2 =4kW.  
8. Calculate R1 .  
2´ p ´ R3 ´ C1  
1
F »  
p
2´ p ´ R3 ´ C2  
R2 ´ VREF  
4k0.8V  
R1=  
=
= 12.8kW  
VOUT -VREF 1.05V-0.8V  
Choose R1=12.7kW.  
Vout  
B. Type II compensator design  
R2  
If the electrolytic capacitors are chosen as  
power stage output capacitors, usually the Type II  
compensator can be used to compensate the sys-  
tem.  
Fb  
Ve  
R3  
gm  
R1  
Vref  
C2  
For this type of compensator, FO has to satisfy  
FLC<FESR<<FO<1/10Fs.  
C1  
power stage  
Figure 15 - Type II compensator with  
transconductance amplifier  
40dB/decade  
The following is parameters for type II compen-  
sator design. Input voltage is 12V, output voltage is  
2.5V, output inductor is 2.2uH, output capacitors are  
two 680uF with 41mW electrolytic capacitors.  
loop gain  
20dB/decade  
1.Calculate the location of LC double pole FLC  
and ESR zero FESR  
.
compensator  
Gain  
1
F
=
=
LC  
2´ p ´  
L
OUT ´ COUT  
1
2´ p ´ 2.2uH´ 1360uF  
P
F
F
F
Z
LCFESR  
FO  
= 2.9kHz  
1
F
=
ESR  
2´ p ´ ESR´ COUT  
Figure 14 - Bode plot of Type II compensator  
1
=
2´ p ´ 20.5m1360uF  
Type II compensator can also be realized by  
simple RC circuit without feedback as shown in figure  
15. R3 and C1 introduce a zero to cancel the double  
pole effect. C2 introduces a pole to suppress the switch-  
= 5.7kHz  
ing noise.  
Rev. 1.4  
01/08/08  
16  
NX2715  
1.Set R2 equal to10kW. Using equation 18, the  
final selection of R1 is 4.7kW.  
Vout  
2. Set crossover frequency at 1/20 of the  
swithing frequency, here FO=10kHz.  
R2  
Fb  
3.Calculate R3 value by the following equation.  
R1  
VOSC 2´ p ´ FO ´ L  
VOUT  
1
Vref  
R3 =  
=
´
´
´
V
RESR  
gm VREF  
in  
1
2´ p ´ 10kHz´ 2.2uH  
1
´
´
Figure 16 - Voltage divider  
10  
20.5mW  
2.5V  
2.5mA/V  
R 2 ´ VREF  
´
R1=  
0.8V  
...(18)  
VOUT -VREF  
=0.8kW  
where R2 is part of the compensator, and the value  
of R1 value can be set by voltage divider.  
Choose R3 =1kW.  
4. Calculate C1 by setting compensator zero FZ  
at 75% of the LC double pole.  
Input Capacitor Selection  
Input capacitors are usually a mix of high fre-  
quency ceramic capacitors and bulk capacitors. Ce-  
ramic capacitors bypass the high frequency noise, and  
bulk capacitors supply switching current to the  
MOSFETs. Usually 1uF ceramic capacitor is chosen  
to decouple the high frequency noise.The bulk input  
capacitors are decided by voltage rating and RMS cur-  
rent rating. The RMS current in the input capacitors  
1
C1=  
2 ´ p ´ R3 ´ Fz  
1
=
2 ´ p ´ 1k0.75 ´ 2.9kHz  
=70nF  
Choose C1=68nF.  
F
5. Calculate C2 by setting compensator pole  
at half the swithing frequency.  
p
can be calculated  
as:  
1
C
=
=
2
p ´ R ´ F s  
3
IRMS = IOUT  
´
D ´ 1-D  
1
VOUT  
p ´ 1k W ´ 3 0 0 k H z  
= 5 3 0 p F  
D =  
V
INMIN  
...(19)  
VINMIN = 7V, VOUT=1.05V, IOUT=10A, the result of  
input RMS current is 3.8A.  
Choose C2=560pF.  
Output Voltage Calculation  
For higher efficiency, low ESR capacitors are  
recommended. One Sanyo OSCON CAP 25SVP56M  
25V 56uF 28mW with 3.8A RMS rating are chosen  
as input bulk capacitors.  
Output voltage is set by reference voltage and  
external voltage divider. The reference voltage is fixed  
at 0.8V. The divider consists of two ratioed resistors  
so that the output voltage applied at the Fb pin is 0.8V  
when the output voltage is at the desired value. The  
following equation applies to figure 16, which shows  
the relationship between VOUT , VREF and voltage di-  
vider.  
Rev. 1.4  
01/08/08  
17  
NX2715  
This power dissipation should not exceed maxi-  
mum power dissipation of the driver device.  
Power MOSFETs Selection  
The NX2715 requires two N-Channel power  
MOSFETs. The selection of MOSFETs is based on  
maximum drain source voltage, gate source voltage,  
maximum current rating, MOSFET on resistance and  
power dissipation. The main consideration is the power  
Over Current Limit Protection  
Over current protection is achieved by sensing  
current through the low side MOSFET. An internal cur-  
rent source of 32uA flows through an external resistor  
connected from OCP pin to SW node sets the over  
current protection threshold. When synchronous FET  
is on, the voltage at node SW is given as  
VSW =-IL ´ RDSON  
loss contribution of MOSFETs to the overall converter  
efficiency. For example, two IRF7822 are used in ap-  
plication. They have the following parameters: VDS=30V,  
ID =18A,RDSON =6.5mW,QGATE =44nC.  
There are two factors causing the MOSFET  
power loss:conduction loss, switching loss.  
Conduction loss is simply defined as:  
The voltage at pin OCP is given as  
IOCP ´ ROCP +VSW  
P
HCON =IOUT2 ´ D´ RDS(ON) ´ K  
LCON=IOUT2 ´ (1- D)´ RDS(ON) ´ K  
PTOTAL =P + P  
When OCP pin voltage is below zero, the over  
current occurs after three cycles as shown in figure 17,  
both Hdrv and Ldrv will be shut down.  
P
...(20)  
HCON  
LCON  
where the RDS(ON) will increases as MOSFET junc-  
tion temperature increases, K is RDS(ON) temperature  
dependency. As a result, RDS(ON) should be selected  
for the worst case, in which K approximately equals to  
1.4 at 125oC according to datasheet. Conduction loss  
should not exceed package rating or overall system  
thermal budget.  
Switching loss is mainly caused by crossover  
conduction at the switching transition. The total  
switching loss can be approximated.  
1
PSW  
=
´ V ´ IOUT ´ TSW ´ F  
IN S  
...(21)  
2
where IOUT is output current, TSW is the sum of TR  
and TF which can be found in mosfet datasheet, and  
FS is switching frequency. Swithing loss PSW is fre-  
quency dependent.  
Also MOSFET gate driver loss should be consid-  
ered when choosing the proper power MOSFET.  
MOSFET gate driver loss is the loss generated by dis-  
charging the gate capacitor and is dissipated in driver  
circuits.It is proportional to frequency and is defined  
as:  
vbus  
I
OCP  
32uA  
OCP  
R
SW  
OCP  
OCP  
comparator  
Pgate = (QHGATE ´ VHGS + QLGATE ´ VLGS )´ FS  
...(22)  
where QHGATE is the high side MOSFETs gate  
charge,QLGATE is the low side MOSFETs gate  
charge,VHGS is the high side gate source voltage, and  
VLGS is the low side gate source voltage.  
Figure 17 - Over Current Protection Waveform  
and Block Diagram  
Rev. 1.4  
01/08/08  
18  
NX2715  
The over current limit can be set by the following  
where FO is the desired crossover frequency.  
Typically, in this LDO compensation, crossover  
frequency FO has to be higher than zero caused by  
ESR. FO is typically around several tens kHz to a few  
hundred kHz. For this example, we select Fo=100kHz.  
gm is the forward trans-conductance of MOSFET.  
equation:  
I
OCP ´ ROCP  
ISET  
=
K ´ RDSON  
If MOSFET RDSON=6.5mW, the worst case ther-  
mal consideration K=1.5 and the current limit is set at  
15A, then  
LDO input  
I
SET ´ K ´ RDSON 15A ´ 1.5´ 6.5mW  
ROCP  
=
=
= 4.57kW  
IOCP  
32uA  
Vref  
R
f1  
Choose ROCP=4.64kW.  
For NX2715, if switching channel goes into OCP  
and latch up, the LDO will be latch up at the same  
time.  
ESR  
Co  
R
f2  
Rload  
Rc  
Cc  
LDO Selection Guide  
NX2715 offers a LDO controller. The selection  
of MOSFET to meet LDO is more straight forward.  
The selection is that the Rdson of MOSFET should  
meet the dropout requirement. For example.  
VLDOIN =3.3V  
Figure 18 - NX2715 LDO controller.  
For IRFR3706, gm=53.  
Select Rf1=5kohm.  
VLDOOUT =2.5V  
Output capacitor is Sanyo POSCAP 4TPE150MI  
with 150uF, ESR=18mohm.  
ILoad =2A  
The maximum Rdson of MOSFET should be  
1
53 ´ 18mW  
RRDSON = (VLDOIN - VLDOOUT )´ ILOAD  
= (3.3V - 2.5V) / 2A = 0.4W  
CC =  
´
=77pF  
4 ´ p ´ 100kHz ´ 5kW 1+53 ´ 18mW  
Most of MOSFETs can meet the requirement.  
More important is that MOSFET has to be selected  
right package to handle the thermal capability. For LDO,  
maximum power dissipation is given as  
Choose CC=82pF. For electrolytic or POSCAP,  
RC is typically selected to be zero.  
Rf2 is determined by the desired output voltage.  
Rf1 ´ VREF  
Rf2 =  
PLOSS = (VLDOIN - VLDOOUT )´ ILOAD  
= (3.3V - 2.5V)´ 2A =1.6W  
VLDOOUT - VREF  
5k0.8V  
=
Select IR MOSFET IRFR3706 with 9mW RDSON  
1.6V - 0.8V  
is sufficient.  
=5kW  
Choose Rf2=5kW.  
LDO Compensation  
When ceramic capacitors or some low ESR bulk  
capacitors are chosen as LDO output capacitors, the  
zero caused by output capacitor ESR is so high that  
crossover frequency FO has to be chosen much higher  
than zero caused by RC and CC and much lower than  
zero caused by ESR . For example, 22uF ceramic is  
used as output capacitor. We select Fo=100kHz,  
Rf1=1kohm and select MOSFET MTD3055(gm=5). RC  
and CC can be calculated as follows.  
The diagram of LDO controller including VCC  
regulator is shown in the following figure.  
For most low frequency capacitor such as elec-  
trolytic, POSCAP, OSCON, etc, the compensation pa-  
rameter can be calculated as follows.  
gm ´ ESR  
1
CC =  
´
4´ p ´ FO ´ Rf1 1+gm ´ ESR  
Rev. 1.4  
01/08/08  
19  
NX2715  
Layout Considerations  
2´ p ´ FO ´ CO  
0.5´ gm  
RC =Rf1 ´  
The layout is very important when designing high  
frequency switching converters. Layout will affect noise  
pickup and can cause a good design to perform with  
less than expected results.  
2´ p ´ 100kHz´ 22uF  
=1kW´  
=5.4kW  
0.5´ 5S  
There are two sets of components considered in  
the layout which are power components and small sig-  
nal components. Power components usually consist of  
input capacitors, high-side MOSFET, low-side  
MOSFET, inductor and output capacitors. A noisy en-  
vironment is generated by the power components due  
to the switching power. Small signal components are  
connected to sensitive pins or nodes. A multilayer lay-  
out which includes power plane, ground plane and sig-  
nal plane is recommended .  
Choose RC=5.4kW.  
10´ CO  
CC =  
RC ´ gm  
10´ 22uF  
=
2´ p ´ 5.4k5S  
=1.3nF  
Choose CC=1.2nF.  
Current Limit for LDO  
Layout guidelines:  
Current limit of LDO is achieved by sensing  
1. First put all the power components in the top  
layer connected by wide, copper filled areas. The input  
capacitor, inductor, output capacitor and the MOSFETs  
should be close to each other as possible. This helps  
to reduce the EMI radiated by the power loop due to  
the high switching currents through them.  
the LDO feedback voltage. When LDO_FB pin is  
below 70% of VREF, the IC goes into latch up. The IC  
will turn off all the channel and latch up.  
Over Voltage Protection  
When FB pin voltage exceeds  
1.04V(130%*VRE F) and be there for three cycles, over  
voltage protection will be triggered. Hdrv turns low  
and Ldrv turns high. Ldrv will be from high to low once  
FB voltage falls below 0.68V(85%*VREF).  
2. Low ESR capacitor which can handle input  
RMS ripple current and a high frequency decoupling  
ceramic cap which usually is 1uF need to be practi-  
cally touching the drain pin of the upper MOSFET, a  
plane connection is a must.  
3. The output capacitors should be placed as close  
as to the load as possible and plane connection is re-  
quired.  
4. Drain of the low-side MOSFET and source of  
the high-side MOSFET need to be connected thru a  
plane ans as close as possible. A snubber nedds to be  
placed as close to this junction as possible.  
5. Source of the lower MOSFET needs to be con-  
nected to the GND plane with multiple vias. One is not  
enough. This is very important. The same applies to  
the output capacitors and input capacitors.  
6. Hdrv and Ldrv pins should be as close to  
MOSFET gate as possible. The gate traces should be  
wide and short. A place for gate drv resistors is needed  
to fine tune noise if needed.  
7. Vcc capacitor, BST capacitor or any other by-  
Figure 19 - OVP trigger threshold.  
Rev. 1.4  
01/08/08  
20  
NX2715  
passing capacitor needs to be placed first around the  
IC and as close as possible. The capacitor on comp to  
GND or comp back to FB needs to be place as close to  
the pin as well as resistor divider.  
8. The output sense line which is sensing output  
back to the resistor divider should not go through high  
frequency signals.  
9. All GNDs need to go directly thru via to GND  
plane.  
10. The feedback part of the system should be  
kept away from the inductor and other noise sources,  
and be placed close to the IC.  
11. In multilayer PCB, separate power ground and  
analog ground. These two grounds must be connected  
together on the PC board layout at a single point. The  
goal is to localize the high current path to a separate  
loop that does not interfere with the more sensitive ana-  
log control function.  
Rev. 1.4  
01/08/08  
21  
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