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NX2114CSTR

型号：

NX2114CSTR

描述：

为300kHz和600kHz的同步PWM控制器[ 300kHz & 600kHz SYNCHRONOUS PWM CONTROLLER ]

品牌：

MICROSEMI[ Microsemi ]

页数：

20 页

PDF大小：

810 K

下载PDF手册
Evaluation board available.  
NX2114/2114A  
300kHz & 600kHz SYNCHRONOUS PWM CONTROLLER  
PRELIMINARY DATA SHEET  
Pb Free Product  
FEATURES  
DESCRIPTION  
n Synchronous Controller in 8 Pin Package  
The NX2114 controller IC is a synchronous Buck con-  
troller IC designed for step down DC to DC converter  
applications. Synchronous control operation replaces  
the traditional catch diode with an Nch MOSFET result-  
ing in improved converter efficiency.Although the NX2114  
controller is optimized to convert single 5V bus voltages  
to supplies as low as 0.8V output voltage, however us-  
ing a few external components it can also be used for  
other input supplies such as 12V input (See NX2113  
data sheet for more optimized solution). The NX2114  
operates at 300kHz while 2114A is set at 600kHz  
operation which together with less than 50 nS of dead  
band provides an efficient and cost effective solution.  
Other features of the device are:  
n
n
n
Bus voltage operation from 2V to 25V  
Single 5V Supply Operation  
Short protection with feedback UVLO  
n Internal 300kHz for 2114 and 600kHz for 2114A  
n Internal Digital Soft Start Function  
n Shut Down via pulling comp pin low  
n Pb-free and RoHS compliant  
APPLICATIONS  
n
n
n
Graphic Card on board converters  
Memory Vddq Supply in mother board applications  
On board DC to DC such as  
5V to 3.3V, 2.5V or 1.8V  
Internal digital soft start; Vcc undervoltage lock out; Out-  
put undervoltage protection with digital filter and shut-  
down capability via the enable pin.  
n
n
Hard Disk Drive  
Set Top Box  
TYPICAL APPLICATION  
L2 1uH  
Vin  
+5V  
C4  
47uF,70mohm  
R5  
10  
D1 MBR0530T1  
C6  
1uF  
C8  
47uF,70mohm  
C5  
1uF  
Cin  
5
1
220uF,12mohm  
C7  
0.1uF  
BST  
Vcc  
M1  
L1 1.5uH  
7
2
8
Comp  
Fb  
Hdrv  
OFF  
R6  
10k  
C2  
2N3904  
ON  
1.5nF  
Vout  
R7  
C1  
47pF  
SW  
R4  
+1.6V,6A  
10k  
Co  
22.1k  
2 x (220uF,15mohm)  
6
M2  
4
Ldrv  
Gnd  
3
R1  
10.2k  
R2  
10.2k  
R3  
1.5k  
C3  
2.2nF  
Figure1 - Typical application of 2114  
ORDERING INFORMATION  
Device  
NX2114CSTR  
NX2114ACSTR  
Temperature  
0 to 70oC  
Package  
SOIC-8L  
SOIC-8L  
Frequency  
300kHz  
600kHz  
Pb-Free  
Yes  
Yes  
0 to 70o C  
Rev. 4.0  
06/20/06  
1
NX2114/2114A  
ABSOLUTE MAXIMUM RATINGS(NOTE1)  
Vcc to GND & BST to SW voltage ................... 6.5V  
BST to GND Voltage ...................................... 35V  
Storage Temperature Range ............................. -65oC to 150oC  
Operating Junction Temperature Range ............. -40oC to 125oC  
NOTE1: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent  
damage to the device. This is a stress only rating and operation of the device at these or any other  
conditions above those indicated in the operational sections of this specification is not implied.  
PACKAGE INFORMATION  
8-PIN PLASTIC SOIC (S)  
qJA » 130o C/W  
BST  
HDrv  
Gnd  
1
2
3
4
8
7
6
5
SW  
Comp  
Fb  
LDrv  
Vcc  
ELECTRICAL SPECIFICATIONS  
Unless otherwise specified, these specifications apply over Vcc = 5V, and TA = 0 to 70oC. Typical values refer to TA  
= 25oC. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient  
temperature.  
PARAMETER  
Reference Voltage  
Ref Voltage  
SYM  
Test Condition  
4.5V<Vcc<5.5V  
Min  
TYP  
MAX Units  
VREF  
0.8  
0.1  
V
Ref Voltage line regulation  
Supply Voltage(Vcc)  
VCC Voltage Range  
VCC Supply Current (Static)  
VCC Supply Current  
(Dynamic)  
%
VCC  
5
2.1  
5
V
4.5  
5.5  
ICC (Static) Outputs not switching  
mA  
mA  
ICC  
(Dynamic)  
CLOAD=3300pF FS=300kHz  
Supply Voltage(VBST  
)
VBST Supply Current (Static)  
IBST (Static) Outputs not switching  
0.15  
5
mA  
mA  
VBST Supply Current  
(Dynamic)  
IBST  
CLOAD=3300pF FS=300kHz  
(Dynamic)  
Under Voltage Lockout  
VCC-Threshold  
VCC_UVLO VCC Rising  
VCC_Hyst VCC Falling  
4.2  
V
V
VCC-Hysteresis  
0.22  
Rev. 4.0  
06/20/06  
2
NX2114/2114A  
PARAMETER  
SYM  
Tss  
Test Condition  
Min  
TYP  
MAX Units  
SS  
Soft Start time  
Oscillator (Rt)  
Frequency  
Fsw=300Khz, 2114  
3.4  
mS  
FS  
2114  
300  
600  
1.7  
94  
kHz  
kHz  
V
2114A  
Ramp-Amplitude Voltage  
Max Duty Cycle  
VRAMP  
%
Min Duty Cycle  
%
0
Error Amplifiers  
Transconductance  
1900  
10  
umho  
nA  
Input Bias Current  
Ib  
Comp SD Threshold  
FB Under Voltage Protection  
FB Under voltage threshold  
High Side Driver(CL=3300pF)  
0.3  
V
0.4  
1.1  
0.8  
V
Output Impedance , Sourcing  
Current  
Rsource(Hdrv)  
Rsink(Hdrv)  
I=200mA  
I=200mA  
ohm  
ohm  
Output Impedance , Sinking  
Current  
Output Sourcing Current  
Output Sinking Current  
Rise Time  
VBST-VHDRV=5V  
VHDRV-VSW=5V  
10% to 90%  
2
A
A
2
THdrv(Rise)  
THdrv(Fall)  
50  
50  
30  
ns  
ns  
ns  
Fall Time  
90% to 10%  
Deadband Time  
Tdead(L to Ldrv going Low to Hdrv  
H)  
going High, 10%-10%  
Low Side Driver (CL=3300pF)  
Output Impedance, Sourcing  
Current  
Rsource(Ldrv)  
Rsink(Ldrv)  
I=200mA  
I=200mA  
1.1  
0.5  
ohm  
ohm  
Output Impedance, Sinking  
Current  
Output Sourcing Current  
Output Sinking Current  
VPVCC-VLDRV=5V  
VLDRV-PGND=5V  
2
4
A
A
Rise Time  
Fall Time  
Deadband Time  
TLdrv(Rise)  
TLdrv(Fall)  
Tdead(H to SW going Low to Ldrv  
L) going High, 10% to 10%  
10% to 90%  
90% to 10%  
50  
50  
30  
ns  
ns  
ns  
Rev. 4.0  
06/20/06  
3
NX2114/2114A  
PIN DESCRIPTIONS  
PIN #  
PIN SYMBOL  
PIN DESCRIPTION  
This pin supplies voltage to the high side driver. A high frequency  
1
BST  
ceramic capacitor of 0.1 to 1 uF must be connected from this pin to SW pin.  
High side MOSFET gate driver.  
Ground pin.  
2
3
4
HDRV  
GND  
Low side MOSFET gate driver.  
LDRV  
Voltage supply for the internal circuit as well as the low side MOSFET gate  
driver. A 1uF high frequency ceramic capacitor must be connected from this pin  
to GND pin.  
5
6
Vcc  
FB  
This pin is the error amplifier inverting input. This pin is also connected to the  
output UVLO comparator. When this pin falls below 0.4V, both HDRV and LDRV  
outputs are latched off.  
This pin is the output of the error amplifier and together with FB pin is used to  
compensate the voltage control feedback loop. This pin is also used as a shut  
down pin. When this pin is pulled below 0.3V, both drivers are turned off and  
internal soft start is reset.  
7
8
COMP  
SW  
This pin is connected to the source of the high side MOSFET and provides  
return path for the high side driver.  
Rev. 4.0  
06/20/06  
4
NX2114/2114A  
BLOCK DIAGRAM  
1
BST  
5
VCC  
UVLO  
2
Hdrv  
8
DRIVER  
SW  
4
Ldrv  
3
GND  
OSC  
7
COMP  
Q
Q
S
R
6
FB  
0.3V  
LATCH  
TIMER  
0.4V  
DIGITAL SS  
VREF  
Figure 1 - Simplified block diagram of the NX2114  
Rev. 4.0  
06/20/06  
5
NX2114/2114A  
Demoboard design and waveforms  
sdfd  
L2 1uH  
Vin  
+5V  
C4  
47uF,70mohm  
R5  
10  
D1 1N5819  
C6  
1uF  
C8  
47uF,70mohm  
C5  
1uF  
Cin  
5
1
220uF,12mohm  
C7  
0.1uF  
BST  
Vcc  
7
2
8
4
M1  
L1 1.5uH  
Comp  
Hdrv  
C2  
1.5nF  
Vout  
C1  
47pF  
SW  
R4  
+1.6V,6A  
Co  
22.1k  
2 x (220uF,15mohm)  
6
M2  
Ldrv  
Fb  
Gnd  
3
R1  
10.2k  
C3  
R2  
10.2k  
R3  
1.5kohm  
2.2nF  
Figure 2 - demoboard design on NX2114  
Bill of Material  
Name  
Component description  
10.2k 1% chip resistor  
10.2k 1% chip resistor  
1.5k 1% chip resistor  
22.1k 1% chip resistor  
Vendor  
Vendor P/N  
Number  
R1  
R2  
R3  
R4  
R5  
C1  
C2  
C3  
1
1
1
1
1
1
1
1
1
1
sdfdsf  
10  
chip resistor  
47pF ceramic  
1.5nF ceramic  
2.2nF ceramic  
47uF,16V,70mohm,SMD  
1uF ceramic  
C4,C8  
C5,C6  
Sanyo  
16TQC47M  
C7  
0.1uF ceramic  
1
1
CIN  
220uF,6.3V,12mohm,SMD  
Sanyo  
Sanyo  
6TPD220M  
CO  
220uF,4V,15mohm,SMD  
4TPE220MF  
2
D1  
Diode  
D1N5819  
1
1
1
1
M1,M2  
L1  
MOSFET  
1.5uH,6.8A  
1uH,6.4A  
Fairchild  
Coilcraft  
Coilcraft  
FDS6294  
DO3316P-152  
DO3316P-102  
L2  
Note: To make sure short circuit protection of device functions correctly, C8 and R5 are necessary for  
filtering noise in single power supply design.  
Rev. 4.0  
06/20/06  
6
NX2114/2114A  
Vin=5V,Vout=1.6V  
95  
90  
85  
80  
75  
70  
0
1
2
3
4
5
6
Current (A)  
Figure 4: Voltage ripple @1.6 V output  
Figure 3: Output efficiency  
voltage, 7A output current  
Figure 5: Start up time  
Figure 6: Output voltage transient  
response for load curent 0A-6A  
Figure 8: Startup operation waveform  
Figure 7: Output voltage droop during  
transient(0A-6A)  
Rev. 4.0  
06/20/06  
7
NX2114/2114A  
APPLICATION INFORMATION  
V -VOUT VOUT  
1
IN  
DIRIPPLE  
=
=
´
´
LOUT  
V
F
S
IN  
...(2)  
Symbol Used In Application Information:  
5V-1.6V 1.6v  
1
´
´
= 2.4A  
1.5uH  
5v 300kHz  
VIN  
- Input voltage  
- Output voltage  
- Output current  
VOUT  
IOUT  
Output Capacitor Selection  
∆VRIPPLE - Output voltage ripple  
- Working frequency  
Output capacitor is basically decided by the  
amount of the output voltage ripple allowed during steady  
state(DC) load condition as well as specification for the  
load transient. The optimum design may require a couple  
of iterations to satisfy both condition.  
FS  
∆IRIPPLE - Inductor current ripple  
Design Example  
The following is typical application for NX2114, the  
schematic is figure 2.  
VIN = 5V  
Based on DC Load Condition  
The amount of voltage ripple during the DC load  
condition is determined by equation(3).  
DIRIPPLE  
VOUT=1.6V  
DVRIPPLE = ESR´ DIRIPPLE  
+
...(3)  
8´ F ´ COUT  
IOUT=6A  
S
∆VRIPPLE <=20mV  
Where ESR is the output capacitors' equivalent  
series resistance,COUT is the value of output capacitors.  
Typically when large value capacitors are selected  
such as Aluminum Electrolytic,POSCAP and OSCON  
types are used, the amount of the output voltage ripple  
is dominated by the first term in equation(3) and the  
second term can be neglected.  
∆VDROOP<=60mV @ 6A step  
Output Inductor Selection  
The selection of inductor value is based on  
inductor ripple current, power rating, working frequency  
and efficiency. Larger inductor value normally means  
smaller ripple current. However if the inductance is  
chosen too large, it brings slow response and lower  
efficiency. Usually the ripple current ranges from 20%  
to 40% of the output current. This is a design freedom  
which can be decided by design engineer according to  
various application requirements. The inductor value  
can be calculated by using the following equations:  
For this example, POSCAP are chosen as output  
capacitors, the ESR and inductor current typically de-  
termines the output voltage ripple.  
DVRIPPLE  
DIRIPPLE  
20mV  
2.3A  
ESRdesire  
=
=
= 8.6mW  
...(4)  
If low ESR is required, for most applications, mul-  
tiple capacitors in parallel are better than a big capaci-  
tor. For example, for 20mV output ripple, POSCAP  
4TPE220MF with 15mW are chosen.  
V - VOUT  
V
OUT  
1
IN  
LOUT  
=
´
´
DIRIPPLE  
V
F
S
IN  
...(1)  
IRIPPLE = k´ IOUTPUT  
E S R E ´ DIR IPPLE  
N =  
...(5)  
where k is between 0.2 to 0.4.  
Select k=0.4, then  
D VR IPPLE  
Number of Capacitor is calculated as  
5V-1.6V 1.6V  
1
LOUT  
=
´
´
15mW´ 2.3A  
N =  
0.4´ 6A  
LOUT =1.51uH  
5V 300kHz  
20mV  
N =1.8  
Choose inductor from COILCRAFT DO3316P-152  
with L=1.5uH is a good choice.  
The number of capacitor has to be round up to a  
integer. Choose N =2.  
Current Ripple is recalculated as  
Rev. 4.0  
06/20/06  
8
NX2114/2114A  
If ceramic capacitors are chosen as output ca- voltage droop or overshoot is only dependent on the ESR  
pacitors, both terms in equation (3) need to be evaluated of output capacitor. For low frequency capacitor such  
to determine the overall ripple. Usually when this type of as electrolytic capacitor, the product of ESR and ca-  
capacitors are selected, the amount of capacitance per  
single unit is not sufficient to meet the transient specifi-  
cation, which results in parallel configuration of multiple  
capacitors.  
pacitance is high and L £ Lcrit is true. In that case, the  
transient spec is dependent on the ESR of capacitor.  
In most cases, the output capacitors are multiple  
capacitors in parallel. The number of capacitors can be  
calculated by the following  
For example, one 100uF, X5R ceramic capacitor  
with 2mW ESR is used. The amount of output ripple is  
ESRE ´ DIstep  
VOUT  
N =  
+
´ t 2  
...(9)  
2.3A  
DV  
2´ L´ CE ´ DV  
tran  
tran  
DVRIPPLE = 2mW´ 2.3A +  
8´ 300kHz´ 100uF  
where  
= 4.6mV +9.6mV =13.2mV  
0
if L £ Lcrit  
ì
Although this meets DC ripple spec, however it  
needs to be studied for transient requirement.  
Based On Transient Requirement  
Typically, the output voltage droop during transient  
is specified as:  
ï
L´ DI  
t =  
í
ï
î
step  
...(10)  
- ESRE ´ CE  
if L ³ Lcrit  
VOUT  
For example, assume voltage droop during tran-  
sient is 100mV for 6A load step.  
DVDROOP <DVTRAN @ step load ∆ISTEP  
If the POSCAP 2R5TPE220MC (220uF, 12mW ) is  
used, the critical inductance is given as  
During the transient, the voltage droop during the  
transient is composed of two sections. One Section is  
dependent on the ESR of capacitor, the other section is  
a function of the inductor, output capacitance as well as  
input, output voltage. For example, for the overshoot,  
when load from high load to light load with a ∆ISTEP tran-  
sient load, if assuming the bandwidth of system is high  
enough, the overshoot can be estimated as the following  
equation.  
ESRE ´ CE ´ VOUT  
Lcrit  
=
=
DIstep  
15mW´ 220mF´ 1.6V  
= 0.88mH  
6A  
The selected inductor is 1.5uH which is bigger than  
critical inductance. In that case, the output voltage tran-  
sient not only dependent on the ESR, but also capaci-  
tance.  
VOUT  
´ t 2  
number of capacitors is  
DVovershoot = ESR ´ DIstep  
+
...(6)  
2´ L´ COUT  
where is the a function of capacitor, etc.  
L ´ DIstep  
t
t =  
- ESRE ´ CE  
VOUT  
0
if L £ Lcrit  
ì
ï
1.5mH ´ 6A  
=
- 15mW´ 220mF = 2.3us  
t = L´ DI  
í
1.6V  
step  
...(7)  
...(8)  
- ESR ´ COUT  
if L ³ Lcrit  
ï
VOUT  
î
ESRE ´ DIstep  
VOUT  
where  
ESR ´ COUT ´ VOUT ESRE ´ CE ´ VOUT  
N =  
+
´ t 2  
DV  
2´ L´ CE ´ DV  
tran  
tran  
Lcrit  
=
=
15mW´ 6A  
DIstep  
DIstep  
=
+
60mV  
where ESRE and CE represents ESR and capaci-  
tance of each capacitor if multiple capacitors are used  
in parallel.  
1.6V  
´ 2.3us2  
2´ 1.5mH´ 220mF´ 60mV  
=1.7  
The above equation shows that if the selected out-  
put inductor is smaller than the critical inductance, the  
The number of capacitors has to satisfied both ripple  
and transient requirement. Overall, we can choose N=2.  
Rev. 4.0  
06/20/06  
9
NX2114/2114A  
It should be considered that the proposed equa-  
tion is based on ideal case, in reality, the droop or over-  
shoot is typically more than the calculation. The equa-  
tion gives a good start. For more margin, more capaci-  
tors have to be chosen after the test. Typically, for high  
frequency capacitor such as high quality POSCAP es-  
pecially ceramic capacitor, 20% to 100% (for ceramic)  
more capacitors have to be chosen since the ESR of  
capacitors is so low that the PCB parasitic can affect  
the results tremendously. More capacitors have to be  
selected to compensate these parasitic parameters.  
1
FZ1  
FZ2  
=
=
=
=
...(11)  
2´ p ´ R4 ´ C2  
1
...(12)  
...(13)  
...(14)  
2´ p ´ (R2 + R3 )´ C3  
1
F
P1  
2´ p ´ R3 ´ C3  
1
F
P2  
C1 ´ C2  
2´ p ´ R4 ´  
C1 + C2  
where FZ1,FZ2,FP1 and FP2 are poles and zeros in  
the compensator. Their locations are shown in figure 10.  
The transfer function of type III compensator for  
transconductance amplifier is given by:  
Compensator Design  
Due to the double pole generated by LC filter of the  
power stage, the power system has 180o phase shift ,  
and therefore, is unstable by itself. In order to achieve  
accurate output voltage and fast transient response,  
compensator is employed to provide highest possible  
bandwidth and enough phase margin. Ideally, the Bode  
plot of the closed loop system has crossover frequency  
between 1/10 and 1/5 of the switching frequency, phase  
margin greater than 50o and the gain crossing 0dB with -  
20dB/decade. Power stage output capacitors usually  
decide the compensator type. If electrolytic capacitors  
are chosen as output capacitors, type II compensator  
can be used to compensate the system, because the  
zero caused by output capacitor ESR is lower than cross-  
over frequency. Otherwise type III compensator should  
be chosen.  
Ve  
1- gm ´ Zf  
=
VOUT  
1+ gm ´ Zin + Zin /R1  
For the voltage amplifier, the transfer function of  
compensator is  
Ve  
- Zf  
=
VOUT  
Zin  
To achieve the same effect as voltage amplifier,  
the compensator of transconductance amplifier must  
satisfy this condition: R4>>2/gm. R1||R2||R3>>1/gm  
is desirable.  
Zf  
Vout  
Zin  
R3  
C1  
A. Type III compensator design  
C2  
R4  
R2  
R1  
For low ESR output capacitors, typically such as  
Sanyo oscap and poscap, the frequency of ESR zero  
caused by output capacitors is higher than the cross-  
over frequency. In this case, it is necessary to compen-  
sate the system with type III compensator. The follow-  
ing figures and equations show how to realize the type III  
compensator by transconductance amplifier.  
C3  
Fb  
Ve  
gm  
Vref  
Figure 9 - Type III compensator using  
transconductance amplifier  
Rev. 4.0  
06/20/06  
10  
NX2114/2114A  
FO=30kHz.  
C3 =  
1
1
1
)
´ (  
-
power stage  
2´ p ´ R2  
F
F
z2  
p1  
LC  
F
1
1
1
=
´ (  
-
)
40dB/decade  
2´ p ´ 10kW 6.2kHz 48kHz  
=2.2nF  
VOSC 2´ p ´ FO ´ L  
R4 =  
=
´
´ Cout  
loop gain  
V
C3  
1.7V 2´ p ´ 30kHz´ 1.5uH  
in  
ESR  
F
´
´ 440uF  
5V  
=19.2kW  
2.2nF  
20dB/decade  
Choose C3=2.2nF, R4=22.1kW.  
compensator  
5. Calculate C2 with zero Fz1 at 75% of the LC  
double pole by equation (11).  
1
FZ1  
FO  
FP2  
FZ2  
FP1  
C2 =  
2´ p ´ FZ1 ´ R4  
1
=
2´ p ´ 0.75´ 6.2kHz´ 22.1kW  
= 1.55nF  
Figure 10 - Bode plot of Type III compensator  
Design example for type III compensator are in  
order. The crossover frequency has to be selected as  
FLC<FO<FESR, and FO<=1/10~1/5Fs.  
Choose C2=1.5nF.  
6. Calculate C1 by equation (14) with pole Fp2 at  
half the switching frequency.  
1. Calculate the location of LC double pole FLC  
1
C1 =  
and ESR zero FESR  
.
2´ p ´ R4 ´ F  
P2  
1
1
F
=
=
=
LC  
2´ p ´ 22.1kW´ 150kHz  
= 48pF  
2´ p ´  
L
OUT ´ COUT  
1
2´ p ´ 1.5uH´ 440uF  
Choose C1=47pF.  
= 6.2kHz  
7. Calculate R3 by equation (13).  
1
1
R3 =  
F
=
ESR  
2´ p ´ F ´ C3  
2´ p ´ ESR´ COUT  
P1  
1
1
=
=
2´ p ´ 48kHz´ 2.2nF  
= 1.5kW  
2´ p ´ 7.5mW´ 440uF  
= 48kHz  
2. Set R2 equal to10.2kW, then R1= 10.2kW.  
3. Set zero FZ2 = FLC and Fp1 =FESR  
Choose R3=1.5kW.  
.
4. Calculate R4 and C3 with the crossover  
frequency at 1/10~ 1/5 of the switching frequency. Set  
Rev. 4.0  
06/20/06  
11  
NX2114/2114A  
Vout  
B. Type II compensator design  
If the electrolytic capacitors are chosen as power  
stage output capacitors, usually the Type II compensa-  
tor can be used to compensate the system.  
Type II compensator can be realized by simple  
RC circuit without feedback as shown in figure 12. R3  
and C1 introduce a zero to cancel the double pole  
effect. C2 introduces a pole to suppress the switching  
noise. The following equations show the compensator  
pole zero location and constant gain.  
R2  
Fb  
Ve  
gm  
R1  
R3  
C2  
Vref  
C1  
Figure 12 - Type II compensator with  
transconductance amplifier  
R1  
Gain=gm ´  
´ R3  
... (15)  
... (16)  
... (17)  
R1+R2  
1
F =  
z
For this type of compensator, FO has to satisfy  
FLC<FESR<<FO<=1/10~1/5Fs.  
2´ p ´ R3 ´ C1  
1
F »  
p
The following uses typical design in figure 19 as  
an example for type II compensator design, two 680uF  
with 41mW electrolytic capacitors are used.  
1.Calculate the location of LC double pole FLC  
2´ p ´ R3 ´ C2  
and ESR zero FESR  
.
power stage  
1
F
=
=
40dB/decade  
LC  
2´ p ´  
L
OUT ´ COUT  
1
loop gain  
2´ p ´ 1.5uH´ 1360uF  
= 3.5kHz  
20dB/decade  
1
F
=
ESR  
2´ p ´ ESR´ COUT  
1
=
compensator  
2´ p ´ 20.5mW´ 1360uF  
Gain  
= 5.7kHz  
2.Set R2 equal to10.2kW. Using equation 18, the  
final selection of R1 is 3.24kW.  
P
F
F
F
Z
LCFESR  
FO  
3. Set crossover frequency at 1/10~ 1/5 of the  
swithing frequency, here FO=30kHz.  
4.Calculate R3 value by the following equation.  
Figure 11- Bode plot of Type II compensator  
Rev. 4.0  
06/20/06  
12  
NX2114/2114A  
1.6V, the result of R1 is 10kW.  
VOSC 2´ p ´ F ´ L  
R1+R2  
R1  
Vout  
1
O
R3 =  
´
´
´
V
RESR  
gm  
in  
R2  
1.7V 2´ p ´ 30kHz´ 1.5uH  
1
Fb  
=
´
´
12  
20.5W  
10.2kW+3.24kW  
3.24kW  
1.9mA/V  
´
R1  
Vref  
=4.23kW  
Choose R3 =4.53kW.  
Voltage divider  
5. Calculate C1 by setting compensator zero FZ  
at 75% of the LC double pole.  
Figure 13 - Voltage divider  
In general, the minimum output load impedance  
including the resistor divider should be less than 5kW to  
prevent overcharge the output voltage by leakage cur-  
rent (e.g. Error Amplifier feedback pin bias current). A  
minimum load for 5kW less (<1/16w for most of applica-  
tion) is recommended to put at the output. For example,  
in this application,  
1
C1=  
2´ p ´ R3 ´ F  
z
1
=
2´ p ´ 4.51kW´ 0.75´ 3.5kHz  
=13.3nF  
Choose C1=12nF.  
F
6. Calculate C2 by setting compensator pole  
at half the swithing frequency.  
p
Vout=1.6V  
The power loss is 1/16W less  
1
RLOAD = 1.6V ´ 1.6V /(1/16W) = 40W  
C2 =  
p ´ R3 ´ F  
s
Select minimum load, 1kW should be good enough.  
1
=
p ´ 3.74kW´ 300kHz  
Input Capacitor Selection  
=235pF  
Input capacitors are usually a mix of high frequency  
ceramic capacitors and bulk capacitors. Ceramic ca-  
pacitors bypass the high frequency noise, and bulk ca-  
pacitors supply current to the MOSFETs. Usually 1uF  
ceramic capacitor is chosen to decouple the high fre-  
quency noise. The bulk input capacitors are decided by  
voltage rating and RMS current rating. The RMS current  
in the input capacitors can be calculated as:  
Choose C2=220pF.  
Output Voltage Calculation  
Output voltage is set by reference voltage and  
external voltage divider. The reference voltage is fixed  
at 0.8V. The divider consists of two ratioed resistors  
so that the output voltage applied at the Fb pin is 0.8V  
when the output voltage is at the desired value. The  
following equation and picture show the relationship  
between VOUT , VREF and voltage divider.  
IRMS = IOUT  
´
D ´ 1-D  
VOUT  
...(19)  
D =  
V
IN  
VIN = 5V, VOUT=1.6V, IOUT=6A, using equation  
(19), the result of input RMS current is 2.80A.  
R 2 ´ VREF  
R1=  
...(18)  
VOUT -VREF  
For higher efficiency, low ESR capacitors are rec-  
ommended. One Sanyo TPD series POSCAP 6TPD220M  
6V 220uF with 12mW is chosen as input bulk capacitor.  
where R2 is part of the compensator, and the  
value of R1 value can be set by voltage divider.  
Choose R2=10kW, to set the output voltage at  
Rev. 4.0  
06/20/06  
13  
NX2114/2114A  
dependent.  
Power MOSFETs Selection  
The NX2114 requires two N-Channel power  
MOSFETs. The selection of MOSFETs is based on  
maximum drain source voltage, gate source voltage,  
maximum current rating, MOSFET on resistance and  
power dissipation. The main consideration is the power  
loss contribution of MOSFETs to the overall converter  
efficiency. In this design example, two Fairchild FDS6294  
are used. They have the following parameters: VDS=30V,  
ID =13A, RDSON =14.4mW,QGATE =10nC.  
Soft Start, Enable and shut Down  
The NX2114 has a digital start up. It is based on  
digital counter with 1024 cycles. For NX2114 with 300kHz  
operation, the start up time is about 3.5ms. For NX2114A  
with 600kHz operation, the start up time is about half of  
NX2114, 1.75mS.  
NX2114/NX2114A can be enabled or disabled by  
pulling COMP pin below 0.3V. The function is illustrated  
in the following diagram. During the normal operation,  
the lowest COMP voltage is clamped to be about 700mV  
, the COMP voltage is higher than 0.3V. If external switch  
with 10W Rdson or less to pull down COMP pin, when  
COMP is below 0.3V, the digital soft start will be reset to  
zero. All the drivers will be off. The synchronous buck is  
shut off. When external switch is released, and COMP  
is above 0.3V, a soft start will initiates and system starts  
from the beginning.  
There are three factors causing the MOSFET power  
loss: conduction loss, switching loss and gate driver loss.  
Gate driver loss is the loss generated by discharg-  
ing the gate capacitor and is dissipated in driver circuits.  
It is proportional to frequency and is defined as:  
...(20)  
Pgate = (QHGATE ´ VHGS + QLGATE ´ VLGS )´ FS  
where QHGATE is the high side MOSFETs gate  
charge, QLGATE is the low side MOSFETs gate charge,  
VHGS is the high side gate source voltage, and VLGS is  
the low side gate source voltage.  
According to equation (20), PGATE =0.03W. This  
power dissipation should not exceed maximum power  
dissipation of the driver device.  
Conduction loss is simply defined as:  
2114  
Shut  
down  
2
PH C O N =IO U T ´ D ´ R D S ( O N ) ´ K  
FB  
2
PL C O N =IO U T ´ (1 - D ) ´ R D S (O N ) ´ K  
Compensation  
Network  
PT O T A L =PH C O N + PL C O N  
...(21)  
0.3V  
where the RDS(ON) will increases as MOSFET junc-  
tion temperature increases, K is RDS(ON) temperature  
dependency. As a result, RDS(ON) should be selected for  
the worst case, in which K equals to 1.43 at 125oC  
according to FDS6294 datasheet. Using equation (21),  
the result of PTOTAL is 0.75W. Conduction loss should  
not exceed package rating or overall system thermal  
budget.  
comp  
0.6  
OFF  
ON  
1.3V  
Clamp  
Figure 14 - Enable and Shut down NX2114 by  
pulling down COMP pin.  
Switching loss is mainly caused by crossover con-  
duction at the switching transition. The total switching  
Feedback Under Voltage Shut Down  
NX2114 relies on the Feedback Under Voltage Lock  
Out (FB UVLO ) to provide short circuit protection. Ba-  
sically, NX2114 has a comparator compare the feedback  
voltage with the FB UVLO threshold 0.4V.  
loss can be approximated.  
1
PSW  
=
´ VIN ´ IOUT ´ TSW ´ FS  
...(22)  
2
where IOUT is output current, TSW is swithing time,and FS  
is switching frequency. Swithing loss PSW is frequency  
Rev. 4.0  
06/20/06  
14  
NX2114/2114A  
During the normal operation, if the output is short,  
the feedback voltage will be lower than 0.4V and com-  
parator will change the state.After certain internal delay,  
both high side and low side driver will be turned off. The  
output will be latched. The normal operation should be  
achieved by removing the short and recycle the VCC.  
age Lock Out comparator is disabled. After half of start  
up time, the Feedback UVLO comparator is enabled.  
The FB UVLO threshold is set to be half of voltage at the  
positive input of error amplifier. With this set up, if the  
output is short before soft start, the Feedback UVLO  
comparator can catch it and turn off the driver. The short  
circuit operation waveform during normal operation and  
during the soft start are shown as follows.  
During the normal operation, Feedback UVLO  
will take the role. But during the soft start, due to the  
input voltage dropping, UVLO Vcc will take the role,  
hiccup happens.  
The Feedback UVLO can provide short circuit pro-  
tection under certain conditions. However, since feed-  
back does not have accurate information of current, this  
protection only provides certain level of over current pro-  
tection. MOSFET should design such that it can survive  
with high pulse current for a short period of time.  
Layout Considerations  
Figure 15 - Operation waveforms during short con-  
dition.  
The layout is very important when designing high  
frequency switching converters. Layout will affect noise  
pickup and can cause a good design to perform with  
less than expected results.  
CH3-bus voltage  
5V/DIV  
There are two sets of components considered in  
the layout which are power components and small sig-  
nal components. Power components usually consist of  
input capacitors, high-side MOSFET, low-side MOSFET,  
inductor and output capacitors. A noisy environment is  
generated by the power components due to the switch-  
ing power. Small signal components are connected to  
sensitive pins or nodes. A multilayer layout which in-  
cludes power plane, ground plane and signal plane is  
recommended .  
CH2-Vcc voltage  
5V/DIV  
CH1-Fb voltage  
0.5V/DIV  
CH4-output current  
10A/DIV  
Layout guidelines:  
1. First put all the power components in the top  
layer connected by wide, copper filled areas. The input  
capacitor, inductor, output capacitor and the MOSFETs  
should be close to each other as possible. This helps to  
reduce the EMI radiated by the power loop due to the  
high switching currents through them.  
Figure 16 - Operation waveform with start up at  
short.  
During the start up, the output voltage is discharged  
to zero by the synchronous FET. FB voltage starts in-  
crease from zero when digital start block operates. Be-  
fore half of the start up time, the Feedback Under Volt-  
2. Low ESR capacitor which can handle input RMS  
ripple current and a high frequency decoupling ceramic  
Rev. 4.0  
06/20/06  
15  
NX2114/2114A  
cap which usually is 1uF need to be practically touch-  
ing the drain pin of the upper MOSFET, a plane connec-  
tion is a must.  
3. The output capacitors should be placed as close  
as to the load as possible and plane connection is re-  
quired.  
4. Drain of the low-side MOSFET and source of  
the high-side MOSFET need to be connected thru a plane  
ans as close as possible.A snubber nedds to be placed  
as close to this junction as possible.  
5. Source of the lower MOSFET needs to be con-  
nected to the GND plane with multiple vias. One is not  
enough. This is very important. The same applies to the  
output capacitors and input capacitors.  
6. Hdrv and Ldrv pins should be as close to  
MOSFET gate as possible. The gate traces should be  
wide and short. A place for gate drv resistors is needed  
to fine tune noise if needed.  
7. Vcc capacitor, BST capacitor or any other by-  
passing capacitor needs to be placed first around the IC  
and as close as possible. The capacitor on comp to  
GND or comp back to FB needs to be place as close to  
the pin as well as resistor divider.  
8. The output sense line which is sensing output  
back to the resistor divider should not go through high  
frequency signals.  
9. All GNDs need to go directly thru via to GND  
plane.  
10. The feedback part of the system should be  
kept away from the inductor and other noise sources,  
and be placed close to the IC.  
11. In multilayer PCB, separate power ground and  
analog ground. These two grounds must be connected  
together on the PC board layout at a single point. The  
goal is to localize the high current path to a separate  
loop that does not interfere with the more sensitive ana-  
log control function.  
Rev. 4.0  
06/20/06  
16  
NX2114/2114A  
TYPICAL APPLICATION  
Single Supply 5V Input  
L2 1uH  
Vin  
+5V  
C5  
1uF  
R3  
10  
Cin  
C4  
33uF  
D1 MBR0530T1  
2 x (470uF,60mohm)  
C3  
C6  
1uF  
33uF  
1
5
C7  
0.1uF  
BST  
Vcc  
Comp  
7
2
8
4
M1  
L1 1.5uH  
Hdrv  
C2  
8.2nF  
Vout  
C1  
150pF  
SW  
R4  
7k  
+2.5V,10A  
Co  
4 x (330uF,80mohm)  
6
M2  
Ldrv  
Fb  
Gnd  
3
R1  
10k 1%  
R2  
4.7k 1%  
Figure 17 - Application of NX2114 for 5V input and 2.5V output with electrolytic capacitors  
L2 1uH  
Vin  
+5V  
C5  
1uF  
Cin  
3 x 22uF  
X7R  
R3  
10  
C4  
22uF  
D1  
C6  
1uF  
MBR0530T1  
C3  
22uF  
1
5
BST  
Vcc  
C7  
0.1uF  
7
2
8
4
M1  
L1 3.3uH  
Comp  
Fb  
Hdrv  
C2  
330pF  
Vout  
C1  
4.7pF  
SW  
R4  
k
+1.2V,4A  
Co  
120  
10 x 22uF  
6
M2  
X7R  
Ldrv  
Gnd  
3
R1  
10k 1%  
R2  
20k 1%  
R3  
787  
C3  
820pF  
Figure 18 - Application of NX2114 A for 5V input and 1.2V output with ceramic output capacitors  
Rev. 4.0  
06/20/06  
17  
NX2114/2114A  
TYPICALAPPLICATIONS(CONT')  
Dual power supply (+5V BIAS,+12V BUS)  
L2 1uH  
Vin  
+12V  
C3  
33uF  
C5  
1uF  
Cin  
2 x (47uF,60mohm)  
D1 MBR0530T1  
Vin  
C6  
1uF  
+5V  
5
1
C4  
0.1uF  
BST  
Vcc  
R8 1  
k
7
2
8
4
M1  
L1 1.5uH  
Comp  
Hdrv  
R7 5  
k
C2  
C1  
270pF  
R5 10  
k
15nF  
Vout  
SW  
2N3904  
2N3904  
R4  
3.74  
+3.3V,10A  
Co  
k
6
2 x (680uF,41mohm)  
M2  
R6 680  
Ldrv  
Fb  
Gnd  
3
R1 10.2 k 1%  
R2  
3.24 k 1%  
Figure 19 -Application of NX2114 for 5V bias and 12V input bus  
Single power supply (+11V to +24V BUS)  
L2 1uH  
Vin  
+11~25V  
C4  
33uF  
R5  
k
C5  
1uF  
Cin  
3
2 x (47uF,60mohm)  
2N3904  
R6  
10  
D1 MBR0530T1  
k
C6  
2.2uF  
TL431  
5
1
R7  
10  
C7  
0.1uF  
k
Vcc  
Comp  
BST  
M1  
L1 5uH  
7
2
8
4
Hdrv  
C2  
2.7nF  
Vout  
C1  
220pF  
SW  
R4  
+1.6V,5A  
Co  
15  
k
2 x (680uF,41mohm)  
6
M2  
Ldrv  
Fb  
Gnd  
3
R1  
10k 1%  
R2  
10 k 1%  
R3  
787  
C3  
1nF  
Figure 20 -Application of NX2114 for high input bus application  
Rev. 4.0  
06/20/06  
18  
NX2114/2114A  
SOIC8 PACKAGE OUTLINE DIMENSIONS  
Rev. 4.0  
06/20/06  
19  
NX2114/2114A  
Rev. 4.0  
06/20/06  
20  
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