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NX2119CSTR

型号：

NX2119CSTR

描述：

与限流保护同步PWM控制器[ SYNCHRONOUS PWM CONTROLLER WITH CURRENT LIMIT PROTECTION ]

品牌：

MICROSEMI[ Microsemi ]

页数：

16 页

PDF大小：

499 K

下载PDF手册
Evaluation board available.  
NX2119/2119A  
SYNCHRONOUS PWM CONTROLLER WITH  
CURRENT LIMIT PROTECTION  
PRELIMINARY DATA SHEET  
Pb Free Product  
FEATURES  
DESCRIPTION  
n
Bus voltage operation from 2V to 25V  
The NX2119 controller IC is a synchronous Buck con-  
troller IC designed for step down DC to DC converter  
applications. It is optimized to convert bus voltages from  
2V to 25V to outputs as low as 0.8V voltage. The  
NX2119 operates at fixed 300kHz, while NX2119A oper-  
ates at fixed 600kHz, making it ideal for applications  
requiring ceramic output capacitors. The NX2119 em-  
ploys fixed loss-less current limiting by sensing the Rdson  
of synchronous MOSFET followed by latch out feature.  
Feedback under voltage triggers Hiccup.  
n Fixed 300kHz and 600kHz  
n Internal Digital Soft Start Function  
n Prebias Startup  
n Less than 50 nS adaptive deadband  
n
n
Current limit triggers latch out by sensing Rdson of  
Synchronous MOSFET  
No negative spike at Vout during startup and  
shutdown  
n Pb-free and RoHS compliant  
Other features of the device are: 5V gate drive,Adaptive  
deadband control, Internal digital soft start, Vcc n Graphic Card on board converters  
undervoltage lock out and shutdown capability via the n Memory Vddq Supply  
APPLICATIONS  
comp pin.  
n
On board DC to DC such as  
12V to 3.3V, 2.5V or 1.8V  
ADSL Modem  
n
TYPICAL APPLICATION  
L2 1uH  
Vin  
+5V  
C4  
100uF  
C5  
1uF  
Cin  
280uF  
18mohm  
R5  
10  
D1  
MBR0530T1  
C3  
1uF  
5
1
C6  
0.1uF  
Vcc  
BST  
M1  
2
Hdrv  
7
6
COMP  
M3  
L1 1.5uH  
HI=SD  
Vout  
R4  
37.4k  
8
4
SW  
Ldrv  
+1.8V 9A  
Co  
C7  
27pF  
R1  
4k  
2 x (1500uF,13mohm)  
M2  
C2  
2.2nF  
R2  
FB  
C1  
4.7nF  
10k  
Gnd  
3
R3  
8k  
Figure1 - Typical application of 2119  
ORDERING INFORMATION  
Device  
Temperature  
0 to 70oC  
Package  
SOIC - 8L  
SOIC - 8L  
MSOP - 8L  
Frequency  
300kHz  
600kHz  
Pb-Free  
Yes  
Yes  
NX2119CSTR  
NX2119ACSTR  
NX2119ACUTR  
0 to 70o C  
0 to 70o C  
600kHz  
Yes  
Rev.3.2  
04/10/08  
1
NX2119/2119A  
ABSOLUTE MAXIMUM RATINGS  
VCC to GND & BST to SW voltage .................... -0.3V to 6.5V  
BST to GND Voltage ........................................ -0.3V to 35V  
SW to GND ...................................................... -2V to 35V  
All other pins .................................................... -0.3V to VCC+0.3V or 6.5V  
Storage Temperature Range ............................... -65oC to 150oC  
Operating Junction Temperature Range ............... -40oC to 125oC  
ESD Susceptibility ........................................... 2kV  
CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to  
the device. This is a stress only rating and operation of the device at these or any other conditions above those  
indicated in the operational sections of this specification is not implied.  
PACKAGE INFORMATION  
8-LEAD PLASTIC SOIC(S)  
8-LEAD PLASTIC MSOP  
qJA » 130o C/W  
qJA » 216o C/W  
BST  
HDrv  
Gnd  
1
2
3
4
8
7
6
5
SW  
Comp  
Fb  
1
8
7
6
5
SW  
Comp  
Fb  
BST  
HDrv  
Gnd  
2
3
4
LDrv  
Vcc  
LDrv  
Vcc  
ELECTRICAL SPECIFICATIONS  
Unless otherwise specified, these specifications apply over Vcc = 5V, and TA= 0 to 70oC. Typical values refer to Ta  
= 25oC. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient  
temperature.  
PARAMETER  
Reference Voltage  
Ref Voltage  
SYM  
Test Condition  
Min  
TYP  
MAX Units  
VREF  
0.8  
0.2  
V
Ref Voltage line regulation  
Supply Voltage(Vcc)  
VCC Voltage Range  
VCC Supply Current (Static)  
VCC Supply Current  
(Dynamic)  
%
VCC  
5
3
V
4.5  
5.5  
ICC (Static) Outputs not switching  
mA  
mA  
ICC  
(Dynamic)  
CLOAD=3300pF FS=300kHz  
TBD  
Supply Voltage(VBST  
)
VBST Supply Current (Static)  
IBST (Static) Outputs not switching  
0.2  
mA  
mA  
VBST Supply Current  
(Dynamic)  
IBST  
CLOAD=3300pF FS=300kHz  
TBD  
(Dynamic)  
Rev.3.2  
04/10/08  
2
NX2119/2119A  
PARAMETER  
Under Voltage Lockout  
VCC-Threshold  
SYM  
TEST CONDITION  
MIN  
TYP  
MAX UNITS  
VCC_UVLO VCC Rising  
VCC_Hyst VCC Falling  
4
V
V
3.8  
4.2  
VCC-Hysteresis  
0.2  
Oscillator (Rt)  
Frequency  
FS  
2119  
300  
600  
1.5  
93  
kHz  
kHz  
V
2119A  
Ramp-Amplitude Voltage  
Max Duty Cycle  
VRAMP  
%
Min Duty Cycle  
0
%
Min LDRV on time  
Controllable Min on time  
Error Amplifiers  
250  
100  
nS  
nS  
Transconductance  
Input Bias Current  
Comp SD Threshold  
2000  
10  
umho  
nA  
Ib  
0.3  
V
Soft Start  
Soft Start time  
Tss  
FS=300kHz  
6.8  
0.9  
mS  
ohm  
ohm  
High Side  
Output Impedance , Sourcing Rsource(Hdrv)  
Current  
I=200mA  
Output Impedance , Sinking  
Current  
Rsink(Hdrv)  
I=200mA  
0.65  
Rise Time  
THdrv(Rise)  
THdrv(Fall)  
VBST-VSW=4.5V  
VBST-VSW=4.5V  
50  
50  
30  
ns  
ns  
ns  
Fall Time  
Deadband Time  
Tdead(L to Ldrv going Low to Hdrv going  
H)  
High, 10%-10%  
Low Side Driver  
(CL=3300pF)  
Output Impedance, Sourcing Rsource(Ldrv)  
I=200mA  
I=200mA  
0.9  
0.5  
50  
50  
30  
ohm  
ohm  
ns  
Output Impedance, Sinking  
Rise Time  
Rsink(Ldrv)  
TLdrv(Rise)  
TLdrv(Fall)  
10% to 90%  
90% to 10%  
Fall Time  
ns  
Deadband Time  
Tdead(H to SW going Low to Ldrv going  
L) High, 10% to 10%  
ns  
OCP  
OCP voltage  
320  
mV  
Rev.3.2  
04/10/08  
3
NX2119/2119A  
PIN DESCRIPTIONS  
PIN #  
PIN SYMBOL  
PIN DESCRIPTION  
Power supply voltage. A high freq 1uF ceramic capacitor is placed as close as  
possible to and connected to this pin and ground pin.  
5
VCC  
This pin supplies voltage to high side FET driver. A high freq 0.1uF ceramic capaci-  
tor is placed as close as possible to and connected to these pins and respected  
SW pins.  
1
3
6
BST  
GND  
FB  
Ground pin.  
This pin is the error amplifier inverting input. This pin is connected via resistor divider  
to the output of the switching regulator to set the output DC voltage. When FB pin  
voltage is lower than 0.6V, hiccup circuit starts to recycle the soft start circuit after  
2048 switching cycles.  
This pin is the output of the error amplifier and together with FB pin is used to  
compensate the voltage control feedback loop. This pin is also used as a shut down  
pin. When this pin is pulled below 0.3V, both drivers are turned off and internal soft  
start is reset.  
7
COMP  
This pin is connected to source of high side FET and provides return path for the  
high side driver. It is also used to hold the low side driver low until this pin is brought  
low by the action of high side turning off. LDRV can only go high if SW is below 1V  
threshold .  
8
SW  
2
4
HDRV  
LDRV  
High side gate driver output.  
Low side gate driver output.  
Rev.3.2  
04/10/08  
4
NX2119/2119A  
BLOCK DIAGRAM  
VCC  
FB  
Hiccup Logic  
0.6V  
1.25V  
0.8V  
OC  
Bias  
Generator  
BST  
UVLO  
POR  
START  
HDRV  
SW  
COMP  
0.3V  
OC  
Control  
Logic  
START  
0.8V  
VCC  
PWM  
OSC  
ramp  
Digital  
start Up  
S
R
LDRV  
Q
FB  
0.6V  
CLAMP  
1.3V  
CLAMP  
320mV  
COMP  
latch out  
START  
OCP  
comparator  
GND  
Figure 2 - Simplified block diagram of the NX2119  
Rev.3.2  
04/10/08  
5
NX2119/2119A  
APPLICATION INFORMATION  
V -VOUT VOUT  
1
IN  
DIRIPPLE  
=
=
´
´
LOUT  
V
F
Symbol Used In Application Information:  
IN  
S
...(2)  
VIN  
- Input voltage  
- Output voltage  
- Output current  
5V-1.8V 1.8v  
1
´
´
= 2.56A  
1.5uH  
5v 300kHz  
VOUT  
IOUT  
∆VRIPPLE - Output voltage ripple  
- Working frequency  
Output Capacitor Selection  
FS  
Output capacitor is basically decided by the  
amount of the output voltage ripple allowed during steady  
state(DC) load condition as well as specification for the  
load transient. The optimum design may require a couple  
of iterations to satisfy both condition.  
∆IRIPPLE - Inductor current ripple  
Design Example  
The following is typical application for NX2119, the  
Based on DC Load Condition  
schematic is figure 1.  
VIN = 5V  
The amount of voltage ripple during the DC load  
condition is determined by equation(3).  
VOUT=1.8V  
DIRIPPLE  
FS=300kHz  
DVRIPPLE = ESR´ DIRIPPLE  
+
...(3)  
8´ F ´ COUT  
IOUT=9A  
S
∆VRIPPLE <=20mV  
∆VDROOP<=100mV @ 9A step  
Where ESR is the output capacitors' equivalent  
series resistance,COUT is the value of output capacitors.  
Typically when large value capacitors are selected  
such as Aluminum Electrolytic,POSCAP and OSCON  
types are used, the amount of the output voltage ripple  
is dominated by the first term in equation(3) and the  
second term can be neglected.  
Output Inductor Selection  
The selection of inductor value is based on induc-  
tor ripple current, power rating, working frequency and  
efficiency. Larger inductor value normally means smaller  
ripple current. However if the inductance is chosen too  
large, it brings slow response and lower efficiency. Usu-  
ally the ripple current ranges from 20% to 40% of the  
output current. This is a design freedom which can be  
decided by design engineer according to various appli-  
cation requirements. The inductor value can be calcu-  
lated by using the following equations:  
For this example, POSCAP are chosen as output  
capacitors, the ESR and inductor current typically de-  
termines the output voltage ripple.  
DVRIPPLE  
DIRIPPLE  
20mV  
2.56A  
ESRdesire  
=
=
= 7.8mW  
...(4)  
If low ESR is required, for most applications, mul-  
tiple capacitors in parallel are better than a big capaci-  
tor. For example, for 20mV output ripple, POSCAP  
2R5TPE220MC with 12mW are chosen.  
V -VOUT VOUT  
1
IN  
LOUT  
=
´
´
DIRIPPLE  
V
F
S
IN  
...(1)  
IRIPPLE =k ´ IOUTPUT  
E S R E ´ DIR IPPLE  
N =  
where k is between 0.2 to 0.4.  
Select k=0.3, then  
...(5)  
D VR IPPLE  
Number of Capacitor is calculated as  
5V-1.8V 1.8V  
1
LOUT  
=
´
´
12mW´ 2.56A  
N =  
0.3´ 9A  
LOUT =1.4uH  
5V 300kHz  
20mV  
N =1.5  
Choose inductor from COILCRAFT DO5010P-  
152HC with L=1.5uH is a good choice.  
Current Ripple is recalculated as  
The number of capacitor has to be round up to a  
integer. Choose N =2.  
If ceramic capacitors are chosen as output ca  
Rev.3.2  
04/10/08  
6
NX2119/2119A  
pacitors, both terms in equation (3) need to be evalu- of output capacitor. For low frequency capacitor such  
ated to determine the overall ripple. Usually when this as electrolytic capacitor, the product of ESR and ca-  
type of capacitors are selected, the amount of capaci-  
tance per single unit is not sufficient to meet the tran-  
sient specification, which results in parallel configura-  
tion of multiple capacitors .  
pacitance is high and L £ Lcrit is true. In that case, the  
transient spec is dependent on the ESR of capacitor.  
In most cases, the output capacitors are multiple  
capacitors in parallel. The number of capacitors can be  
calculated by the following  
For example, one 100uF, X5R ceramic capacitor  
with 2mW ESR is used. The amount of output ripple is  
ESRE ´ DIstep  
VOUT  
N =  
+
´ t 2  
...(9)  
2.56A  
DV  
2´ L´ CE ´ DV  
tran  
tran  
DV  
= 2mW´ 2.56A +  
=15mV  
RIPPLE  
8´ 300kHz´ 100uF  
where  
0
if L £ Lcrit  
ì
Although this meets DC ripple spec, however it  
needs to be studied for transient requirement.  
Based On Transient Requirement  
ï
L´ DI  
t =  
í
ï
î
step  
...(10)  
- ESRE ´ CE  
if L ³ Lcrit  
VOUT  
Typically, the output voltage droop during transient  
is specified as:  
For example, assume voltage droop during tran-  
sient is 100mV for 9A load step.  
DVDROOP <DVTRAN @ step load ∆ISTEP  
If the POSCAP 2R5TPE220MC(220uF, 12mW ) is  
used, the critical inductance is given as  
During the transient, the voltage droop during the  
transient is composed of two sections. One Section is  
dependent on the ESR of capacitor, the other section is  
a function of the inductor, output capacitance as well as  
input, output voltage. For example, for the overshoot,  
when load from high load to light load with a ∆ISTEP  
transient load, if assuming the bandwidth of system is  
high enough, the overshoot can be estimated as the fol-  
lowing equation.  
ESRE ´ CE ´ VOUT  
Lcrit  
=
=
DIstep  
12mW´ 220mF´ 1.9V  
= 0.56mH  
9A  
The selected inductor is 1.5uH which is bigger than  
critical inductance. In that case, the output voltage tran-  
sient not only dependent on the ESR, but also capaci-  
tance.  
VOUT  
´ t 2  
number of capacitors is  
DVovershoot = ESR ´ DIstep  
+
...(6)  
2´ L´ COUT  
where is the a function of capacitor, etc.  
L´ DIstep  
t =  
- ESRE ´ CE  
t
VOUT  
0
if L £ Lcrit  
ì
ï
1.5mH ´ 9A  
=
- 12mW´ 220mF = 4.86us  
t = L´ DI  
í
1.8V  
step  
...(7)  
...(8)  
- ESR ´ COUT  
if L ³ Lcrit  
ï
VOUT  
î
ESRE ´ DIstep  
VOUT  
where  
ESR ´ COUT ´ VOUT ESRE ´ CE ´ VOUT  
N =  
+
´ t 2  
DV  
2´ L´ CE ´ DV  
tran  
tran  
Lcrit  
=
=
12mW´ 9A  
DIstep  
DIstep  
=
+
100mV  
where ESRE and CE represents ESR and capaci-  
tance of each capacitor if multiple capacitors are used  
in parallel.  
1.8V  
´ (4.86us)2  
2´ 1.5mH´ 220mF´ 100mV  
=1.7  
The above equation shows that if the selected out-  
put inductor is smaller than the critical inductance, the  
voltage droop or overshoot is only dependent on the ESR  
The number of capacitors has to satisfied both ripple  
and transient requirement. Overall, we can choose N=2.  
Rev.3.2  
04/10/08  
7
NX2119/2119A  
It should be considered that the proposed equa-  
tion is based on ideal case, in reality, the droop or over-  
shoot is typically more than the calculation. The equa-  
tion gives a good start. For more margin, more capaci-  
tors have to be chosen after the test. Typically, for high  
frequency capacitor such as high quality POSCAP es-  
pecially ceramic capacitor, 20% to 100% (for ceramic)  
more capacitors have to be chosen since the ESR of  
capacitors is so low that the PCB parasitic can affect  
the results tremendously. More capacitors have to be  
selected to compensate these parasitic parameters.  
1
FZ1  
FZ2  
=
=
=
=
...(11)  
2´ p ´ R4 ´ C2  
1
...(12)  
...(13)  
...(14)  
2´ p ´ (R2 + R3 )´ C3  
1
F
P1  
2´ p ´ R3 ´ C3  
1
F
P2  
C1 ´ C2  
2´ p ´ R4 ´  
C1 + C2  
where FZ1,FZ2,FP1 and FP2 are poles and zeros in  
the compensator. Their locations are shown in figure 4.  
The transfer function of type III compensator for  
transconductance amplifier is given by:  
Compensator Design  
Due to the double pole generated by LC filter of the  
power stage, the power system has 180o phase shift ,  
and therefore, is unstable by itself. In order to achieve  
accurate output voltage and fast transient  
response,compensator is employed to provide highest  
possible bandwidth and enough phase margin.Ideally,the  
Bode plot of the closed loop system has crossover fre-  
quency between1/10 and 1/5 of the switching frequency,  
phase margin greater than 50o and the gain crossing  
0dB with -20dB/decade. Power stage output capacitors  
usually decide the compensator type. If electrolytic  
capacitors are chosen as output capacitors, type II com-  
pensator can be used to compensate the system, be-  
cause the zero caused by output capacitor ESR is lower  
than crossover frequency. Otherwise type III compensa-  
tor should be chosen.  
Ve  
1- gm ´ Zf  
=
VOUT  
1+ gm ´ Zin + Zin /R1  
For the voltage amplifier, the transfer function of  
compensator is  
Ve  
- Zf  
=
VOUT  
Zin  
To achieve the same effect as voltage amplifier,  
the compensator of transconductance amplifier must  
satisfy this condition: R4>>2/gm. And it would be desir-  
able if R1||R2||R3>>1/gm can be met at the same time.  
Zf  
Vout  
Zin  
R3  
C1  
A. Type III compensator design  
C2  
R4  
R2  
R1  
For low ESR output capacitors, typically such as  
Sanyo oscap and poscap, the frequency of ESR zero  
caused by output capacitors is higher than the cross-  
over frequency. In this case, it is necessary to compen-  
sate the system with type III compensator. The follow-  
ing figures and equations show how to realize the type III  
compensator by transconductance amplifier.  
C3  
Fb  
Ve  
gm  
Vref  
Figure 3 - Type III compensator using  
transconductance amplifier  
Rev.3.2  
04/10/08  
8
NX2119/2119A  
Choose R1=8kW.  
3. Set zero FZ2 = FLC and Fp1 =FESR  
Case 1: FLC<FO<FESR  
.
4. Calculate R4 and C3 with the crossover  
frequency at 1/10~ 1/5 of the switching frequency. Set  
FO=30kHz.  
power stage  
LC  
F
40dB/decade  
1
1
1
C3 =  
´ (  
-
)
2´ p ´ R2  
F
F
p1  
z2  
1
1
1
=
´ (  
-
)
2´ p ´ 10kW 6.2kHz 60.3kHz  
loop gain  
=2.3nF  
ESR  
F
VOSC 2´ p ´ FO ´ L  
20dB/decade  
R4 =  
=
´
´ Cout  
V
C3  
1.5V 2´ p ´ 30kHz´ 1.5uH  
in  
´
´ 440uF  
compensator  
5V  
=16.9kW  
2.2nF  
Choose C3=2.2nF, R4=16.9kW.  
5. Calculate C2 with zero Fz1 at 75% of the LC  
double pole by equation (11).  
FZ1  
FO  
FP2  
FZ2  
FP1  
1
C2 =  
2´ p ´ FZ1 ´ R4  
Figure 4 - Bode plot of Type III compensator  
1
=
2´ p ´ 0.75´ 6.2kHz´ 16.9kW  
= 2nF  
Design example for type III compensator are in  
order. The crossover frequency has to be selected as  
FLC<FO<FESR, and FO<=1/10~1/5Fs.  
Choose C2=2.2nF.  
6. Calculate C1 by equation (14) with pole Fp2 at  
half the switching frequency.  
1.Calculate the location of LC double pole FLC  
and ESR zero FESR  
.
1
1
C1 =  
F
=
=
LC  
2´ p ´ R4 ´ F  
P2  
2´ p ´  
L
OUT ´ COUT  
1
1
=
2´ p ´ 16.9kW´ 150kHz  
2´ p ´ 1.5uH´ 440uF  
= 63pF  
= 6.2kHz  
Choose C1=68pF.  
1
7. Calculate R3 by equation (13).  
FESR  
=
2 ´ p ´ ESR ´ COUT  
1
1
R3 =  
=
2´ p ´ F ´ C3  
P1  
2 ´ p ´ 6mW´ 440uF  
1
= 60.3kHz  
=
2´ p ´ 60.3kHz´ 2.2nF  
=1.2kW  
2. Set R2 equal to 10kW.  
R2 ´ VREF  
10kW´ 0.8V  
R1 =  
=
= 8kW  
Choose R3=1.2kW.  
VOUT -VREF  
1.8V-0.8V  
Rev.3.2  
04/10/08  
9
NX2119/2119A  
2. Set R2 equal to 10kW.  
Case 2: FLC<FESR<FO  
R2 ´ VREF  
10kW´ 0.8V  
R1=  
=
= 8kW  
VOUT -VREF  
1.8V-0.8V  
Choose R1=8.06kW.  
3. Set zero FZ2 = FLC and Fp1 =FESR  
4. Calculate C3 .  
power stage  
.
LC  
F
40dB/decade  
1
1
1
C3 =  
´ (  
-
)
2´ p ´ R2  
F
F
p1  
z2  
ESR  
F
1
1
1
=
´ (  
-
)
2´ p ´ 10kW 2.3kHz 8.2kHz  
loop gain  
=4.76nF  
Choose C3=4.7nF.  
5. Calculate R3 .  
20dB/decade  
1
R3 =  
2´ p ´ F ´ C3  
P1  
compensator  
1
=
2´ p ´ 8.2kHz´ 4.7nF  
= 4.1k W  
Choose R3 =4kW.  
6. Calculate R4 with FO=30kHz.  
FZ1  
FO  
FP2  
FZ2  
F
P1  
VOSC 2´ p ´ F ´ L R2 ´ R3  
O
R4 =  
´
´
V
ESR  
R2 +R3  
in  
Figure 5 - Bode plot of Type III compensator  
(FLC<FESR<FO)  
1.5V 2´ p ´ 30kHz´ 1.5uH 10kW´ 4kW  
=
´
´
5V  
=37.3kW  
Choose R4=37.4kW.  
6.5mW  
10kW+ 4kW  
If electrolytic capacitors are used as output  
capacitors, typical design example of type III  
compensator in which the crossover frequency is  
selected as FLC<FESR<FO and FO<=1/10~1/5Fs is shown  
as the following steps. Here two SANYO MV-WG1500  
with 13 mW is chosen as output capacitor.  
7. Calculate C2 with zero Fz1 at 75% of the LC  
double pole by equation (11).  
1
C2 =  
2´ p ´ FZ1 ´ R4  
1
1. Calculate the location of LC double pole FLC  
=
2´ p ´ 0.75´ 2.3kHz´ 37.4kW  
= 2.4nF  
and ESR zero FESR  
.
1
Choose C2=2.2nF.  
8. Calculate C1 by equation (14) with pole Fp2 at  
half the switching frequency.  
F
=
=
LC  
2´ p ´  
L
OUT ´ COUT  
1
2´ p ´ 1.5uH´ 3000uF  
1
C1 =  
= 2.3kHz  
2´ p ´ R4 ´ F  
P2  
1
1
=
F
=
2´ p ´ 37.4kW´ 150kHz  
= 28pF  
ESR  
2´ p ´ ESR´ COUT  
1
=
Choose C1=27pF.  
2´ p ´ 6.5mW´ 3000uF  
= 8.2kHz  
Rev.3.2  
04/10/08  
10  
NX2119/2119A  
B. Type II compensator design  
If the electrolytic capacitors are chosen as power  
stage output capacitors, usually the Type II compensa-  
tor can be used to compensate the system.  
Type II compensator can be realized by simple RC  
circuit without feedback as shown in figure 6. R3 and C1  
introduce a zero to cancel the double pole effect. C2  
introduces a pole to suppress the switching noise. The  
following equations show the compensator pole zero lo-  
cation and constant gain.  
Vout  
R2  
Fb  
Ve  
gm  
R1  
R3  
C2  
Vref  
C1  
R1  
Gain=gm ´  
´ R3  
... (15)  
... (16)  
... (17)  
R1+R2  
Figure 7 - Type II compensator with  
transconductance amplifier  
1
F =  
z
2´ p ´ R3 ´ C1  
1
For this type of compensator, FO has to satisfy  
FLC<FESR<<FO<=1/10~1/5Fs.  
F »  
p
2´ p ´ R3 ´ C2  
The following is parameters for type II compensa-  
tor design. Input voltage is 5V, output voltage is 1.8V,  
output inductor is 1.5uH, output capacitors are two  
1500uF with 13mW electrolytic capacitors.  
1.Calculate the location of LC double pole FLC  
power stage  
40dB/decade  
and ESR zero FESR  
.
1
loop gain  
F
=
=
LC  
2´ p ´  
L
OUT ´ COUT  
1
20dB/decade  
2´ p ´ 1.5uH´ 3000uF  
= 2.3kHz  
1
compensator  
F
=
ESR  
2´ p ´ ESR ´ COUT  
Gain  
1
=
2´ p ´ 6.5mW´ 3000uF  
= 8.2kHz  
2.Set R2 equal to 1kW.  
R2 ´ VREF  
P
F
F
F
Z
LCFESR  
FO  
1kW´ 0.8V  
R1=  
=
= 800W  
Figure 6 - Bode plot of Type II compensator  
VOUT -VREF 1.8V-0.8V  
Choose R1=800W.  
3. Set crossover frequency at 1/10~ 1/5 of the  
swithing frequency, here FO=30kHz.  
4.Calculate R3 value by the following equation.  
Rev.3.2  
04/10/08  
11  
NX2119/2119A  
Vout  
4.Calculate R3 value by the following equation.  
VOSC 2´ p ´ FO ´ L VOUT  
R2  
Fb  
1
R3 =  
´
´
´
V
RESR  
gm VREF  
in  
R1  
1.5V 2´ p ´ 30kHz´ 1.5uH  
1
=
´
´
Vref  
5V  
6.5mW  
2.0mA/V  
1.8V  
0.8V  
´
Voltage divider  
=14.6kW  
Figure 8 - Voltage divider  
Choose R3 =14.7kW.  
5. Calculate C1 by setting compensator zero FZ  
at 75% of the LC double pole.  
Input Capacitor Selection  
Input capacitors are usually a mix of high frequency  
ceramic capacitors and bulk capacitors. Ceramic ca-  
pacitors bypass the high frequency noise, and bulk ca-  
pacitors supply switching current to the MOSFETs. Usu-  
ally 1uF ceramic capacitor is chosen to decouple the  
high frequency noise.The bulk input capacitors are de-  
cided by voltage rating and RMS current rating. The RMS  
current in the input capacitors can be calculated as:  
1
C1=  
2´ p ´ R3 ´ F  
z
1
=
2´ p ´ 14.7kW´ 0.75´ 2.3kHz  
=6.3nF  
Choose C1=6.8nF.  
F
6. Calculate C2 by setting compensator pole  
at half the swithing frequency.  
p
IRMS = IOUT ´ D ´ 1-D  
1
C 2 =  
VOUT  
D =  
p ´ R 3 ´ Fs  
V
IN  
...(19)  
1
=
VIN = 5V, VOUT=1.8V, IOUT=9A, using equation (19),  
the result of input RMS current is 4.3A.  
p ´ 1 4 .7k W ´ 3 0 0 k H z  
= 7 2 p F  
For higher efficiency, low ESR capacitors are rec-  
ommended. One Sanyo OS-CON 16SP270M 16V 270uF  
18mW with 4.4A RMS rating are chosen as input bulk  
capacitors.  
Choose C1=68pF.  
Output Voltage Calculation  
Output voltage is set by reference voltage and  
external voltage divider. The reference voltage is fixed  
at 0.8V. The divider consists of two ratioed resistors  
so that the output voltage applied at the Fb pin is 0.8V  
when the output voltage is at the desired value. The  
following equation and picture show the relationship  
between VOUT , VREF and voltage divider.  
Power MOSFETs Selection  
The power stage requires two N-Channel power  
MOSFETs. The selection of MOSFETs is based on  
maximum drain source voltage, gate source voltage,  
maximum current rating, MOSFET on resistance and  
power dissipation. The main consideration is the power  
loss contribution of MOSFETs to the overall converter  
efficiency. In this design example, two IRFR3706 are  
used. They have the following parameters: VDS=30V, ID  
=75A,RDSON =9mW,QGATE =23nC.  
R 2 ´ VREF  
R1=  
...(18)  
VOUT -VREF  
where R2 is part of the compensator, and the  
value of R1 value can be set by voltage divider.  
See compensator design for R1 and R2 selection.  
There are two factors causing the MOSFET power  
loss:conduction loss, switching loss.  
Conduction loss is simply defined as:  
Rev.3.2  
04/10/08  
12  
NX2119/2119A  
HCON =IOUT2 ´ D´ RDS(ON) ´ K  
LCON=IOUT2 ´ (1- D)´ RDS(ON) ´ K  
PTOTAL =P + P  
320mV  
P
ISET  
=
K ´ RDSON  
P
...(20)  
If MOSFET RDSON=9mW, the worst case thermal  
consideration K=1.5, then  
HCON  
LCON  
where the RDS(ON) will increases as MOSFET junc-  
tion temperature increases, K is RDS(ON) temperature  
dependency. As a result, RDS(ON) should be selected for  
the worst case, in which K approximately equals to 1.4  
at 125oC according to IRFR3706 datasheet. Conduc-  
tion loss should not exceed package rating or overall  
system thermal budget.  
320mV  
320mV  
ISET  
=
=
= 23.7A  
K ´ RDSON 1.5´ 9mW  
Layout Considerations  
The layout is very important when designing high  
frequency switching converters. Layout will affect noise  
pickup and can cause a good design to perform with  
less than expected results.  
Switching loss is mainly caused by crossover con-  
duction at the switching transition. The total switching  
loss can be approximated.  
Start to place the power components, make all the  
connection in the top layer with wide, copper filled ar-  
eas. The inductor, output capacitor and the MOSFET  
should be close to each other as possible. This helps to  
reduce the EMI radiated by the power traces due to the  
high switching currents through them. Place input ca-  
pacitor directly to the drain of the high-side MOSFET, to  
reduce the ESR replace the single input capacitor with  
two parallel units. The feedback part of the system should  
be kept away from the inductor and other noise  
sources,and be placed close to the IC. In multilayer PCB  
use one layer as power ground plane and have a control  
circuit ground (analog ground), to which all signals are  
referenced.  
1
PSW  
=
´ V ´ IOUT ´ TSW ´ F  
IN S  
...(21)  
2
where IOUT is output current, TSW is the sum of TR  
and TF which can be found in mosfet datasheet, and FS  
is switching frequency. Switching loss PSW is frequency  
dependent.  
Also MOSFET gate driver loss should be consid-  
ered when choosing the proper power MOSFET.  
MOSFET gate driver loss is the loss generated by dis-  
charging the gate capacitor and is dissipated in driver  
circuits.It is proportional to frequency and is defined as:  
P
= (QHGATE ´ VHGS + QLGATE ´ VLGS )´ FS  
...(22)  
gate  
where QHGATE is the high side MOSFETs gate  
The goal is to localize the high current path to a  
separate loop that does not interfere with the more sen-  
sitive analog control function. These two grounds must  
be connected together on the PC board layout at a single  
point.  
charge,QLGATE is the low side MOSFETs gate charge,VHGS  
is the high side gate source voltage, and VLGS is the low  
side gate source voltage.  
This power dissipation should not exceed maxi-  
mum power dissipation of the driver device.  
Over Current Limit Protection  
Over current Limit for step down converter is  
achieved by sensing current through the low side  
MOSFET. For NX2119, the current limit is decided by  
the RDSON of the low side mosfet. When synchronous  
FET is on, and the voltage on SW pin is below 320mV,  
the over current occurs. The over current limit can be  
calculated by the following equation.  
Rev.3.2  
04/10/08  
13  
NX2119/2119A  
SOIC8 PACKAGE OUTLINE DIMENSIONS  
Rev.3.2  
04/10/08  
14  
NX2119/2119A  
Rev.3.2  
04/10/08  
15  
NX2119/2119A  
MSOP8 PACKAGE OUTLINE DIMENSIONS  
Rev.3.2  
04/10/08  
16  
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