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NX2139A

型号:

NX2139A

描述:

单通道手机PWM和LDO控制器[ SINGLE CHANNEL MOBILE PWM AND LDO CONTROLLER ]

品牌:

MICROSEMI[ Microsemi ]

页数:

21 页

PDF大小:

857 K

NX2139A  
SINGLE CHANNEL MOBILE PWM AND LDO CONTROLLER  
PRELIMINARY DATA SHEET  
Pb Free Product  
FEATURES  
DESCRIPTION  
n
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Internal Boost Schottky Diode  
The NX2139A controller IC is a compact Buck control-  
ler IC with 16 lead MLPQ package designed for step  
down DC to DC converter in portable applications. It  
can be selected to operate in synchronous mode or  
non-synchronous mode to improve the efficiency at light  
load.Constant on time control provides fast response,  
good line regulation and nearly constant frequency un-  
der wide voltage input range. The NX2139A controller  
is optimized to convert single supply up to 24V bus  
voltage to as low as 0.75V output voltage. Over cur-  
rent protection and FB UVLO followed by latch fea-  
ture. A built-in LDO controller can drive an external N-  
MOSFET to provide a second output voltage from ei-  
ther PWM output source or other power source. Both  
PWM controller and LDO controller have separate EN  
feature. Other features includes: 5V gate drive capa-  
bility, power good indicator, over voltage protection,  
internal Boost schottky diode and adaptive dead band  
control.  
Ultrasonic mode operation available  
Bus voltage operation from 4.5V to 24V  
Less than 1uA shutdown current with Enable low  
Excellent dynamic response with constant on time  
control  
Selectable between Synchronous CCM mode and  
diode emulation mode to improve efficiency at  
light load  
Programmable switching frequency  
Current limit and FB UVLO with latch off  
Over voltage protection with latch off  
LDO controller with seperate enable  
Two independent Power Good indicator available  
Pb-free and RoHS compAlianPt PLICATIONS  
Notebook PCs and Desknotes  
Tablet PCs/Slates  
n
n
n
n
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n
n
n
n
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On board DC to DC such as  
12V to 3.3V, 2.5V or 1.8V  
n
Hand-held portable instruments  
TYPICAL APPLICATION  
4
1MEG  
16  
PGOOD  
PGOOD  
TON  
VIN 7V~22V  
1n  
100k  
2x10uF  
9
2
5V  
PVCC  
VCC  
12  
13  
HDRV  
BST  
IRF7807  
10  
2.2  
1u  
1u  
1u  
Vout 1.8V/7A  
1.5uH  
11  
8
SW  
2R5TPE330MC  
330uF  
AO4714  
LDRV  
ENSW  
/MODE  
15  
5k  
10  
1
OCSET  
VOUT  
330p  
10.5k  
3
7
FB  
7.5k  
M3  
SI4800  
LDODRV  
14  
1.5V@2A  
ENLDO  
LDOPG  
50  
33n  
1n  
5V  
20k  
7.5k  
7.5k  
2x10uF  
100k  
6
LDOFB  
5
LDOPG  
GND  
PAD  
Figure1 - Typical application of NX2139A  
ORDERING INFORMATION  
Device  
Temperature  
Package  
Pb-Free  
Yes  
NX2139ACMTR -10o C to 100o C 3X3 MLPQ-16L  
Rev. 2.3  
03/19/09  
1
NX2139A  
ABSOLUTE MAXIMUM RATINGS  
VCC,PVCC to GND & BST to SW voltage ............ -0.3V to 6.5V  
TON to GND ......................................................... -0.3V to 28V  
HDRV to SW Voltage .......................................... -0.3V to 6.5V  
SW to GND ......................................................... -2V to 30V  
All other pins ........................................................ VCC+0.3V  
StorageTemperatureRange..................................-65oC to 150oC  
Operating Junction Temperature Range .................-40oC to 150oC  
ESD Susceptibility ............................................... 2kV  
CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent  
damage to the device. This is a stress only rating and operation of the device at these or any other conditions  
above those indicated in the operational sections of this specification is not implied.  
PACKAGE INFORMATION  
3x3 16-LEAD PLASTIC MLPQ  
qJA » 46oC/W  
13  
16 15 14  
HDRV  
1
2
3
4
VO  
12  
11  
10  
9
SW  
VCC  
FB  
17  
AGND  
OCSET  
PVCC  
PGOOD  
7
5
6
8
ELECTRICAL SPECIFICATIONS  
Unless otherwise specified, these specifications apply over Vcc =5V, VIN=15V and TA =25oC, unless otherwise  
specified.  
PARAMETER  
SYM  
Test Condition  
Min  
TYP  
MAX Units  
VIN  
VIN  
V
recommended voltage range  
Shut down current  
4.5  
24  
uA  
ENLDO=GND, ENSW=GND  
1
VCC,PVCC Supply  
Input voltage range  
VCC  
4.5  
5.5  
V
VFB=0.85V, ENLDO=GND,  
ENSW=5V  
Operating quiescent current  
Shut down current  
1.8  
1
mA  
uA  
ENLDO=GND, ENSW=GND  
Rev. 2.3  
03/19/09  
2
NX2139A  
PARAMETER  
VCC UVLO  
SYM  
Test Condition  
Min  
TYP  
MAX Units  
Under-voltage Lockout  
VCC_UVLO  
threshold  
3.9  
3.7  
4.1  
3.9  
4.5  
4.3  
V
V
Falling VCC threshold  
ON and OFF time  
TON operating current  
VIN=15V, Rton=1Mohm  
VIN=9V,VOUT=0.75V,  
Rton=1Mohm  
15  
uA  
ON -time  
Minimum off time  
312  
380  
390  
590  
468  
800  
ns  
ns  
FB voltage  
Vref  
Internal FB voltage  
Input bias current  
Line regulation  
OUTPUT voltage  
0.739  
-1  
0.75  
0.761  
100  
1
V
nA  
%
VCC from 4.5V to 5.5V  
ENSW/MODE=GND  
Output range  
VOUT shut down discharge  
resistance  
0.75  
3.3  
V
30  
ohm  
ms  
Soft start time  
1.5  
PGOOD  
Pgood high rising threshold  
PGOOD delay after softstart  
PGOOD propagation delay  
filter  
90  
1.6  
% Vref  
ms  
NOTE1  
NOTE1  
2
5
us  
%
Power good hysteresis  
Pgood output switch  
impedance  
13  
1
ohm  
uA  
Pgood leakage current  
SW zero cross comparator  
Offset voltage  
5
mV  
HighNSide Driver  
(CL=3300pF)  
Output Impedance , Sourcing Rsource(Hdrv)  
Current  
I=200mA  
I=200mA  
1.5  
1.5  
ohm  
ohm  
Output Impedance , Sinking  
Current  
Rsink(Hdrv)  
Rise Time  
Fall Time  
Deadband Time  
THdrv(Rise)  
THdrv(Fall)  
Tdead(L to Ldrv going Low to Hdrv going  
10% to 90%  
90% to 10%  
50  
50  
30  
ns  
ns  
ns  
H)  
High, 10% to 10%  
Low Side Driver  
(CL=3300pF)  
Output Impedance, Sourcing Rsource(Ldrv)  
Current  
I=200mA  
I=200mA  
1.5  
0.5  
ohm  
ohm  
Output Impedance, Sinking  
Current  
Rsink(Ldrv)  
Rise Time  
Fall Time  
Deadband Time  
TLdrv(Rise)  
TLdrv(Fall)  
Tdead(H to SW going Low to Ldrv going  
L) High, 10% to 10%  
10% to 90%  
90% to 10%  
50  
50  
10  
ns  
ns  
ns  
Rev. 2.3  
03/19/09  
3
NX2139A  
PARAMETER  
ENSW/MODE threshold and  
bias current  
SYM  
Test Condition  
Min  
TYP  
MAX Units  
80%  
VCC  
60%  
VCC  
VCC+0  
.3V  
80%  
VCC  
60%  
VCC  
PFM/Non Synchronous Mode  
Ultrasonic Mode  
V
V
Leave it open or use limits in  
spec  
Synchronous Mode  
Shutdown mode  
2
0
V
V
0.8  
ENSW/MODE=VCC  
ENSW/MODE=GND  
5
uA  
uA  
Input bias current  
-5  
LDO Controller  
PWM OFF, LDOEN=HI,  
IOUT=0mA  
Quiescent current  
1
mA  
V
LDOEN logic high voltage  
2
LDOEN logic low voltage  
LDOFB reference voltage  
0.8  
0.773  
V
V
0.728  
0.75  
70  
Output UVLO threshold  
Open loop gain  
%Vref  
DB  
NOTE1  
60  
LDOFB input bias current  
LDODrv sourcing current  
LDODrv sinking current  
1
uA  
LDOFB=0.72V  
LDOFB=0.78V  
2
2
mA  
mA  
LDO PGOOD threshold  
LDO PGOOD propagation  
delay filter  
90  
%Vref  
NOTE1  
2
us  
LDO PGOOD impedance  
13  
ohm  
Current Limit  
Ocset setting current  
Over temperature  
Threshold  
20  
24  
28  
uA  
oC  
oC  
NOTE1  
155  
15  
Hysteresis  
Under voltage  
FB threshold  
Over voltage  
Over voltage tripp point  
Internal Schottky Diode  
Forward voltage drop  
70  
%Vref  
%Vref  
mV  
125  
500  
Forward current=50mA  
NOTE1: This parameter is guaranteed by design but not tested in production(GBNT).  
Rev. 2.3  
03/19/09  
4
NX2139A  
PIN DESCRIPTIONS  
PIN NUMBER PIN SYMBOL  
PIN DESCRIPTION  
This pin is directly connected to the output of the switching regulator and  
senses the VOUT voltage. An internal MOSFET discharges the output during  
turn off.  
1
VOUT  
This pin supplies the internal 5V bias circuit. A 1uF X7R ceramic capacitor is  
placed as close as possible to this pin and ground pin.  
2
3
VCC  
FB  
This pin is the error amplifiers inverting input. This pin is connected via  
resistor divider to the output of the switching regulator to set the output DC  
voltage from 0.75V to 3.3V.  
PGOOD indicator for switching regulator. It requires a pull up resistor to Vcc  
or lower voltage. When FB pin reaches 90% of the reference voltage  
PGOOD transitions from LO to HI state.  
4
5
PGOOD  
LDOPG  
PGOOD indicator for LDO, requires a pull up resistor to Vcc or lower volt-  
age. When LDOFB pin reaches 90% of the reference voltage PGOOD  
transitions from LO to HI state.  
This pin is the error amplifiers inverting input. This pin is connected via  
resistor divider to the output of the LDO to set the output DC voltage.  
6
7
8
9
LDOFB  
LDODRV  
LDRV  
The drive signal for external LDO N channel MOSFET.  
Low side gate driver output.  
PVCC  
Provide the voltage supply to the lower MOSFET drivers. Place a high  
frequency decoupling capacitor 1uF X5R to this pin.  
10  
OCSET  
This pin is connected to the drain of the external low side MOSFET and is  
the input of over current protection(OCP) comparator. An internal current  
source is flown to the external resistor which sets the OCP voltage across  
the Rdson of the low side MOSFET.  
11  
12  
13  
SW  
HDRV  
BST  
This pin is connected to source of high side FETs and provide return path for  
the high side driver. It is also the input of zero current sensing comparator.  
High side gate driver output.  
This pin supplies voltage to high side FET driver. A high freq 1uF X7R  
ceramic capacitor and 2.2ohm resistor in series are recommended to be  
placed as close as possible to and connected to this pin and SW pin.  
14  
15  
ENLDO  
LDO enable input functions only when ENSW/MODE is not shutdown.  
ENSW/  
MODE  
Switching converter enable input. Connect to VCC for PFM/Non synchronous  
mode, connected to an external resistor divider equals to 70%VCC for ultra-  
sonic, connected to GND for shutdown mode, floating or connected to 2V for  
the synchronous mode.  
16  
TON  
GND  
VIN sensing input. A resistor connects from this pin to VIN will set the fre-  
quency. A 1nF capacitor from this pin to GND is recommended to ensure the  
proper operation.  
PAD  
Power ground.  
Rev. 2.3  
03/19/09  
5
NX2139A  
BLOCK DIAGRAM  
VCC(2)  
Bias  
4.3/4.1  
Disable_B  
POR  
ODB  
BST(13)  
Thermal  
shutdown  
VIN  
TON(16)  
VIN  
start  
ON time  
pulse  
genearation  
HDRV(12)  
HD  
VOUT  
FET Driver  
HD_IN  
R
Q
S
VOUT  
FB(3)  
SW(11)  
1.8V  
5V  
PVCC(9)  
LDRV(8)  
Mini offtime  
400ns  
OCP_COMP  
PGND  
VREF=0.75V  
start  
POR  
FBUVLO_latch  
HD  
Diode  
emulation  
soft start  
VCC  
1M  
ENSW  
/MODE(15)  
Disable  
PFM_nonultrasonic  
Sync  
MODE  
1M  
SELECTION  
OCSET(10)  
FB  
1.25*Vref/0.7VREF  
OVP  
OCP_COMP  
GND(17 PAD)  
PGOOD(4)  
FB  
VOUT(1)  
FBUVLO_latch  
0.7*Vref  
VOUT  
SS_finished  
start  
0.9*Vref  
1.5V@2A~5A  
LDOFBUVLO_latch  
0.7*Vref  
LDOPG(5)  
LDOSS_finished  
0.9*Vref  
soft  
start  
LDO_POR  
LDOFBUVLO_latch  
LDODRV(7)  
LDOFB(6)  
ENLDO(14)  
LDO_EN  
Figure 2 - Simplified block diagram of the NX2139A  
Rev. 2.3  
03/19/09  
6
NX2139A  
TYPICAL APPLICATION  
(VIN=7V to 22V, SW VOUT=1.8V/7A, LDO VOUT=1.5V/2A)  
R4  
1MEG  
4
PGOOD  
PGOOD  
16  
TON  
C3  
1n  
VIN 7V~22V  
Vout 1.8V/7A  
R1  
100k  
CI1  
2x10uF  
9
2
5V  
PVCC  
VCC  
M1  
R2  
10  
12  
13  
HDRV  
BST  
IRF7807  
R13 2.2  
C1  
1u  
C2  
1u  
C4  
1u  
Lo  
1.5uH  
11  
8
SW  
CO1  
2R5TPE330MC  
330uF  
M2  
AO4714  
LDRV  
ENSW  
/MODE  
15  
R12  
2.2  
C7  
1.5n  
R5  
5k  
10  
1
OCSET  
VOUT  
R6  
10.5k  
C8  
330p  
3
7
FB  
R7  
M3  
SI4800  
7.5k  
LDODRV  
14  
R8  
50  
1.5V@2A  
ENLDO  
LDOPG  
C5  
1n  
R10  
7.5k  
5V  
C6  
R9  
20k  
CO2  
2x10uF  
33n  
R3  
100k  
6
LDOFB  
5
R11  
7.5k  
LDOPG  
GND  
PAD  
Figure 3 - Demo board schematic  
Rev. 2.3  
03/19/09  
7
NX2139A  
Bill of Materials  
Item  
1
Quantity  
Reference  
Value  
10uF/25V/X5R  
10uF/6.3V/X5R  
2R5TPE330MC  
1uF  
1nF  
33nF  
1.5nF  
330pF  
DO5010H-152  
IRF7807  
AO4714  
SI4800  
100k  
10  
1M  
5k  
10.5k  
Manufacture  
2
2
1
3
2
1
1
1
1
1
1
1
2
1
1
1
1
3
1
1
2
1
CI1  
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
CO2  
CO1  
C1,C2,C4  
C3,C5  
C6  
C7  
C8  
Lo  
M1  
M2  
M3  
R1,R3  
R2  
R4  
SANYO  
COILCRAFT  
IR  
AOS  
PHILIPS  
R5  
R6  
R7,R10,R11  
R8  
R9  
R12,R13  
U1  
7.5k  
50  
20k  
2.2  
NX2139A  
NEXSEM INC.  
Rev. 2.3  
03/19/09  
8
NX2139A  
Demoboard Waveforms  
Fig.4 Startup (CH1 1.8V OUTPUT, CH2 1.5V LDO,  
CH3 SW PGOOD, CH4 LDO PGOOD)  
Fig.5 Turn off (CH1 1.8V OUTPUT, CH2 1.5V LDO,  
CH3 SW PGOOD, CH4 LDO PGOOD)  
Fig.6 LDO output transient with SW in PFM mode  
(CH1 1.8V OUTPUT AC, CH2 1.5V LDO AC, CH4  
LDO OUTPUT CURRENT)  
Fig.7 SW output transient (CH1 1.8V OUTPUT AC,  
CH2 1.5V LDO AC, CH4 1.8V OUTPUT CURRENT)  
Fig.8 Start into short (CH1 VIN, CH2 5V VCC, CH4  
INDUCTOR CURRENT)  
Fig. 9 VOUT ripple @ VIN=12V,IOUT=4A (CH1 SW,  
CH3 VOUT AC)  
Rev. 2.3  
03/19/09  
9
NX2139A  
VIN=12V, VOUT=1.8V  
100.00%  
90.00%  
80.00%  
70.00%  
60.00%  
50.00%  
10  
100  
1000  
10000  
OUTPUT CURRENT(mA)  
Fig. 10 Output efficiency  
Rev. 2.3  
03/19/09  
10  
NX2139A  
FS is around 220kHz.  
APPLICATION INFORMATION  
Symbol Used In Application Information:  
Output Inductor Selection  
VIN  
- Input voltage  
- Output voltage  
- Output current  
The value of inductor is decided by inductor ripple  
current and working frequency. Larger inductor value  
normally means smaller ripple current. However if the  
inductance is chosen too large, it brings slow response  
and lower efficiency. The ripple current is a design free-  
dom which can be decided by design engineer accord-  
ing to various application requirements. The inductor  
value can be calculated by using the following equa-  
tions:  
VOUT  
IOUT  
VRIPPLE - Output voltage ripple  
- Working frequency  
FS  
IRIPPLE - Inductor current ripple  
Design Example  
The following is typical application for NX2139A,  
the schematic is figure 1.  
VIN = 7 to 22V  
V -V  
´ T  
ON  
(
)
IN  
OUT  
LOUT  
=
IRIPPLE  
VOUT=1.8V  
...(3)  
IRIPPLE =k ´ IOUTPUT  
FS=220kHz  
IOUT=7A  
where k is percentage of output current.  
In this example, inductor from COILCRAFT  
DO5010H-152 with L=1.5uH is chosen.  
VRIPPLE <=60mV  
VDROOP<=60mV @ 3A step  
Current Ripple is recalculated as below:  
On_Time and Frequency Calculation  
The constant on time control technique used in  
NX2139A delivers high efficiency, excellent transient  
dynamic response, make it a good candidate for step  
down notebook applications.  
(V -VOUT )´ TON  
IN  
IRIPPLE  
=
=
LOUT  
(22V-1.8V)´ 372nS  
1.5uH  
=5A  
...(4)  
An internal one shot timer turns on the high side  
driver with an on time which is proportional to the input  
supply VIN as well inversely proportional to the output  
voltage VOUT. During this time, the output inductor  
charges the output cap increasing the output voltage  
by the amount equal to the output ripple. Once the  
timer turns off, the Hdrv turns off and cause the output  
voltage to decrease until reaching the internal FB volt-  
age of 0.75V on the PFM comparator. At this point the  
comparator trips causing the cycle to repeat itself. A  
minimum off time of 400nS is internally set.  
Output Capacitor Selection  
Output capacitor is basically decided by the  
amount of the output voltage ripple allowed during  
steady state(DC) load condition as well as specifica-  
tion for the load transient. The optimum design may  
require a couple of iterations to satisfy both conditions.  
Based on DC Load Condition  
The amount of voltage ripple during the DC load  
condition is determined by equation(5).  
DIRIPPLE  
The equation setting the On Time is as follows:  
DVRIPPLE = ESR´ DIRIPPLE  
+
...(5)  
8´ F ´ COUT  
S
4.45´ 10- 12 ´ RTON ´ VOUT  
TON =  
...(1)  
...(2)  
Where ESR is the output capacitors' equivalent  
series resistance,COUT is the value of output capaci-  
tors.  
V - 0.5V  
IN  
VOUT  
V ´ TON  
F =  
S
IN  
Typically POSCAP is recommended to use in  
NX2139's applications. The amount of the output volt-  
age ripple is dominated by the first term in equation(5)  
In this application example, the RTON is chosen  
to be 1Mohm, when VIN=22V, the TON is 372nS and  
Rev. 2.3  
03/19/09  
11  
NX2139A  
and the second term can be neglected.  
ESR ´ COUT ´ VOUT ESRE ´ CE ´ VOUT  
Lcrit  
=
=
...(10)  
For this example, one POSCAP 2R5TPE330MC  
is chosen as output capacitor, the ESR and inductor  
current typically determines the output voltage ripple.  
When VIN reach maximum voltage, the output volt-  
age ripple is in the worst case.  
DIstep  
DIstep  
where ESRE and CE represents ESR and capaci-  
tance of each capacitor if multiple capacitors are used  
in parallel.  
The above equation shows that if the selected  
output inductor is smaller than the critical inductance,  
the voltage droop or overshoot is only dependent on  
the ESR of output capacitor. For low frequency ca-  
pacitor such as electrolytic capacitor, the product of  
DVRIPPLE  
DIRIPPLE  
60mV  
5A  
ESRdesire  
=
=
= 12mW  
...(6)  
If low ESR is required, for most applications, mul-  
tiple capacitors in parallel are needed. The number of  
output capacitor can be calculate as the following:  
ESR and capacitance is high and L £ Lcrit is true. In  
that case, the transient spec is mostly like to depen-  
dent on the ESR of capacitor.  
E S R E ´ DIR IPPLE  
N =  
...(7)  
D VR IPPLE  
Most case, the output capacitor is multiple ca-  
pacitor in parallel. The number of capacitor can be cal-  
culated by the following  
12m5A  
N =  
60mV  
N =1  
ESRE ´ DIstep  
VOUT  
The number of capacitor has to be round up to a  
integer. Choose N =1.  
N =  
where  
+
´ t 2  
...(11)  
DV  
2´ L´ CE ´ DV  
tran  
tran  
Based On Transient Requirement  
Typically, the output voltage droop during tran-  
sient is specified as  
0
if L £ Lcrit  
ì
ï
L´ DI  
t =  
í
ï
î
step  
...(12)  
- ESRE ´ CE  
if L ³ Lcrit  
VOUT  
DV  
< DV  
@step load I  
tran  
droop  
STEP  
During the transient, the voltage droop during the  
transient is composed of two sections. One section is  
dependent on the ESR of capacitor, the other section  
is a function of the inductor, output capacitance as well  
as input, output voltage. For example, for the over-  
shoot when load from high load to light load with a  
DISTEP transient load, if assuming the bandwidth of sys-  
tem is high enough, the overshoot can be estimated  
as the following equation.  
For example, assume voltage droop during tran-  
sient is 60mV for 3A load step.  
If one POSCAP 2R5TPE330MC(330uF, 12mohm  
ESR) is used, the crticial inductance is given as  
ESRE ´ CE ´ V  
OUT  
Lcrit  
=
=
DIstep  
12mW´ 3300mF´ 1.8V  
= 23.76mH  
3A  
VOUT  
DVovershoot = ESR ´ DIstep  
+
´ t 2  
The selected inductor is 1.5uH which is smaller  
than critical inductance. In that case, the output volt-  
age transient mainly dependent on the ESR.  
...(8)  
2´ L´ COUT  
where  
is the a function of capacitor,etc.  
t
number of capacitor is  
0
if L £ Lcrit  
ì
ï
L´ DI  
t =  
ESRE ´ DIstep  
N =  
í
ï
î
step  
...(9  
- ESR ´ COUT  
if L ³ Lcrit  
VOUT  
DV  
tran  
12m3A  
where  
=
60mV  
= 0.6  
Choose N=1.  
12  
Rev. 2.3  
03/19/09  
NX2139A  
Based On Stability Requirement  
and power dissipation. The main consideration is the  
ESR of the output capacitor can not be chosen power loss contribution of MOSFETs to the overall con-  
too low which will cause system unstable. The zero verter efficiency. In this application, one IRF7807 for  
caused by output capacitor's ESR must satisfy the re- high side and one AO4714 with integrated schottky di-  
quirement as below:  
ode for low side are used.  
There are two factors causing the MOSFET  
power loss:conduction loss, switching loss.  
Conduction loss is simply defined as:  
F
1
SW  
F
=
£
ESR  
...(13)  
2´ p ´ ESR´ COUT  
4
Besides that, ESR has to be bigger enough so  
that the output voltage ripple can provide enough volt-  
age ramp to error amplifier through FB pin. If ESR is  
too small, the error amplifier can not correctly dectect  
the ramp, high side MOSFET will be only turned off for  
minimum time 400nS. Double pulsing and bigger out-  
put ripple will be observed. In summary, the ESR of  
output capacitor has to be big enough to make the sys-  
tem stable, but also has to be small enough to satify  
the transient and DC ripple requirements.  
P
HCON =IOUT2 ´ D´ RDS(ON) ´ K  
LCON=IOUT2 ´ (1- D)´ RDS(ON) ´ K  
PTOTAL =P + P  
P
...(15)  
HCON  
LCON  
where the RDS(ON) will increases as MOSFET junc-  
tion temperature increases, K is RDS(ON) temperature  
dependency. As a result, RDS(ON) should be selected  
for the worst case. Conduction loss should not exceed  
package rating or overall system thermal budget.  
Switching loss is mainly caused by crossover  
conduction at the switching transition. The total  
switching loss can be approximated.  
Input Capacitor Selection  
Input capacitors are usually a mix of high fre-  
quency ceramic capacitors and bulk capacitors. Ce-  
ramic capacitors bypass the high frequency noise, and  
bulk capacitors supply switching current to the  
MOSFETs. Usually 1uF ceramic capacitor is chosen  
to decouple the high frequency noise.The bulk input  
capacitors are decided by voltage rating and RMS cur-  
rent rating. The RMS current in the input capacitors  
can be calculated as:  
1
PSW  
=
´ V ´ IOUT ´ TSW ´ F  
IN S  
...(16)  
2
where IOUT is output current, TSW is the sum of TR  
and TF which can be found in mosfet datasheet, and  
FS is switching frequency. Swithing loss PSW is fre-  
quency dependent.  
Also MOSFET gate driver loss should be consid-  
ered when choosing the proper power MOSFET.  
MOSFET gate driver loss is the loss generated by dis-  
charging the gate capacitor and is dissipated in driver  
circuits.It is proportional to frequency and is defined  
as:  
IRMS = IOUT  
´ D ´ 1-D  
...(14)  
D = TON ´ FS  
When VIN = 22V, VOUT=1.8V, IOUT=7A, the result of  
input RMS current is 1.9A.  
P
= (QHGATE ´ VHGS + QLGATE ´ VLGS )´ FS  
...(17)  
gate  
For higher efficiency, low ESR capacitors are  
recommended. One 10uF/X5R/25V and two 4.7uF/  
X5R/25V ceramic capacitors are chosen as input  
capacitors.  
where QHGATE is the high side MOSFETs gate  
charge,QLGATE is the low side MOSFETs gate  
charge,VHGS is the high side gate source voltage, and  
VLGS is the low side gate source voltage.  
This power dissipation should not exceed maxi-  
mum power dissipation of the driver device.  
Power MOSFETs Selection  
The NX2139A requires at least two N-Channel  
power MOSFETs. The selection of MOSFETs is based  
on maximum drain source voltage, gate source volt-  
age, maximum current rating, MOSFET on resistance  
Output Voltage Calculation  
Output voltage is set by reference voltage and  
external voltage divider. The reference voltage is fixed  
Rev. 2.3  
03/19/09  
13  
NX2139A  
at 0.75V. The divider consists of two ratioed resistors tion of frequency keeps the system running at light light  
so that the output voltage applied at the Fb pin is 0.75V with high efficiency.  
when the output voltage is at the desired value.  
In CCM mode, inductor current zero-crossing  
The following equation applies to figure 11, which sensing is disabled, low side MOSFET keeps on even  
shows the relationship between VOUT , VREF and volt- when inductor current becomes negative. In this way  
age divider.  
the efficiency is lower compared with PFM mode at  
light load, but frequency will be kept constant.  
Vout  
Over Current Protection  
Over current protection for NX2139A is achieved  
by sensing current through the low side MOSFET. An  
typical internal current source of 24uA flows through  
an external resistor connected from OCSET pin to SW  
node sets the over current protection threshold. When  
synchronous FET is on, the voltage at node SW is given  
as  
R2  
R1  
Fb  
Vref  
Figure 11 - Voltage Divider  
VSW =-IL ´ RDSON  
The voltage at pin OCSET is given as  
R 2 ´ VREF  
I
OCP ´ ROCP +VSW  
R1=  
...(18)  
VOUT -VREF  
When the voltage is below zero, the over current  
occurs as shown in figure below.  
where R2 is part of the compensator, and the value  
of R1 value can be set by voltage divider.  
vbus  
Mode Selection  
I
OCP  
24uA  
NX2139A can be operated in PFM mode, ultra-  
sonic PFM mode, CCM mode and shutdown mode by  
applying different voltage on ENSW/MODE pin.  
When VCC applied to ENSW/MODE pin,  
NX2139A is In PFM mode. The low side MOSFET emu-  
lates the function of diode when discontinuous con-  
tinuous mode happens, often in light load condition.  
During that time, the inductor current crosses the zero  
ampere border and becomes negative current. When  
the inductor current reaches negative territory, the low  
side MOSFET is turned off and it takes longer time for  
the output voltage to drop, the high side MOSFET waits  
OCP  
R
SW  
OCP  
OCP  
comparator  
Figure 12 - Over Voltage Protection  
The over current limit can be set by the following  
equation.  
ISET = IOCP ´ ROCP/RDSON  
If the low side MOSFET RDSON=10mW at the OCP  
occuring moment, and the current limit is set at 12A,  
longer to be turned on. At the same time, no matter then  
light load and heavy load, the on time of high side  
MOSFET keeps the same. Therefore the lightier load,  
the lower the switching frequency will be. In ultrosonic  
PFM mode, the lowest frequency is set to be 25kHz to  
avoid audio frequency modulation. This kind of reduc-  
I
SET ´ RDSON 12A ´ 10mW  
ROCP  
=
=
= 5kW  
IOCP  
24uA  
Choose ROCP=5kW  
Rev. 2.3  
03/19/09  
14  
NX2139A  
Power Good Output  
PLOSS = (VLDOIN - VLDOOUT )´ ILOAD  
= (1.8V - 1.5V)´ 2A = 0.6W  
Power good output is open drain output, a pull  
up resistor is needed. Typically when softstart is  
finised and FB pin voltage is over 90% of VREF, the  
PGOOD pin is pulled to high after a 1.6ms delay.  
Select MOSFET SI4800 with 33mW RDSON is  
sufficient.  
LDO Compensation  
Smart Over Output Voltage Protection  
Active loads in some applications can leak cur-  
rent from a higher voltage than VOUT, cause output volt-  
age to rise. When the FB pin voltage is sensed over  
112% of VREF, the high side MOSFET will be turned off  
and low side MOSFET will be turned on to discharge  
the VOUT. NX2139A resumes its switching operation af-  
The diagram of LDO controller including VCC  
regulator is shown in the following figure.  
LDO input  
Vref  
LDODRV  
Rf1  
Rf2  
LDOFB  
Rb  
Cb  
ESR  
Co  
ter FB pin voltage drops to VREF  
.
Rload  
If FB pin voltage keeps rising and is sensed over  
125% of VREF, the low side MOSFET will be latched to  
be on to discharge the output voltage and over voltage  
protection is triggered. To resume the switching opera-  
tion, resetting voltage on pin VCC or pin EN is neces-  
sary.  
Rc  
Cc  
Figure 13 - NX2139A LDO controller.  
Rb and Cb have fixed value which is used to com-  
pensate the comparater of the LDO controller. Set  
Rb=50ohm, Cb=33nF.  
Under Output Voltage Protection  
Typically when the FB pin voltage is under 70%  
of VREF, the high side and low side MOSFET will be  
turned off. To resume the switching operation, VCC or  
ENSW has to be reset.  
For most low frequency capacitor such as elec-  
trolytic, POSCAP, OSCON, etc, the compensation pa-  
rameter can be calculated as follows.  
LDO Selection Guide  
gm ´ ESR  
1
CC =  
´
NX2139A offers a LDO controller. The selection  
of MOSFET to meet LDO is more straight forward.  
The MOSFET has to be logic level MOSFET and its  
Rdson at 4.5V should meet the dropout requirement.  
For example.  
2´ p ´ FO ´ Rf1 1+gm ´ ESR  
where FO is the desired crossover frequency.  
Typically, when the POSCAP and electrical ca-  
pacitor is chosen as output capacitor, crossover fre-  
quency FO has to be 2 to 3 times higher than zero  
caused by ESR. In this example, we select Fo=150kHz.  
gm is the forward trans-conductance of MOSFET.  
For SI4800, gm=19.  
VLDOIN =1.8V  
VLDOOUT =1.5V  
ILoad =2A  
The maximum Rdson of MOSFET should be  
Select Rf1=7.5kohm.  
Output capacitor is Sanyo POSCAP 4TPE150MI  
with 150uF, ESR=18mohm.  
RRDSON = (VLDOIN - VLDOOUT )´ ILOAD  
= (1.8V - 1.5V) / 2A = 0.15W  
1
19S´ 18mW  
Most of MOSFETs can meet the requirement.  
More important is that MOSFET has to be selected  
right package to handle the thermal capability. For LDO,  
maximum power dissipation is given as  
CC =  
´
=36pF  
2´ p ´ 150kHz´ 7.5kW 1+19S´ 18mW  
Typically CC is chosen to be 1 to 1.5 times smaller  
than calculated value to compensate parasitic effect.  
Rev. 2.3  
03/19/09  
15  
NX2139A  
Here CC is chosen to be 33pF. For electrolytic or 70% of VREF, the IC goes into latch mode. The IC will  
POSCAP, RC is typically selected to be zero.  
Rf2 is determined by the desired output voltage.  
turn off all the channel until VCC or ENSW resets.  
Power Good for LDO  
Rf1 ´ VREF  
Rf2 =  
Power good output is open drain output, a pull  
V
- VREF  
LDOOUT  
up resistor is needed. Typically when softstart is  
7.5k0.75V  
1.5V - 0.75V  
=7.5kW  
=
finised and LDOFB pin voltage is over 90% of VREF  
the LDOPGOOD pin is pulled to high.  
,
Choose Rf2=7.5kW.  
Layout Considerations  
When ceramic capacitors or some low ESR bulk  
capacitors are chosen as LDO output capacitors, the  
zero caused by output capacitor ESR is so high that  
crossover frequency FO has to be chosen much higher  
than zero caused by RC and CC and much lower than  
zero caused by ESR . For example, 10uF ceramic is  
used as output capacitor. We select Fo=300kHz,  
Rf1=7.5kohm and select MOSFET SI4800(gm=19). RC  
and CC can be calculated as follows.  
The layout is very important when designing high  
frequency switching converters. Layout will affect noise  
pickup and can cause a good design to perform with  
less than expected results.  
There are two sets of components considered in  
the layout which are power components and small sig-  
nal components. Power components usually consist of  
input capacitors, high-side MOSFET, low-side  
MOSFET, inductor and output capacitors. A noisy en-  
vironment is generated by the power components due  
to the switching power. Small signal components are  
connected to sensitive pins or nodes. A multilayer lay-  
out which includes power plane, ground plane and sig-  
nal plane is recommended .  
VOUT  
1+gm ´  
2´ p ´ FO ´ CO  
IOUT  
VOUT  
IOUT  
RC =Rf1 ´  
´
gm  
gm ´  
1.5V  
2A  
1.5V  
1+19S´  
2´ p ´ 300kHz´ 20uF  
Layout guidelines:  
=7.5kW´  
´
19S  
19S´  
1. First put all the power components in the top  
layer connected by wide, copper filled areas. The input  
capacitor, inductor, output capacitor and the MOSFETs  
should be close to each other as possible. This helps  
to reduce the EMI radiated by the power loop due to  
the high switching currents through them.  
2A  
=14.9kW  
Typically RC is chosen to be 1 to 1.5 times smaller  
than calculated value to compensate parasitic effect.  
Choose RC=20kW.  
2. Low ESR capacitor which can handle input  
RMS ripple current and a high frequency decoupling  
ceramic cap which usually is 1uF need to be practi-  
cally touching the drain pin of the upper MOSFET, a  
plane connection is a must.  
10´ CO  
CC =  
RC ´ gm  
10 ´ 20uF  
=
20k19S  
=0.53nF  
3. The output capacitors should be placed as close  
as to the load as possible and plane connection is re-  
quired.  
Choose CC=1000pF.  
4. Drain of the low-side MOSFET and source of  
the high-side MOSFET need to be connected thru a  
plane and as close as possible. A snubber needs to be  
placed as close to this junction as possible.  
Current Limit for LDO  
Current limit of LDO is achieved by sensing the  
LDO feedback voltage. When LDO_FB pin is below  
Rev. 2.3  
03/19/09  
16  
NX2139A  
5. Source of the lower MOSFET needs to be con-  
nected to the GND plane with multiple vias. One is not  
enough. This is very important. The same applies to  
the output capacitors and input capacitors.  
6. Hdrv and Ldrv pins should be as close to  
MOSFET gate as possible. The gate traces should be  
wide and short. A place for gate drv resistors is needed  
to fine tune noise if needed.  
7. Vcc capacitor, BST capacitor or any other by-  
passing capacitor needs to be placed first around the  
IC and as close as possible. The capacitor on comp to  
GND or comp back to FB needs to be place as close to  
the pin as well as resistor divider.  
8. The output sense line which is sensing output  
back to the resistor divider should not go through high  
frequency signals, should be kept away from the in-  
ductor and other noise sources. The resistor divider  
must be located as close as possible to the FB pin of  
the device.  
9. All GNDs need to go directly thru via to GND  
plane.  
10. In multilayer PCB, separate power ground  
and analog ground. These two grounds must be con-  
nected together on the PC board layout at a single point.  
The goal is to localize the high current path to a sepa-  
rate loop that does not interfere with the more sensi-  
tive analog control function.  
Rev. 2.3  
03/19/09  
17  
NX2139A  
Demoboard Schematic  
BUS  
CIN3  
BUS  
1
4.7u/25V  
R7  
1M  
C6  
1n  
U1  
CIN2  
R4  
2.2  
13  
R11  
4.7u/25V  
BST  
4
5
PGOOD  
CIN1  
100k  
R8  
LIN_PGOOD  
VCCP  
10u/25V  
C17  
1u  
100k  
5V  
5V  
1
9
2
R2  
C16  
1u  
12  
4
M1  
IRF7807  
DH  
0
R6  
VCC  
VCC  
EN  
VOUT  
Lo  
10  
OUT  
C2  
1u  
11  
10  
1
2
SW  
DO5010H-152  
R3  
OCP  
CO2  
CO1  
15  
14  
10k  
4.7u/6.3V  
2R5TPE330MC  
R15  
2.2  
8
4
M2  
AO4714  
LIN_EN  
DL  
LDOIN  
C9  
1.5n  
LDOIN  
GND  
LDODRV  
M3  
SI4800  
4
7
LIN_DRV  
R18  
50  
1
3
VOUT  
R17  
20k  
LDOOUT  
LDOOUT  
C19  
33n  
R5  
10.5k  
C15  
330p  
C7  
10u  
C3  
10u  
R19  
7.5k  
C18  
1n  
6
LIN_FB  
FB  
R20  
7.5k  
R10  
7.5k  
Figure 14 - NX2139A schematic for the demoboard layout  
Rev. 2.3  
03/19/09  
18  
NX2139A  
Demoboard Layout  
Figure 15 Top layer  
Figure 16 Ground layer  
Rev. 2.3  
03/19/09  
19  
NX2139A  
Figure 17 Power layer  
Figure 18 Bottom layer  
Rev. 2.3  
03/19/09  
20  
NX2139A  
MLPQ 16 PIN 3 x 3 PACKAGE OUTLINE DIMENSIONS  
SYMBOL  
Dimensions In Millimeters  
Dimensions In Inches  
NAME  
A
A1  
A3  
B
D
D2  
E
MIN  
0.700  
0.000  
MAX  
0.800  
0.050  
MIN  
0.028  
0.000  
MAX  
0.031  
0.002  
0.203REF  
0.008REF  
0.180  
2.950  
1.600  
2.950  
1.600  
0.300  
3.050  
1.750  
3.050  
1.750  
0.007  
0.116  
0.063  
0.116  
0.063  
0.012  
0.120  
0.069  
0.120  
0.069  
E2  
e
L
0.50BSC  
1.5REF  
0.50BSC  
0.325  
0.450  
0.013  
0.018  
M
0.059REF  
Rev. 2.3  
03/19/09  
21  
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