NX2141
This power dissipation should not exceed maxi-
mum power dissipation of the driver device.
Power MOSFETs Selection
The NX2141 requires two N-Channel power
MOSFETs. The selection of MOSFETs is based on
maximum drain source voltage, gate source voltage,
maximum current rating, MOSFET on resistance and
power dissipation. The main consideration is the power
Over Current Limit Protection
Over current Limit for step down converter is
achieved by sensing current through the low side
MOSFET. For NX2141, the current limit is decided by
the RDSON of the low side mosfet. When synchronous
FET is on, and the voltage on SW pin is below 320mV,
the over current occurs. The over current limit can be
calculated by the following equation.
loss contribution of MOSFETs to the overall converter
efficiency. For example, two IRF7822 are used in appli-
cation. They have the following parameters: VDS=30V, ID
=18A,RDSON =6.5mW,QGATE =44nC.
There are two factors causing the MOSFET power
loss:conduction loss, switching loss.
Conduction loss is simply defined as:
ISET = 320mV/RDSON
The MOSFET RDSON is calculated in the worst case
situation, then the current limit for MOSFET IRF7822 is
P
HCON =IOUT2 ´ D´ RDS(ON) ´ K
LCON=IOUT2 ´ (1- D)´ RDS(ON) ´ K
PTOTAL =P + P
320mV
320mV
ISET
=
=
= 35A
P
...(20)
RDSON 1.4´ 6.5mW
HCON
LCON
where the RDS(ON) will increases as MOSFET junc-
tion temperature increases, K is RDS(ON) temperature
dependency. As a result, RDS(ON) should be selected for
the worst case, in which K approximately equals to 1.4
at 125oC according to datasheet. Conduction loss should
not exceed package rating or overall system thermal
budget.
Layout Considerations
The layout is very important when designing high
frequency switching converters. Layout will affect noise
pickup and can cause a good design to perform with
less than expected results.
There are two sets of components considered in
the layout which are power components and small sig-
nal components. Power components usually consist of
input capacitors, high-side MOSFET, low-side MOSFET,
inductor and output capacitors. A noisy environment is
generated by the power components due to the switch-
ing power. Small signal components are connected to
sensitive pins or nodes. A multilayer layout which in-
cludes power plane, ground plane and signal plane is
recommended .
Switching loss is mainly caused by crossover
conduction at the switching transition. The total
switching loss can be approximated.
1
PSW
=
´ V ´ IOUT ´ TSW ´ F
IN S
...(21)
2
where IOUT is output current, TSW is the sum of TR
and TF which can be found in mosfet datasheet, and FS
is switching frequency. Swithing loss PSW is frequency
dependent.
Layout guidelines:
Also MOSFET gate driver loss should be consid-
ered when choosing the proper power MOSFET.
MOSFET gate driver loss is the loss generated by dis-
charging the gate capacitor and is dissipated in driver
circuits.It is proportional to frequency and is defined as:
1. First put all the power components in the top
layer connected by wide, copper filled areas. The input
capacitor, inductor, output capacitor and the MOSFETs
should be close to each other as possible. This helps to
reduce the EMI radiated by the power loop due to the
high switching currents through them.
Pgate = (QHGATE ´ VHGS + QLGATE ´ VLGS )´ FS
...(22)
2. Low ESR capacitor which can handle input RMS
ripple current and a high frequency decoupling ceramic
cap which usually is 1uF need to be practically touch-
where QHGATE is the high side MOSFETs gate
charge,QLGATE is the low side MOSFETs gate charge,VHGS
is the high side gate source voltage, and VLGS is the low
side gate source voltage.
Rev. 1.6
05/15/07
18
