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NX2154ACSTR

型号:

NX2154ACSTR

描述:

300kHz的同步PWM控制器[ 300kHz SYNCHRONOUS PWM CONTROLLER ]

品牌:

MICROSEMI[ Microsemi ]

页数:

17 页

PDF大小:

556 K

Evaluation board available.  
NX2154/2154A  
300kHz SYNCHRONOUS PWM CONTROLLER  
PRELIMINARY DATA SHEET  
Pb Free Product  
FEATURES  
DESCRIPTION  
n
Bus voltage operation from 2V to 40V  
The NX2154/2154A controller IC is a synchronous Buck  
controller IC designed for step down DC to DC con-  
verter applications. It is optimized to convert bus volt-  
ages from 2V to 40V to outputs as low as 0.8V voltage.  
The NX2154/2154A operates at fixed 300kHz. The  
NX2154/2154A employs fixed loss-less current limiting  
by sensing the Rdson of synchronous MOSFET followed  
by hiccup feature.NX2154A has higher current limit  
threshold than NX2154. Feedback under voltage also  
triggers hiccup.  
n Fixed 300kHz voltage mode controller  
n Internal Digital Soft Start Function  
n Prebias Startup  
n Less than 50 nS adaptive deadband  
n
n
Current limit triggers hiccup by sensing Rdson of  
Synchronous MOSFET  
No negative spike at Vout during startup and  
shutdown  
n Pb-free and RoHS compliant  
Other features of the device are: 5V gate drive,Adaptive  
deadband control, Internal digital soft start, Vcc  
undervoltage lock out and shutdown capability via the  
comp pin.  
APPLICATIONS  
n
n
n
Graphic Card on board converters  
Memory Vddq Supply in mother board applications  
On board DC to DC such as  
5V to 3.3V, 2.5V or 1.8V  
Hard Disk Drive  
n
n
Set Top Box  
TYPICAL APPLICATION  
Vin  
Vin  
+33V  
+5V  
MBR0530T1  
1uF  
50ME180WX  
1uF  
5
1
BST  
Vcc  
0.1uF  
M1A STM6920  
15uH  
7
2
Comp  
Hdrv  
M3  
12nF  
HI=SD  
Vout  
+5V,3A  
82pF  
8
4
SW  
Ldrv  
13.3k  
6
M1B  
6ME1000WG(1000uF,30mohm)  
Fb  
Gnd  
3
1k  
191  
Figure1 - Typical application of 2154  
ORDERING INFORMATION  
Device  
NX2154CSTR  
NX2154ACSTR  
Temperature  
0 to 70oC  
0 to 70o C  
Package  
SOIC-8L  
SOIC-8L  
Frequency  
300kHz  
300kHz  
OCP Threshold  
360mV  
Pb-Free  
Yes  
Yes  
540mV  
Rev.1.2  
02/26/07  
1
NX2154/2154A  
ABSOLUTE MAXIMUM RATINGS(NOTE1)  
Vcc to GND & BST to SW voltage ................... 6.5V  
BST to GND Voltage ...................................... 50V  
Storage Temperature Range ............................. -65oC to 150oC  
Operating Junction Temperature Range ............. -40oC to 125oC  
NOTE1: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent  
damage to the device. This is a stress only rating and operation of the device at these or any other  
conditions above those indicated in the operational sections of this specification is not implied.  
PACKAGE INFORMATION  
8-PIN PLASTIC SOIC (S)  
qJA » 130o C/W  
BST  
HDrv  
Gnd  
1
2
3
4
8
7
6
5
SW  
Comp  
Fb  
LDrv  
Vcc  
ELECTRICAL SPECIFICATIONS  
Unless otherwise specified, these specifications apply over Vcc = 5V, and TA = 0 to 70oC. Typical values refer to TA  
= 25oC. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient  
temperature.  
PARAMETER  
Reference Voltage  
Ref Voltage  
SYM  
Test Condition  
Min  
TYP  
MAX Units  
VREF  
4.5V<Vcc<5.5V  
0.8  
0.4  
V
Ref Voltage line regulation  
Supply Voltage(Vcc)  
VCC Voltage Range  
VCC Supply Current (Static)  
VCC Supply Current  
(Dynamic)  
%
VCC  
5
3
5
V
4.5  
5.5  
ICC (Static) Outputs not switching  
mA  
mA  
ICC  
(Dynamic)  
CLOAD=3300pF FS=300kHz  
Supply Voltage(VBST  
)
VBST Supply Current (Static)  
IBST (Static) Outputs not switching  
0.15  
5
mA  
mA  
VBST Supply Current  
(Dynamic)  
IBST  
CLOAD=3300pF FS=300kHz  
(Dynamic)  
Under Voltage Lockout  
VCC-Threshold  
VCC_UVLO VCC Rising  
VCC_Hyst VCC Falling  
4.2  
V
V
VCC-Hysteresis  
0.22  
Rev.1.2  
02/26/07  
2
NX2154/2154A  
PARAMETER  
SYM  
Test Condition  
Fsw=300Khz  
Min  
TYP  
MAX Units  
SS  
Soft Start time  
Tss  
3.4  
mS  
Oscillator (Rt)  
Frequency  
FS  
300  
1.6  
84  
kHz  
V
Ramp-Amplitude Voltage  
Max Duty Cycle  
VRAMP  
%
Min Duty Cycle  
%
0
Error Amplifiers  
Transconductance  
Input Bias Current  
Comp SD Threshold  
FBUVLO  
2000  
10  
umho  
nA  
Ib  
0.3  
V
Feedback UVLO threshold  
High Side Driver(CL=2200pF)  
Output Impedance , Sourcing  
Output Impedance , Sinking  
Sourcing Current  
Sinking Current  
percent of nominal  
70  
%
65  
75  
Rsource(Hdrv)  
Rsink(Hdrv)  
Isource(Hdrv)  
Isink(Hdrv)  
I=200mA  
I=200mA  
1.9  
1.7  
1
ohm  
ohm  
A
1.2  
14  
17  
30  
A
Rise Time  
THdrv(Rise)  
THdrv(Fall)  
ns  
Fall Time  
ns  
Deadband Time  
Tdead(L to Ldrv going Low to Hdrv  
ns  
H)  
going High, 10%-10%  
Low Side Driver (CL=2200pF)  
Output Impedance, Sourcing  
Current  
Output Impedance, Sinking  
Current  
Rsource(Ldrv)  
Rsink(Ldrv)  
I=200mA  
I=200mA  
1.9  
1
ohm  
ohm  
Sourcing Current  
Isource(Ldrv)  
Isink(Ldrv)  
1
2
A
A
Sinking Current  
Rise Time  
Fall Time  
Deadband Time  
TLdrv(Rise)  
TLdrv(Fall)  
Tdead(H to SW going Low to Ldrv  
13  
12  
10  
ns  
ns  
ns  
L)  
going High, 10% to 10%  
OCP  
OCP voltage  
NX2154  
NX2154A  
360  
540  
mV  
Rev.1.2  
02/26/07  
3
NX2154/2154A  
PIN DESCRIPTIONS  
PIN #  
PIN SYMBOL  
PIN DESCRIPTION  
This pin supplies voltage to the high side driver. A high frequency  
1
BST  
ceramic capacitor of 0.1 to 1 uF must be connected from this pin to SW pin.  
High side MOSFET gate driver.  
Ground pin.  
2
3
4
HDRV  
GND  
Low side MOSFET gate driver. For the high current application, a 4.7nF capaci-  
tor is recommend to placed on low side MOSFET's gate to ground. This is to  
prevent undesired Cdv/dt induced low side MOSFET's turn on to happen, which  
is caused by fast voltage change on the drain of low side MOSFET in synchro-  
nous buck converter and lower the system efficiency.  
LDRV  
Voltage supply for the internal circuit as well as the low side MOSFET gate  
driver. A 1uF high frequency ceramic capacitor must be connected from this pin  
to GND pin.  
5
6
7
Vcc  
This pin is the error amplifier inverting input. This pin is also connected to the  
output UVLO comparator. When this pin falls below 0.56V, both HDRV and  
LDRV outputs are in hiccup.  
FB  
This pin is the output of the error amplifier and together with FB pin is used to  
compensate the voltage control feedback loop. This pin is also used as a shut  
down pin. When this pin is pulled below 0.3V, both drivers are turned off and  
internal soft start is reset.  
COMP  
This pin is connected to the source of the high side MOSFET and provides  
return path for the high side driver. Also SW senses the low side MOSFETS  
current, when the pin voltage is lower than 360mV for NX2154, 540mV for NX2154A,  
hiccup will be triggered.  
8
SW  
Rev.1.2  
02/26/07  
4
NX2154/2154A  
BLOCK DIAGRAM  
VCC  
70%Vp  
FB  
Hiccup Logic  
1.25V  
0.8V  
OC  
Bias  
Generator  
BST  
UVLO  
POR  
START  
HDRV  
SW  
COMP  
0.3V  
OC  
Control  
Logic  
START  
0.8V  
VCC  
PWM  
OSC  
ramp  
Digital  
start Up  
S
R
LDRV  
Q
FB  
0.6V  
CLAMP  
360mV/540mV  
1.3V  
CLAMP  
COMP  
Hiccup Logic  
START  
OCP  
comparator  
GND  
Figure 2 - Simplified block diagram of the NX2154/NX2154A  
Rev.1.2  
02/26/07  
5
NX2154/2154A  
V -VOUT VOUT  
1
IN  
DIRIPPLE  
=
=
´
´
APPLICATION INFORMATION  
LOUT  
V
F
S
IN  
Symbol Used In Application Information:  
...(2)  
33V-5V 5V  
1
´
´
= 0.94A  
VIN  
- Input voltage  
- Output voltage  
- Output current  
15uH 33V 300kHz  
VOUT  
IOUT  
Output Capacitor Selection  
VRIPPLE - Output voltage ripple  
- Working frequency  
Output capacitor is basically decided by the  
amount of the output voltage ripple allowed during steady  
state(DC) load condition as well as specification for the  
load transient. The optimum design may require a couple  
of iterations to satisfy both condition.  
FS  
IRIPPLE - Inductor current ripple  
Design Example  
Based on DC Load Condition  
The following is typical application for NX2154, the  
The amount of voltage ripple during the DC load  
condition is determined by equation(3).  
schematic is figure 1.  
VIN = 33V  
VOUT=5V  
DIRIPPLE  
DVRIPPLE = ESR´ DIRIPPLE  
+
FS=300kHz  
8´ F ´ COUT  
...(3)  
S
IOUT=3A  
Where ESR is the output capacitors' equivalent  
series resistance,COUT is the value of output capacitors.  
Typically when large value capacitors are selected  
such as Aluminum Electrolytic,POSCAP and OSCON  
types are used, the amount of the output voltage ripple  
is dominated by the first term in equation(3) and the  
second term can be neglected.  
VRIPPLE <=50mV  
VDROOP<=250mV @ 9A step  
Output Inductor Selection  
The selection of inductor value is based on induc-  
tor ripple current, power rating, working frequency and  
efficiency. Larger inductor value normally means smaller  
ripple current. However if the inductance is chosen too  
large, it brings slow response and lower efficiency. Usu-  
ally the ripple current ranges from 20% to 40% of the  
output current. This is a design freedom which can be  
decided by design engineer according to various appli-  
cation requirements. The inductor value can be calcu-  
lated by using the following equations:  
For this example,electrolytic capacitors are cho-  
sen as output capacitors, the ESR and inductor current  
typically determines the output voltage ripple.  
DVRIPPLE  
DIRIPPLE  
50mV  
0.94A  
ESRdesire  
=
=
= 53mW  
...(4)  
If low ESR is required, for most applications, mul-  
tiple capacitors in parallel are better than a big capaci-  
tor. For example, SANYO electrolytic capacitor  
6ME1000WG (1000uF,30mW) is chosen.  
V -VOUT VOUT  
1
IN  
LOUT  
=
´
´
DIRIPPLE  
V
F
S
IN  
...(1)  
E S R E ´ DIR IPPLE  
N =  
IRIPPLE =k ´ IOUTPUT  
...(5)  
D VR IPPLE  
where k is between 0.2 to 0.4.  
Select k=0.3, then  
Number of Capacitor is calculated as  
30m0.94A  
N =  
33V-5V 5V  
1
LOUT  
=
´
´
50mV  
0.3´ 3A 33V 300kHz  
LOUT =15.7uH  
N =0.566  
The number of capacitor has to be round up to a  
integer. Choose N =1.  
If ceramic capacitors are chosen as output ca  
Choose inductor from COILCRAFT DO5022P-153  
with L=15uH is a good choice.  
Current Ripple is recalculated as  
Rev.1.2  
02/26/07  
6
NX2154/2154A  
pacitors, both terms in equation (3) need to be evalu- of output capacitor. For low frequency capacitor such  
ated to determine the overall ripple. Usually when this as electrolytic capacitor, the product of ESR and ca-  
type of capacitors are selected, the amount of capaci-  
tance per single unit is not sufficient to meet the tran-  
sient specification, which results in parallel configura-  
tion of multiple capacitors .  
pacitance is high and L £ Lcrit is true. In that case, the  
transient spec is dependent on the ESR of capacitor.  
In most cases, the output capacitors are multiple  
capacitors in parallel. The number of capacitors can be  
calculated by the following  
For example, one 100uF, X5R ceramic capacitor  
with 2mW ESR is used. The amount of output ripple is  
ESRE ´ DIstep  
VOUT  
N =  
+
´ t 2  
...(9)  
0.94A  
DV  
2´ L´ CE ´ DV  
tran  
tran  
DV  
= 2mW´ 0.94A +  
= 5.4mV  
RIPPLE  
8´ 300kHz´ 100uF  
where  
0
if L £ Lcrit  
ì
Although this meets DC ripple spec, however it  
needs to be studied for transient requirement.  
Based On Transient Requirement  
ï
L´ DI  
t =  
í
ï
î
step  
...(10)  
- ESRE ´ CE  
if L ³ Lcrit  
VOUT  
Typically, the output voltage droop during transient  
is specified as:  
For example, assume voltage droop during tran-  
sient is 250mV for 3A load step.  
DVDROOP <DVTRAN @ step load ISTEP  
If the SANYO electrolytic capaictor 6ME1000WG  
(1000uF, 30mW ) is used, the critical inductance is given  
as  
During the transient, the voltage droop during the  
transient is composed of two sections. One Section is  
dependent on the ESR of capacitor, the other section is  
a function of the inductor, output capacitance as well as  
input, output voltage. For example, for the overshoot,  
when load from high load to light load with a ISTEP  
transient load, if assuming the bandwidth of system is  
high enough, the overshoot can be estimated as the fol-  
lowing equation.  
ESRE ´ CE ´ VOUT  
Lcrit  
=
=
DIstep  
30m1000mF ´ 5V  
= 50mH  
3A  
The selected inductor is 15uH which is smaller than  
critical inductance. In that case, the output voltage tran-  
sient only dependent on the ESR.  
VOUT  
´ t 2  
number of capacitors is  
DVovershoot = ESR ´ DIstep  
+
...(6)  
2´ L´ COUT  
where is the a function of capacitor, etc.  
ESRE ´ DIstep  
VOUT  
t
N =  
+
´ t 2  
DV  
2´ L´ CE ´ DV  
tran  
tran  
0
if L £ Lcrit  
ì
30m3A  
ï
L´ DI  
t =  
=
+
í
ï
î
step  
...(7)  
...(8)  
- ESR ´ COUT  
if L ³ Lcrit  
250mV  
VOUT  
5V  
´ (0)2  
where  
ESR ´ COUT ´ VOUT ESRE ´ CE ´ VOUT  
2´ 15mH´ 1000mF´ 250mV  
= 0.36  
Lcrit  
=
=
DIstep  
DIstep  
The number of capacitors has to satisfied both ripple  
where ESRE and CE represents ESR and capaci-  
tance of each capacitor if multiple capacitors are used  
in parallel.  
and transient requirement. Overall, we can choose N=1.  
The above equation shows that if the selected out-  
put inductor is smaller than the critical inductance, the  
voltage droop or overshoot is only dependent on the ESR  
Rev.1.2  
02/26/07  
7
NX2154/2154A  
It should be considered that the proposed equa-  
tion is based on ideal case, in reality, the droop or over-  
shoot is typically more than the calculation. The equa-  
tion gives a good start. For more margin, more capaci-  
tors have to be chosen after the test. Typically, for high  
frequency capacitor such as high quality POSCAP es-  
pecially ceramic capacitor, 20% to 100% (for ceramic)  
more capacitors have to be chosen since the ESR of  
capacitors is so low that the PCB parasitic can affect  
the results tremendously. More capacitors have to be  
selected to compensate these parasitic parameters.  
1
FZ1  
FZ2  
=
=
=
=
...(11)  
2´ p ´ R4 ´ C2  
1
...(12)  
...(13)  
...(14)  
2´ p ´ (R2 + R3 )´ C3  
1
F
P1  
2´ p ´ R3 ´ C3  
1
F
P2  
C1 ´ C2  
2´ p ´ R4 ´  
C1 + C2  
where FZ1,FZ2,FP1 and FP2 are poles and zeros in  
the compensator. Their locations are shown in figure 4.  
The transfer function of type III compensator for  
transconductance amplifier is given by:  
Compensator Design  
Due to the double pole generated by LC filter of the  
power stage, the power system has 180o phase shift ,  
and therefore, is unstable by itself. In order to achieve  
accurate output voltage and fast transient  
response,compensator is employed to provide highest  
possible bandwidth and enough phase margin.Ideally,the  
Bode plot of the closed loop system has crossover fre-  
quency between1/10 and 1/5 of the switching frequency,  
phase margin greater than 50o and the gain crossing  
0dB with -20dB/decade. Power stage output capacitors  
usually decide the compensator type. If electrolytic  
capacitors are chosen as output capacitors, type II com-  
pensator can be used to compensate the system, be-  
cause the zero caused by output capacitor ESR is lower  
than crossover frequency. Otherwise type III compensa-  
tor should be chosen.  
Ve  
1- gm ´ Zf  
=
VOUT  
1+ gm ´ Zin + Zin /R1  
For the voltage amplifier, the transfer function of  
compensator is  
Ve  
- Zf  
=
VOUT  
Zin  
To achieve the same effect as voltage amplifier,  
the compensator of transconductance amplifier must  
satisfy this condition: R4>>2/gm. And it would be desir-  
able if R1||R2||R3>>1/gm can be met at the same time.  
Zf  
Vout  
Zin  
R3  
C1  
A. Type III compensator design  
C2  
R4  
R2  
R1  
For low ESR output capacitors, typically such as  
Sanyo oscap and poscap, the frequency of ESR zero  
caused by output capacitors is higher than the cross-  
over frequency. In this case, it is necessary to compen-  
sate the system with type III compensator. The follow-  
ing figures and equations show how to realize the type III  
compensator by transconductance amplifier.  
C3  
Fb  
Ve  
gm  
Vref  
Figure 3 - Type III compensator using  
transconductance amplifier  
Rev.1.2  
02/26/07  
8
NX2154/2154A  
2. Set R2 equal to 10kW.  
Case 1: FLC<FESR<FO  
R2 ´ VREF  
10k0.8V  
R1=  
=
=1.91k W  
VOUT -V  
5V-0.8V  
REF  
Choose R1=1.91kW.  
3. Set zero FZ2 = FLC and Fp1 =FESR  
4. Calculate C3 .  
power stage  
.
LC  
F
40dB/decade  
1
1
1
C3 =  
´ (  
-
)
2´ p ´ R2  
F
F
p1  
z2  
ESR  
F
1
1
1
=
´ (  
-
)
2´ p ´ 10kW 1.3kHz 5.3kHz  
loop gain  
=9.2nF  
Choose C3=10nF.  
5. Calculate R3 .  
20dB/decade  
1
R3 =  
2´ p ´ F ´ C3  
P1  
compensator  
1
=
2´ p ´ 5.3kHz ´ 10nF  
= 3kW  
Choose R3 =3kW.  
6. Calculate R4 with FO=30kHz.  
FZ1  
FO  
FP2  
FZ2  
F
P1  
VOSC 2´ p ´ FO ´ L R2 ´ R3  
R4 =  
´
´
V
ESR  
R2 + R3  
in  
Figure 4 - Bode plot of Type III compensator  
(FLC<FESR<FO)  
1.5V 2´ p ´ 30kHz´ 15uH 10k3kW  
=
´
´
33V  
=9.9kW  
Choose R4=10kW.  
30mW  
10kW+ 3kW  
If electrolytic capacitors are used as output  
capacitors, typical design example of type III  
compensator in which the crossover frequency is  
selected as FLC<FESR<FO and FO<=1/10~1/5Fs is shown  
as the following steps. Here one SANYO 6ME1000WG  
with 30 mW is chosen as output capacitor.  
7. Calculate C2 with zero Fz1 at 75% of the LC  
double pole by equation (11).  
1
C2 =  
2 ´ p ´ FZ1 ´ R4  
1
1. Calculate the location of LC double pole FLC  
=
2 ´ p ´ 0.75 ´ 1.3kHz ´ 10kW  
= 12.2nF  
and ESR zero FESR  
.
1
Choose C2=12nF.  
8. Calculate C1 by equation (14) with pole Fp2 at  
half the switching frequency.  
F
=
=
LC  
2´ p ´  
L
OUT ´ COUT  
1
2´ p ´ 15uH´ 1000uF  
1
C1 =  
= 1.3kHz  
2 ´ p ´ R4 ´ FP2  
1
=
1
F
=
2 ´ p ´ 10k150kHz  
= 106pF  
ESR  
2´ p ´ ESR´ COUT  
1
=
Choose C1=100pF.  
2´ p ´ 30m1000uF  
= 5.3kHz  
Rev.1.2  
02/26/07  
9
NX2154/2154A  
Case 2: FLC<FO<FESR  
R2 ´ VREF  
10kW´ 0.8V  
= = 8kW  
R1 =  
VOUT -VREF  
1.8V-0.8V  
Choose R1=8kW.  
3. Set zero FZ2 = FLC and Fp1 =FESR  
power stage  
.
LC  
F
4. Calculate R4 and C3 with the crossover  
40dB/decade  
frequency at 1/10~ 1/5 of the switching frequency. Set  
FO=30kHz.  
1
1
1
C3 =  
´ (  
-
)
2´ p ´ R2  
F
F
p1  
z2  
loop gain  
ESR  
F
1
1
1
=
´ (  
-
)
2´ p ´ 10kW 6.2kHz 60.3kHz  
=2.3nF  
20dB/decade  
VOSC 2´ p ´ FO ´ L  
compensator  
R4 =  
=
´
´ Cout  
V
C3  
1.5V 2´ p ´ 30kHz´ 1.5uH  
in  
´
´ 440uF  
5V  
=16.9kW  
Choose C3=2.2nF, R4=16.9kW.  
2.2nF  
FZ1  
FO  
FP2  
FZ2  
FP1  
5. Calculate C2 with zero Fz1 at 75% of the LC  
double pole by equation (11).  
Figure 5 - Bode plot of Type III compensator  
1
C2 =  
2´ p ´ FZ1 ´ R4  
Design example for type III compensator are in  
order. The crossover frequency has to be selected as  
FLC<FO<FESR and FO<=1/10~1/5Fs. In this case, input  
voltage is 5V, output voltage is 1.8V, inductor is 1.5uH,  
two POSCAP 2R5TPE220MC(220uF,12 mW) are chosen  
as output capacitor.  
1
=
2´ p ´ 0.75´ 6.2kHz´ 16.9kW  
= 2nF  
Choose C2=2.2nF.  
6. Calculate C1 by equation (14) with pole Fp2 at  
half the switching frequency.  
1.Calculate the location of LC double pole FLC  
1
C1 =  
and ESR zero FESR  
.
2´ p ´ R4 ´ F  
P2  
1
1
=
F
=
=
LC  
2´ p ´ 16.9k150kHz  
= 63pF  
2´ p ´  
L
OUT ´ COUT  
1
Choose C1=68pF.  
7. Calculate R3 by equation (13).  
2´ p ´ 1.5uH´ 440uF  
= 6.2kHz  
1
R3 =  
1
2´ p ´ F ´ C3  
FESR  
=
P1  
2 ´ p ´ ESR ´ COUT  
1
1
=
2´ p ´ 60.3kHz´ 2.2nF  
=1.2kW  
=
2 ´ p ´ 6m440uF  
= 60.3kHz  
Choose R3=1.2kW.  
2. Set R2 equal to 10kW.  
Rev.1.2  
02/26/07  
10  
NX2154/2154A  
B. Type II compensator design  
If the electrolytic capacitors are chosen as power  
stage output capacitors, usually the Type II compensa-  
tor can be used to compensate the system.  
Type II compensator can be realized by simple RC  
circuit without feedback as shown in figure 6. R3 and C1  
introduce a zero to cancel the double pole effect. C2  
introduces a pole to suppress the switching noise. The  
following equations show the compensator pole zero lo-  
cation and constant gain.  
Vout  
R2  
Fb  
Ve  
gm  
R1  
R3  
C2  
Vref  
C1  
R1  
Gain=gm ´  
´ R3  
... (15)  
... (16)  
... (17)  
R1+R2  
Figure 7 - Type II compensator with  
transconductance amplifier  
1
F =  
z
2´ p ´ R3 ´ C1  
1
For this type of compensator, FO has to satisfy  
FLC<FESR<<FO<=1/10~1/5Fs.  
F »  
p
2´ p ´ R3 ´ C2  
The following is parameters for type II compensa-  
tor design. Input voltage is 40V, output voltage is 5V,  
output inductor is 6uH, output capacitor is one 1000uF  
with 30mW electrolytic capacitors.  
power stage  
1.Calculate the location of LC double pole FLC  
40dB/decade  
and ESR zero FESR  
.
1
loop gain  
F
=
=
LC  
2´ p ´  
L
OUT ´ COUT  
1
20dB/decade  
2´ p ´ 15uH´ 1000uF  
= 1.3kHz  
1
compensator  
F
=
=
ESR  
2´ p ´ ESR´ COUT  
1
Gain  
2´ p ´ 30m1000uF  
= 5.3kHz  
P
F
F
F
Z
LCFESR  
FO  
2.Set R2 equal to 1kW.  
R2 ´ VREF  
1k0.8V  
R1=  
=
= 191W  
Figure 6 - Bode plot of Type II compensator  
VOUT -VREF  
5V-0.8V  
Choose R1=191W.  
3. Set crossover frequency at 1/10~ 1/5 of the  
swithing frequency, here FO=30kHz.  
4.Calculate R3 value by the following equation.  
Rev.1.2  
02/26/07  
11  
NX2154/2154A  
4.Calculate R3 value by the following equation.  
VOSC 2 ´ p ´ FO ´ L VOUT  
Vout  
1
R3 =  
´
´
´
V
RESR  
gm VREF  
R2  
in  
Fb  
1.5V 2´ p ´ 30kHz´ 15uH  
1
=
´
´
33V  
30mW  
2.0mA/V  
R1  
5V  
´
Vref  
0.8V  
=13.3kW  
Voltage divider  
Choose R3 =13.3kW.  
5. Calculate C1 by setting compensator zero FZ  
at 75% of the LC double pole.  
Figure 8 - Voltage divider  
Input Capacitor Selection  
1
C1=  
Input capacitors are usually a mix of high frequency  
ceramic capacitors and bulk capacitors. Ceramic ca-  
pacitors bypass the high frequency noise, and bulk ca-  
pacitors supply switching current to the MOSFETs. Usu-  
ally 1uF ceramic capacitor is chosen to decouple the  
high frequency noise.The bulk input capacitors are de-  
cided by voltage rating and RMS current rating. The RMS  
current in the input capacitors can be calculated as:  
2´ p ´ R3 ´ F  
z
1
=
2´ p ´ 13.3k0.75´ 1.3kHz  
=12.2nF  
Choose C1=12nF.  
F
6. Calculate C2 by setting compensator pole  
at half the swithing frequency.  
p
1
C 2 =  
IRMS = IOUT ´ D ´ 1-D  
p ´ R 3 ´ Fs  
VOUT  
1
D =  
=
V
p ´ 1 3 .3k W ´ 3 0 0 k H z  
IN  
...(19)  
= 8 0 p F  
VIN = 33V, VOUT=5V, IOUT=3A, using equation (19),  
the result of input RMS current is 1.1A.  
Choose C1=82pF.  
For higher efficiency, low ESR capacitors are rec-  
ommended. One Sanyo electrolytic capacitor  
50ME180WX 50V 180uF 46mW with 1.19A RMS rating  
is chosen as input bulk capacitors.  
Output Voltage Calculation  
Output voltage is set by reference voltage and  
external voltage divider. The reference voltage is fixed  
at 0.8V. The divider consists of two ratioed resistors  
so that the output voltage applied at the Fb pin is 0.8V  
when the output voltage is at the desired value. The  
following equation and picture show the relationship  
between VOUT , VREF and voltage divider.  
Power MOSFETs Selection  
The power stage requires two N-Channel power  
MOSFETs. The selection of MOSFETs is based on  
maximum drain source voltage, gate source voltage,  
maximum current rating, MOSFET on resistance and  
power dissipation. The main consideration is the power  
loss contribution of MOSFETs to the overall converter  
efficiency. In this design example, two STM6920 are used.  
They have the following parameters: VDS=40V, ID  
=7A,RDSON =45mW,QGATE =8.7nC.  
R 2 ´ VREF  
R1=  
...(18)  
VOUT -VREF  
where R2 is part of the compensator, and the  
value of R1 value can be set by voltage divider.  
See compensator design for R1 and R2 selection.  
There are two factors causing the MOSFET power  
loss:conduction loss, switching loss.  
Rev.1.2  
02/26/07  
12  
NX2154/2154A  
Conduction loss is simply defined as:  
HCON =IOUT2 ´ D´ RDS(ON) ´ K  
LCON=IOUT2 ´ (1- D)´ RDS(ON) ´ K  
PTOTAL =P + P  
360mV  
ISET  
=
K ´ RDSON  
P
If MOSFET RDSON=45mW, the worst case thermal  
consideration K=1.5, then  
P
...(20)  
HCON  
LCON  
320mV  
360mV  
ISET  
=
=
= 5.3A  
where the RDS(ON) will increases as MOSFET junc-  
tion temperature increases, K is RDS(ON) temperature  
dependency. As a result, RDS(ON) should be selected for  
the worst case, in which K approximately equals to 1.5  
at 125oC according to STM6920 datasheet. Conduction  
loss should not exceed package rating or overall sys-  
tem thermal budget.  
K ´ RDSON 1.5´ 45mW  
Layout Considerations  
The layout is very important when designing high  
frequency switching converters. Layout will affect noise  
pickup and can cause a good design to perform with  
less than expected results.  
Switching loss is mainly caused by crossover con-  
duction at the switching transition. The total switching  
loss can be approximated.  
There are two sets of components considered in  
the layout which are power components and small sig-  
nal components. Power components usually consist of  
input capacitors, high-side MOSFET, low-side MOSFET,  
inductor and output capacitors. A noisy environment is  
generated by the power components due to the switch-  
ing power. Small signal components are connected to  
sensitive pins or nodes. A multilayer layout which in-  
cludes power plane, ground plane and signal plane is  
recommended .  
1
PSW  
=
´ V ´ IOUT ´ TSW ´ F  
IN S  
...(21)  
2
where IOUT is output current, TSW is the sum of TR  
and TF which can be found in mosfet datasheet, and FS  
is switching frequency. Switching loss PSW is frequency  
dependent.  
Also MOSFET gate driver loss should be consid-  
ered when choosing the proper power MOSFET.  
MOSFET gate driver loss is the loss generated by dis-  
charging the gate capacitor and is dissipated in driver  
circuits.It is proportional to frequency and is defined as:  
Layout guidelines:  
1. First put all the power components in the top  
layer connected by wide, copper filled areas. The input  
capacitor, inductor, output capacitor and the MOSFETs  
should be close to each other as possible. This helps to  
reduce the EMI radiated by the power loop due to the  
high switching currents through them.  
Pgate = (QHGATE ´ VHGS + QLGATE ´ VLGS )´ FS  
...(22)  
where QHGATE is the high side MOSFETs gate  
charge,QLGATE is the low side MOSFETs gate charge,VHGS  
is the high side gate source voltage, and VLGS is the low  
2. Low ESR capacitor which can handle input RMS  
ripple current and a high frequency decoupling ceramic  
cap which usually is 1uF need to be practically touch-  
ing the drain pin of the upper MOSFET, a plane connec-  
tion is a must.  
side gate source voltage.  
This power dissipation should not exceed maxi-  
mum power dissipation of the driver device.  
Over Current Limit Protection  
3. The output capacitors should be placed as close  
as to the load as possible and plane connection is re-  
quired.  
Over current Limit for step down converter is  
achieved by sensing current through the low side  
MOSFET. For NX2154, the current limit is decided by  
the RDSON of the low side mosfet. When synchronous  
FET is on, and the voltage on SW pin is below 360mV,  
the over current occurs. The over current limit can be  
calculated by the following equation.  
4. Drain of the low-side MOSFET and source of  
the high-side MOSFET need to be connected thru a plane  
ans as close as possible.A snubber nedds to be placed  
as close to this junction as possible.  
5. Source of the lower MOSFET needs to be con-  
Rev.1.2  
02/26/07  
13  
NX2154/2154A  
nected to the GND plane with multiple vias. One is not back to the resistor divider should not go through high  
enough. This is very important. The same applies to the frequency signals.  
output capacitors and input capacitors.  
9. All GNDs need to go directly thru via to GND  
6. Hdrv and Ldrv pins should be as close to plane.  
MOSFET gate as possible. The gate traces should be  
10. The feedback part of the system should be  
wide and short. A place for gate drv resistors is needed kept away from the inductor and other noise sources,  
to fine tune noise if needed.  
and be placed close to the IC.  
7. Vcc capacitor, BST capacitor or any other by-  
11. In multilayer PCB, separate power ground and  
passing capacitor needs to be placed first around the IC analog ground. These two grounds must be connected  
and as close as possible. The capacitor on comp to together on the PC board layout at a single point. The  
GND or comp back to FB needs to be place as close to goal is to localize the high current path to a separate  
the pin as well as resistor divider.  
loop that does not interfere with the more sensitive ana-  
8. The output sense line which is sensing output log control function.  
TYPICAL APPLICATION FOR HIGH CURRENT  
L2 1uH  
Vin  
+12V  
C3  
33uF  
C5  
1uF  
Cin  
2 x 16SP180M  
D1 MBR0530T1  
Vin  
C6  
1uF  
+5V  
5
1
C4  
0.1uF  
Vcc  
BST  
7
2
8
M1 IRF3706  
L1 1uH  
Comp  
Hdrv  
M3  
C2  
HI=SD  
C1  
220pF  
15nF  
Vout  
SW  
R4  
5k  
+1.8V,20A  
Co  
M2  
2 x IRF3706  
2 x (1500uF,13mohm)  
6
4
Ldrv  
Fb  
C7 4.7nF  
Gnd  
3
R1 1k  
R2  
800  
Figure 9 - High output current application of 2154  
Rev.1.2  
02/26/07  
14  
NX2154/2154A  
TYPICAL APPLICATION FOR LED  
Vin  
+5V  
78L05  
+9V to 33V  
D1 MBR0530T1  
1uF  
10k  
1uF  
220uF  
5
1
0.1uF  
BST  
Vcc  
1N4148  
1uF  
7
2
8
4
Comp  
Fb  
Hdrv  
IRF7341  
10uH  
68nF  
Vout  
SW  
56pF  
1.6k  
6
Co  
N X 2 1 5 4  
1000uF,30mohm  
Ldrv  
Gnd  
3
LUXEON III star LED  
LM358  
0.1ohm  
POT 100k  
1k  
Figure 10 - NX2154 LED application  
Waveforms for LED application  
0.9  
0.85  
0.8  
0.75  
0.7  
0.65  
0.6  
0.55  
0
0.2  
0.4  
0.6  
0.8  
1
1.2  
LED CURRENT(A)  
Figure 11 - LED application efficiency  
(One LUXEDN III star LED, VIN=12V)  
Figure 12 - Startup in NX2154 LED application  
Rev.1.2  
02/26/07  
15  
NX2154/2154A  
SOIC8 PACKAGE OUTLINE DIMENSIONS  
Rev.1.2  
02/26/07  
16  
NX2154/2154A  
Rev.1.2  
02/26/07  
17  
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