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NX2113CUTR

型号：

NX2113CUTR

描述：

与可编程总线欠压锁定为300kHz和600kHz的同步PWM控制器[ 300kHz & 600kHz SYNCHRONOUS PWM CONTROLLER WITH PROGRAMMABLE BUS UVLO ]

品牌：

MICROSEMI[ Microsemi ]

页数：

19 页

PDF大小：

724 K

下载PDF手册
Evaluation board available.  
NX2113/2113A  
300kHz & 600kHz SYNCHRONOUS PWM CONTROLLER WITH  
PROGRAMMABLE BUS UVLO  
PRELIMINARY DATA SHEET  
Pb Free Product  
FEATURES  
DESCRIPTION  
n Synchronous Controller in 10 Pin Package  
The NX2113 controller IC is a synchronous Buck con-  
troller IC designed for step down DC to DC converter  
applications. Synchronous control operation replaces the  
traditional catch diode with an Nch MOSFET resulting  
in improved converter efficiency. The NX2113 controller  
is optimized to convert bus voltages from 2V to 25V to  
outputs as low as 0.8V voltage using Enable pin to  
program the BUS voltage start up threshold. The NX2113  
operates at 300kHz while 2113A is set at 600kHz  
operation which together with less than 50 nS of dead  
band provides an efficient and cost effective solution.  
Other features of the device are:  
n
n
n
Bus voltage operation from 2V to 25V  
Enable pin allows programmable BUS UVLO  
Less than 50 nS adaptive deadband  
n Internal 300kHz for 2113 and 600kHz for 2113A  
n Internal Digital Soft Start Function  
n Separated power ground and analog ground for  
extra noise filtering  
n Pb-free and RoHS compliant  
APPLICATIONS  
n
n
n
Graphic Card on board converters  
Memory Vcore or Vddq supply  
On board DC to DC such as  
12V, 5V to 3.3V, 2.5V or 1.8V  
Hard Disk Drive  
Internal digital soft start; Vcc undervoltage lock out;  
Output undervoltage protection with digital filter and shut-  
down capability via the enable pin.  
n
TYPICAL APPLICATION  
L2 1uH  
Vin  
+12V  
C3  
C5  
1uF  
Cin  
47uF  
270uF,18mohm  
C6  
1uF  
D1  
R3  
10  
Vin  
+5V  
C4  
1uF  
6
5
1
R5  
C7  
0.1uF  
68k  
BST  
Vcc PVcc  
M1  
L1 1.5uH  
7
9
8
2
Hdrv  
SW  
EN  
2N3904  
OFF  
R8  
10k  
R6  
12.4k  
C9  
Vout  
10  
ON  
1uF  
Comp  
Fb  
R7  
+1.6V,10A  
C2  
Co  
C1  
47pF  
2.7nF  
10k  
3x (220uF,12mohm)  
M2  
4
Ldrv  
R4  
11k  
Gnd  
11  
PGnd  
3
R1 10k 1%  
R2  
10k 1%  
2.2nF  
C8  
R9  
1.2k  
Figure1 - Typical application of 2113A  
ORDERING INFORMATION  
Device  
Temperature  
0 to 70oC  
0 to 70o C  
0 to 70oC  
0 to 70o C  
Package  
Frequency  
300kHz  
300kHz  
600kHz  
600kHz  
Pb-Free  
Yes  
Yes  
Yes  
Yes  
NX2113CMTR  
NX2113CUTR  
NX2113ACMTR  
NX2113ACUTR  
MLPD-10L  
MSOP-10L  
MLPD-10L  
MSOP-10L  
Rev. 2.0  
11/18/05  
1
NX2113/2113A  
ABSOLUTE MAXIMUM RATINGS  
Vcc to GND & BST to SW voltage ................... 6.5V  
BST to GND Voltage ...................................... 35V  
Storage Temperature Range ............................. -65oC to 150oC  
Operating Junction Temperature Range ............. -40oC to 125oC  
CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to  
the device. This is a stress only rating and operation of the device at these or any other conditions above those  
indicated in the operational sections of this specification is not implied.  
PACKAGE INFORMATION  
10-LEAD PLASTIC MSOP  
10-LEAD PLASTIC MLPD  
qJA » 52oC/W  
qJA » 200oC/W  
1
BST  
1
10  
9
10  
BST  
HDrv  
SW  
Comp  
Fb  
SW  
HDrv 2  
2
3
9
8
Comp  
Fb  
PAD  
(Gnd)  
8
3
4
5
PGnd/Gnd  
LDrv  
PGnd  
7
EN  
4
5
7
6
LDrv  
PVcc  
EN  
6
Vcc  
PVcc  
Vcc  
ELECTRICAL SPECIFICATIONS  
Unless otherwise specified, these specifications apply over Vcc = 5V, and TA = 0 to 70oC. Typical values refer to TA  
= 25oC. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient  
PARAMETER  
Reference Voltage  
Ref Voltage  
SYM  
Test Condition  
Min  
TYP  
MAX Units  
VREF  
4.5V<Vcc<5.5V  
0.8  
0.4  
V
Ref Voltage line regulation  
Supply Voltage(Vcc)  
VCC Voltage Range  
VCC Supply Current (Static)  
VCC Supply Current  
(Dynamic)  
%
VCC  
5
2.1  
5
V
4.5  
5.5  
ICC (Static) Outputs not switching  
mA  
mA  
ICC  
(Dynamic)  
CLOAD=3300pF FS=300kHz  
Supply Voltage(VBST  
)
VBST Supply Current (Static)  
IBST (Static) Outputs not switching  
0.15  
5
mA  
mA  
VBST Supply Current  
(Dynamic)  
IBST  
CLOAD=3300pF FS=300kHz  
(Dynamic)  
Under Voltage Lockout  
VCC-Threshold  
VCC-Hysteresis  
SS  
VCC_UVLO VCC Rising  
VCC_Hyst VCC Falling  
4.1  
V
V
0.22  
Soft Start time  
Tss  
Fsw=300Khz, 2113  
Fsw=600Khz, 2113A  
3.4  
1.7  
mS  
Rev. 2.0  
11/18/05  
2
NX2113/2113A  
PARAMETER  
Oscillator (Rt)  
SYM  
FS  
Test Condition  
2113  
Min  
TYP  
MAX Units  
Frequency  
300  
600  
2.1  
93  
kHz  
kHz  
V
2113A  
Ramp-Amplitude Voltage  
Max Duty Cycle  
VRAMP  
%
Min Duty Cycle  
%
0
Error Amplifiers  
Transconductance  
2100  
10  
umho  
nA  
Input Bias Current  
Ib  
FB Under Voltage Protection  
FB Under voltage threshold  
EN  
0.4  
V
Enable Threshold Voltage  
Enable Hysterises  
Enable ramp up  
1.25  
0.2  
V
V
High Side Driver(CL=3300pF)  
Output Impedance , Sourcing  
Current  
Rsource(Hdrv)  
Rsink(Hdrv)  
I=200mA  
I=200mA  
1.1  
0.8  
ohm  
ohm  
Output Impedance , Sinking  
Current  
Rise Time  
THdrv(Rise)  
THdrv(Fall)  
VBST-VSW=4.5V  
VBST-VSW=4.5V  
50  
50  
30  
ns  
ns  
ns  
Fall Time  
Deadband Time  
Tdead(L to Ldrv going Low to Hdrv  
H)  
going High, 10%-10%  
Low Side Driver (CL=3300pF)  
Output Impedance, Sourcing  
Current  
Rsource(Ldrv)  
Rsink(Ldrv)  
I=200mA  
I=200mA  
1.1  
0.5  
ohm  
ohm  
Output Impedance, Sinking  
Current  
Rise Time  
TLdrv(Rise)  
TLdrv(Fall)  
10% to 90%  
90% to 10%  
50  
50  
30  
ns  
ns  
ns  
Fall Time  
Deadband Time  
Tdead(H to SW going Low to Ldrv  
L) going High, 10% to 10%  
Rev. 2.0  
11/18/05  
3
NX2113/2113A  
PIN DESCRIPTIONS  
PIN #  
PIN SYMBOL  
PIN DESCRIPTION  
This pin supplies voltage to the high side driver. A high frequency  
ceramic capacitor of 0.1 to 1 uF must be connected from this pin to SW pin.  
1
BST  
High side MOSFET gate driver.  
2
3
HDRV  
Power and analog ground pin. For MLPD package, analog ground and power ground  
are separated, additional pad pin(11) is available for analog ground.  
PGND/Gnd  
Low side MOSFET gate driver.  
4
5
LDRV  
PVcc  
Ldrv supply voltage. A 1uF high frequency cap must be connected from this pin to  
GND directly.  
Voltage supply for the internal circuit as well as the low side MOSFET gate driver.A  
1uF high frequency ceramic capacitor must be connected from this pin to GND pin.  
6
7
Vcc  
EN  
Pull up this pin to Vcc for normal operation. Pulling this pin down below 1.25V  
shuts down the controller and resets the soft start. This pin can also be used as  
a UVLO detector for the bus voltage via a resistor divider.  
This pin is the error amplifier inverting input. This pin is also connected to the output  
UVLO comparator. When this pin falls below 0.4V, both HDRV and LDRV outputs  
are latched off.  
8
9
FB  
This pin is the output of the error amplifier and together with FB pin is used to  
compensate the voltage control feedback loop.  
COMP  
SW  
This pin is connected to the source of the high side MOSFET and provides return  
path for the high side driver.  
10  
Rev. 2.0  
11/18/05  
4
NX2113/2113A  
BLOCK DIAGRAM  
1.25V  
0.8V  
Bias  
Generator  
VCC  
EN  
POR  
UVLO  
BST  
START  
DRVH  
1.25/1.15  
FB  
SW  
0.4  
PVCC  
START  
OSC  
Digital  
DRVL  
start Up  
S
R
Q
FB  
COMP  
START  
GND  
Rev. 2.0  
11/18/05  
5
NX2113/2113A  
Demo Board Schematic  
J
P
2
L 2  
1
2
BUS  
BUS1  
D
O
1
6
0
8
C
- 1  
0
2
C
4
1
2
7
u
R
O
1
P
0
C
7
C
O
8
P
J
P
3
VCC  
1
2
C
4
1
3
7
u
R
1
4
0
D 1  
D 1 N 5 8 1 9  
R
6
1
8
2
k
C
2
1
4
u
C
1
1
u
4
C
u
9
1
Q
1
IR  
F
R
3
7
0
6
4
C
2
1
5
u
R
1 2  
1
.
1
4
U 1  
F
k
R
0
1
1
B S  
T
C
2
0
u
. 1  
2
Hdrv  
Ldrv  
H d r v  
L 1  
J P  
5
9
C
O M P  
2 N 3 9 0 4  
10  
4
OUT1  
OUT2  
1
2
S
W
Q
3
T P 1  
R
1 3  
C
1
7
C
1
5
D
O
5
0
1
0
P
- 7  
8
1
H
C
L d r v  
o
p
e
n
2 . 7 n  
C
1
n
6
C
4
1
1
1 0 k  
R
1 4  
o
p
e
7
p
R
6
n
5
C
P
1
1 0 k  
o
p
e
1
R
0
2
O
8
3
F b  
P G N D  
0
C
1
8
C
2
1
C
2
2
R
2
1
k
5
4
D 2  
D 1 N 5 8 1 9  
( G  
N
D
D
)
P
A
Q
2
7
R
O
3
P
IR  
F
R
3
0
6
GND  
J 1  
C
1
9
R
7
1
1
.
2 k  
2 . 2 n  
C
2
. 1  
u
R
8
R
9
1
0
k
1
0
k
Figure 2 - Demoboard design on NX2113A  
Rev. 2.0  
11/18/05  
6
NX2113/2113A  
Bill of Materials  
Item  
Quantity  
Reference  
C1,R3,C8,R10,C23,D2  
Part  
Manufacture  
SANYO  
1
2
3
4
5
6
7
8
6
2
1
3
1
2
1
3
3
1
1
2
3
2
1
1
2
1
2
1
1
2
1
1
1
1
1
OPEN  
.1uF  
C2,C20  
C7  
16SP270M  
1uF  
C9,C14,C24  
C11  
C12,C13  
C15  
47pF  
47uF  
2.7nF  
OPEN  
R6,C16,C17  
C18,C21,C22  
9
220uF 2R5TPE220MC SANYO  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
C19  
C25  
D1  
2.2nF  
1uF  
D1N5819  
CON2  
JP2,JP3,JP5  
J1  
L1  
L2  
Q1,Q2  
Q3  
R1,R2  
R4  
R5  
SCOPE TP  
DO5010P-781HC  
DO1608C-102  
Tektronics  
Coilcraft  
Coilcraft  
International Rectifier  
IRFR3706  
2N3904  
0
10  
11k  
10k  
1.2k  
12.4k  
68k  
2k  
R8,R9,R13,R14  
R7  
R11  
R12  
R15  
U1  
NX2113  
NEXSEM INC.  
Rev. 2.0  
11/18/05  
7
NX2113/2113A  
DEMO BOARD WAVEFORM  
Figure 3: Output efficiency  
Figure 4: Voltage ripple @1.6 V output voltage.  
(Ch2-ripple, Ch3-Hdrv)  
Figure 5: Output voltage transient response  
for load curent 0A-9A  
Figure 6: Start up time(Ch1-input volatge,  
Ch2-output voltage)  
Figure 8: Startup operation waveform  
Figure 7: ENABLE function.(Ch1-enable, Ch2-Ldrv,  
Ch3-output voltage)  
Rev. 2.0  
11/18/05  
8
NX2113/2113A  
APPLICATION INFORMATION  
V -VOUT VOUT  
1
´
IN  
DIRIPPLE  
=
=
´
LOUT  
V
FS  
IN  
...(2)  
1
Symbol Used In Application Information:  
12V-1.6V 1.6v  
´
´
= 3A  
0.78uH  
12v 600kHz  
VIN  
- Input voltage  
- Output voltage  
- Output current  
VOUT  
IOUT  
Output Capacitor Selection  
∆VRIPPLE - Output voltage ripple  
- Working frequency  
Output capacitor is basically decided by the  
amount of the output voltage ripple allowed during steady  
state(DC) load condition as well as specification for the  
load transient. The optimum design may require a couple  
of iterations to satisfy both condition.  
FS  
∆IRIPPLE - Inductor current ripple  
Design Example  
The following is typical application for NX2113A,  
the schematic is figure 2.  
VIN = 12V  
Based on DC Load Condition  
The amount of voltage ripple during the DC load  
condition is determined by equation(3).  
DIRIPPLE  
VOUT=1.6V  
DVRIPPLE = ESR´ DIRIPPLE  
+
...(3)  
8´ F ´ COUT  
IOUT=10A  
S
∆VRIPPLE <=20mV  
Where ESR is the output capacitors' equivalent  
series resistance,COUT is the value of output capacitors.  
Typically when large value capacitors are selected  
such as Aluminum Electrolytic,POSCAP and OSCON  
types are used, the amount of the output voltage ripple  
is dominated by the first term in equation(3) and the  
second term can be neglected.  
∆VDROOP<=80mV @ 10A step  
FS=600kHz  
Output Inductor Selection  
The selection of inductor value is based on induc-  
tor ripple current, power rating, switching frequency and  
efficiency. Larger inductor value normally means smaller  
ripple current. However if the inductance is chosen too  
large, it brings slow response and lower efficiency. Usu-  
ally the ripple current ranges from 20% to 40% of the  
output current. This is a design freedom which can be  
decided by design engineer according to various appli-  
cation requirements. The inductor value can be calcu-  
lated by using the following equations:  
For this example, POSCAP are chosen as output  
capacitors, the ESR and inductor current typically de-  
termines the output voltage ripple.  
DVRIPPLE  
DIRIPPLE  
20mV  
3A  
ESRdesire  
=
=
= 6.7mW  
...(4)  
If low ESR is required, for most applications, mul-  
tiple capacitors in parallel are better than a big capaci-  
tor. For example, for 20mV output ripple, POSCAP  
2R5TPE220MC with 12mW are chosen.  
V -VOUT VOUT  
1
IN  
LOUT  
=
´
´
DIRIPPLE  
V
F
S
IN  
...(1)  
E S R E ´ DIR IPPLE  
N =  
IRIPPLE =k ´ IOUTPUT  
...(5)  
D VR IPPLE  
where k is between 0.2 to 0.4.  
Select k=0.3, then  
Number of Capacitor is calculated as  
12mW´ 3A  
N =  
12V-1.6V 1.6V  
1
LOUT  
=
´
´
20mV  
N =1.8  
0.3´ 10A 12V 600kHz  
LOUT =0.8uH  
The number of capacitor has to be round up to a  
integer. Choose N =2.  
Choose inductor from COILCRAFT DO5010P-  
781HC with L=0.78uH is a good choice.  
Current Ripple is recalculated as  
If ceramic capacitors are chosen as output ca-  
Rev. 2.0  
11/18/05  
9
NX2113/2113A  
pacitors, both terms in equation (3) need to be evaluated of output capacitor. For low frequency capacitor such  
to determine the overall ripple. Usually when this type of as electrolytic capacitor, the product of ESR and ca-  
capacitors are selected, the amount of capacitance per  
single unit is not sufficient to meet the transient specifi-  
cation, which results in parallel configuration of multiple  
capacitors .  
pacitance is high and L £ Lcrit is true. In that case, the  
transient spec is dependent on the ESR of capacitor.  
In most cases, the output capacitors are multiple  
capacitors in parallel. The number of capacitors can be  
calculated by the following  
For example, one 100uF, X5R ceramic capacitor  
with 2mW ESR is used. The amount of output ripple is  
ESRE ´ DIstep  
VOUT  
N =  
+
´ t 2  
...(9)  
3A  
DV  
2´ L´ CE ´ DV  
DVRIPPLE = 2mW´ 3A +  
tran  
tran  
8´ 600kHz´ 100uF  
where  
= 6mV + 6.2mV = 12.2mV  
Although this meets DC ripple spec, however it  
needs to be studied for transient requirement.  
0
if L £ Lcrit  
ì
ï
L´ DI  
t =  
í
ï
î
step  
...(10)  
- ESRE ´ CE  
if L ³ Lcrit  
VOUT  
Based On Transient Requirement  
For example, assume voltage droop during tran-  
sient is 100mV for 10A load step.  
Typically, the output voltage droop during transient  
is specified as:  
If the POSCAP 2R5TPE220MC(220uF, 12mW ) is  
used, the critical inductance is given as:  
DVDROOP <DVTRAN @ step load ∆ISTEP  
During the transient, the voltage droop during the  
transient is composed of two sections. One Section is  
dependent on the ESR of capacitor, the other section is  
a function of the inductor, output capacitance as well as  
input, output voltage. For example, for the overshoot,  
when load from high load to light load with a ∆ISTEP  
transient load, if assuming the bandwidth of system is  
high enough, the overshoot can be estimated as the fol-  
lowing equation.  
ESRE ´ CE ´ VOUT  
Lcrit  
=
=
DIstep  
12mW´ 220mF´ 1.6V  
= 0.42mH  
10A  
The selected inductor is 0.78uH which is bigger  
than critical inductance. In that case, the output voltage  
transient not only dependent on the ESR, but also ca-  
pacitance.  
number of capacitors is  
VOUT  
DVovershoot = ESR ´ DIstep  
+
´ t 2  
...(6)  
2´ L´ COUT  
where is the a function of capacitor, etc.  
L´ DIstep  
t =  
- ESRE ´ CE  
t
VOUT  
0.78mH´ 10A  
0
if L £ Lcrit  
ì
=
- 12mW´ 220mF = 2.24us  
ï
1.6V  
L´ DI  
t =  
í
ï
î
step  
...(7)  
...(8)  
- ESR ´ COUT  
if L ³ Lcrit  
VOUT  
ESRE ´ DIstep  
VOUT  
N =  
+
´ t 2  
where  
ESR ´ COUT ´ VOUT ESRE ´ CE ´ VOUT  
DV  
2´ L´ CE ´ DV  
tran  
tran  
12mW´ 10A  
Lcrit  
=
=
=
+
DIstep  
DIstep  
80mV  
1.6V  
´ (2.24us)2  
where ESRE and CE represents ESR and capaci-  
tance of each capacitor if multiple capacitors are used  
in parallel.  
2´ 1.5mH´ 220mF´ 80mV  
» 1.7  
The above equation shows that if the selected out-  
put inductor is smaller than the critical inductance, the  
voltage droop or overshoot is only dependent on the ESR  
The number of capacitors has to satisfy both ripple  
and transient requirement. Overall, we can choose N=3.  
Rev. 2.0  
11/18/05  
10  
NX2113/2113A  
It should be considered that the proposed equa-  
tion is based on ideal case, in reality, the droop or over-  
shoot is typically more than the calculation. The equa-  
tion gives a good start. For more margin, more capaci-  
tors have to be chosen after the test. Typically, for high  
frequency capacitor such as high quality POSCAP es-  
pecially ceramic capacitor, 20% to 100% (for ceramic)  
more capacitors have to be chosen since the ESR of  
capacitors is so low that the PCB parasitic can affect  
the results tremendously. More capacitors have to be  
selected to compensate these parasitic parameters.  
1
FZ1 =  
...(11)  
2´ p ´ R4 ´ C2  
1
FZ2  
=
...(12)  
...(13)  
...(14)  
2´ p ´ (R2 + R3 )´ C3  
1
F =  
P1  
2´ p ´ R3 ´ C3  
1
F
=
P2  
C1 ´ C2  
2´ p ´ R4 ´  
C1 + C2  
where FZ1,FZ2,FP1 and FP2 are poles and zeros in  
the compensator. Their locations are shown in figure 10.  
The transfer function of type III compensator for  
transconductance amplifier is given by:  
Compensator Design  
Due to the double pole generated by LC filter of the  
power stage, the power system has 180o phase shift ,  
and therefore, is unstable by itself. In order to achieve  
accurate output voltage and fast transient response,  
compensator is employed to provide highest possible  
bandwidth and enough phase margin. Ideally, the Bode  
plot of the closed loop system has crossover frequency  
between 1/10 and 1/5 of the switching frequency, phase  
margin greater than 50o and the gain crossing 0dB with -  
20dB/decade. Power stage output capacitors usually  
decide the compensator type. If electrolytic capacitors  
are chosen as output capacitors, type II compensator  
can be used to compensate the system, because the  
zero caused by output capacitor ESR is lower than cross-  
over frequency. Otherwise type III compensator should  
be chosen.  
Ve  
1- gm ´ Zf  
=
VOUT  
1+ gm ´ Zin + Zin /R1  
For the voltage amplifier, the transfer function of  
compensator is  
Ve  
- Zf  
=
VOUT  
Zin  
To achieve the same effect as voltage amplifier,  
the compensator of transconductance amplifier must  
satisfy this condition: R4>>2/gm. R1||R2||R3>>1/gm  
is desirable.  
Zf  
Vout  
Zin  
R3  
C1  
A. Type III compensator design  
C2  
For low ESR output capacitors, typically such as  
Sanyo oscap and poscap, the frequency of ESR zero  
caused by output capacitors is higher than the cross-  
over frequency. In this case, it is necessary to compen-  
sate the system with type III compensator. The follow-  
ing figures and equations show how to realize the type III  
compensator by transconductance amplifier.  
R4  
R2  
R1  
C3  
Fb  
Ve  
gm  
Vref  
Figure 9 - Type III compensator using  
transconductance amplifier  
Rev. 2.0  
11/18/05  
11  
NX2113/2113A  
smaller than 1/10~ 1/5 of the switching frequency. Set  
FO=45kHz.  
1
1
1
C3 =  
´ (  
-
)
power stage  
2´ p ´ R2  
F
F
p1  
z2  
LC  
F
1
1
1
=
´ (  
-
)
40dB/decade  
2´ p ´ 10kW 7kHz 60kHz  
=2nF  
VOSC 2´ p ´ F ´ L  
O
R4 =  
=
´
´ Cout  
loop gain  
V
C3  
in  
ESR  
F
2V 2´ p ´ 45kHz´ 0.78uH  
´
´ 660uF  
12V  
=11k W  
2.2nF  
20dB/decade  
Choose C3=2.2nF, R4=11kW.  
compensator  
5. Calculate C2 with zero Fz1 at 75% of the LC  
double pole by equation (11).  
1
C2  
=
2 ´ p ´ FZ1 ´ R4  
FZ1  
FO  
FP2  
FZ2  
FP1  
1
=
2 ´ p ´ 0.75 ´ 7kHz ´ 11kW  
= 2.75nF  
Figure 10 - Bode plot of Type III compensator  
Choose C2=2.7nF.  
6. Calculate C1 by equation (14) with pole Fp2 at  
half the swithing frequency.  
Design example for type III compensator are in  
order. Use the same power stage requirement as demo  
board. The crossover frequency has to be selected as  
FLC<FO<FESR, and FO<=1/10~1/5Fs.  
1
C1 =  
2 ´ p ´ R4 ´ FP2  
1
1.Calculate the location of LC double pole FLC  
=
2 ´ p ´ 11kW´ 300kHz  
= 48pF  
and ESR zero FESR  
.
1
F
=
=
LC  
Choose C1=47pF.  
2´ p ´  
L
OUT ´ COUT  
7. Calculate R3 by equation (13).  
1
1
2´ p ´ 0.78uH´ 660uF  
R3 =  
= 7kHz  
2´ p ´ F ´ C3  
P1  
1
=
1
2´ p ´ 60kHz ´ 2.2nF  
= 1.2kW  
FESR  
=
2 ´ p ´ ESR ´ COUT  
1
Choose R3=1.2kW.  
=
2 ´ p ´ 4mW´ 660uF  
= 60kHz  
2.Set R2 equal to10kW, then R1= 10kW.  
3. Set zero FZ2 = FLC and Fp1 =FESR  
4. Calculate R4 and C3 with the crossover frequency  
.
Rev. 2.0  
11/18/05  
12  
NX2113/2113A  
B. Type II compensator design  
noise. The following equations show the compensator  
pole zero location and constant gain.  
If the electrolytic capacitors are chosen as power  
stage output capacitors, usually the Type II compensa-  
tor can be used to compensate the system.  
R1  
Gain=gm ´  
´ R3  
... (15)  
... (16)  
... (17)  
R1+R2  
1
F =  
Vout  
z
2´ p ´ R3 ´ C1  
1
R2  
F »  
p
Fb  
2´ p ´ R3 ´ C2  
Ve  
gm  
For this type of compensator, FO has to satisfy  
FLC<FESR<<FO<=1/10~1/5Fs.  
R1  
R3  
Vref  
C2  
C1  
The following uses typical design in figure 18 as  
an example for type II compensator design, two 680uF  
with 36mW electrolytic capacitors are used.  
1.Calculate the location of LC double pole FLC  
and ESR zero FESR  
.
Figure 11 - Type II compensator with  
transconductance amplifier  
1
F
=
=
LC  
2´ p ´  
L
OUT ´ COUT  
1
2´ p ´ 4.7uH´ 1360uF  
power stage  
= 2.0kHz  
40dB/decade  
1
FESR  
=
2 ´ p ´ ESR ´ COUT  
loop gain  
1
=
2 ´ p ´ 18mW´ 1360uF  
= 6.5kHz  
20dB/decade  
2.Set R2 equal to10kW. Using equation 18.  
10kW´ 0.8V  
R1 =  
= 4.7kW  
compensator  
Gain  
2.5V-0.8V  
3. Set crossover frequency at 1/10~ 1/5 of the  
swithing frequency, here FO=30kHz.  
4.Calculate R3 value by the following equation.  
P
F
F
F
Z
LCFESR  
FO  
VOSC 2 ´ p ´ FO ´ L  
R1+R2  
R1  
1
R3 =  
=
´
´
´
V
RESR  
gm  
in  
Figure 12 - Bode plot of Type II compensator  
2V 2´ p ´ 30kHz´ 4.7uH  
1
´
´
12V  
18mW  
10kW+4.7kW  
2.5mA/V  
Type II compensator can be realized by simple  
RC circuit without feedback as shown in figure 11. R3  
and C1 introduce a zero to cancel the double pole  
effect. C2 introduces a pole to suppress the switching  
´
4.7kW  
=10.3kW  
Choose R3 =10kW.  
Rev. 2.0  
11/18/05  
13  
NX2113/2113A  
5. Calculate C1 by setting compensator zero FZ  
at 75% of the LC double pole.  
In general, the minimum output load impedance  
including the resistor divider should be less than 5kW to  
prevent overcharge the output voltage by leakage cur-  
rent (e.g. Error Amplifier feedback pin bias current). A  
minimum load for 5kW less (<1/16w for most of applica-  
tion) is recommended to put at the output. For example,  
in this application,  
1
C1=  
2´ p ´ R3 ´ Fz  
1
=
2 ´ p ´ 10kW´ 0.75 ´ 6.5kHz  
=10.7nF  
Vout=1.6V  
Choose C1=10nF.  
The power loss is 1/16W less  
F
6. Calculate C2 by setting compensator pole  
half the swithing frequency.  
at  
p
RLOAD = 1.6V ´ 1.6V /(1/16W) = 40W  
Select minimum load is 1kW should be good  
enough.  
1
C =  
2
p ´ R ´ Fs  
3
Input Capacitor Selection  
1
=
Input capacitors are usually a mix of high frequency  
ceramic capacitors and bulk capacitors. Ceramic ca-  
pacitors bypass the high frequency noise, and bulk ca-  
pacitors supply current to the MOSFETs. Usually 1uF  
ceramic capacitor is chosen to decouple the high fre-  
quency noise. The bulk input capacitors are decided by  
voltage rating and RMS current rating. The RMS current  
in the input capacitors can be calculated as:  
p ´ 1 0 k W ´ 3 0 0 k H z  
= 1 0 6 p F  
Choose C2=100pF.  
Output Voltage Calculation  
Output voltage is set by reference voltage and  
external voltage divider. The reference voltage is fixed  
at 0.8V. The divider consists of two ratioed resistors  
so that the output voltage applied at the Fb pin is 0.8V  
when the output voltage is at the desired value. The  
following equation and picture show the relationship  
between VOUT , VREF and voltage divider.  
IRMS = IOUT  
´
D ´ 1-D  
VOUT  
...(19)  
D =  
V
IN  
VIN = 12V, VOUT=1.6V, IOUT=10A, using equation  
(19), the result of input RMS current is 3.4A.  
For higher efficiency, low ESR capacitors are  
recommended. One Sanyo OSCON SP series  
16SP270M 16V 270uF with 4.4A is chosen as input  
bulk capacitor.  
R 2 ´ VREF  
R1=  
...(18)  
VOUT -VREF  
whereR 2 is part of the compensator, and the  
value of R1 value can be set by voltage divider.  
Choose R2=10kW, to set the output voltage at  
1.6V, the result of R1 is 10kW.  
Power MOSFETs Selection  
The NX2113 requires two N-Channel power  
MOSFETs. The selection of MOSFETs is based on  
maximum drain source voltage, gate source voltage,  
maximum current rating, MOSFET on resistance and  
power dissipation. The main consideration is the power  
loss contribution of MOSFETs to the overall converter  
efficiency. In this design example, two IRFR3706 are  
used. They have the following parameters: VDS=30V, ID  
=75A,RDSON =9mW,QGATE =23nC.  
Vout  
R2  
Fb  
R1  
Vref  
Voltage divider  
Figure 13 - Voltage divider load  
Rev. 2.0  
11/18/05  
14  
NX2113/2113A  
There are three factors causing the MOSFET power  
loss: conduction loss, switching loss and gate driver loss.  
Gate driver loss is the loss generated by discharg-  
ing the gate capacitor and is dissipated in driver circuits.  
It is proportional to frequency and is defined as:  
Vbus  
POR  
R1  
R2  
Digital  
start  
up  
OFF  
10k  
EN  
1.25/1.15  
ON  
Pgate = (QHGATE ´ VHGS + QLGATE ´ VLGS )´ FS  
...(20)  
where QHGATE is the high side MOSFETs gate  
charge,QLGATE is the low side MOSFETs gate charge,VHGS  
is the high side gate source voltage, and VLGS is  
the low side gate source voltage.  
Figure 14 - Enable and Shut down NX2113 by  
pulling down EN pin.  
According to equation (20), PGATE =0.14W. This  
power dissipation should not exceed maximum power  
dissipation of the driver device.  
The start up of NX2113/2113A can be programmed  
through resistor divider at Enable pin. For example, if  
the input bus voltage is 12V and we want NX2113 starts  
when Vbus is above 8V. We can select  
R2=1.24k  
Conduction loss is simply defined as:  
P
HCON =IOUT2 ´ D´ RDS(ON) ´ K  
LCON=IOUT2 ´ (1- D)´ RDS(ON) ´ K  
PTOTAL =P + P  
P
...(21)  
(8V - 1.25V)´ R2  
HCON  
LCON  
R1 =  
= 6.8kW  
1.25V  
where the RDS(ON) will increases as MOSFET junc-  
tion temperature increases, K is RDS(ON) temperature  
dependency. As a result, RDS(ON) should be selected for  
the worst case, in which K equals to 1.4 at 125oC ac-  
cording to IRFR3706 datasheet. Using equation (21),  
the result of PTOTAL is 0.54W. Conduction loss should  
not exceed package rating or overall system thermal  
budget.  
The NX2113 can be turned off by pulling down the  
ENable pin by extra signal MOSFET or NPN transistor  
such as 2N3904 as shown in the above Figure. When  
Enable pin is below 1.15V, the digital soft start is reset  
to zero. In addition, all the high side is off and output  
voltage is turned off.  
A resistor should be added as preload to prevent  
leakage current from FB pin charging the output capaci-  
tors.  
Switching loss is mainly caused by crossover con-  
duction at the switching transition. The total switching  
loss can be approximated.  
Feedback Under Voltage Shut Down  
NX2113 relies on the Feedback Under Voltage Lock  
Out (FB UVLO ) to provide short circuit protection. Ba-  
sically, NX2113 has a comparator compares the feed-  
back voltage with the FB UVLO threshold 0.4V.  
During the normal operation, if the output is short,  
the feedback voltage will be lower than 0.4V and com-  
parator will change the state.After certain internal delay,  
both high side and low side driver will be turned off. The  
output will be latched. The normal operation should be  
achieved by removing the short and recycle the VCC.  
During the start up, the output voltage is dis-  
1
PSW  
=
´ V ´ IOUT ´ TSW ´ F  
IN S  
...(22)  
2
where IOUT is output current, TSW is the sum of TR and TF  
which can be found in mosfet datasheet, and FS is switch-  
ing frequency. The result of PSW is 3W. Swithing loss  
PSW is frequency dependent.  
Soft Start, Enable and shut Down  
The NX2113 has a digital start up. It is based on  
digital counter with 1024 cycles. For NX2113 with 300kHz  
operation, the start up time is about 3.5ms. For NX2113A  
with 600kHz operation, the start up time is about half of  
NX2113, 1.75mS.  
charged to zero by the synchronous FET. FB voltage  
starts increase from zero when digital start block  
Rev. 2.0  
11/18/05  
15  
NX2113/2113A  
operates. Before half of the start up time, the Feedback  
The Feedback UVLO can provide certain short cir-  
Under Voltage Lock Out comparator is disabled. After cuit protection. However, since feedback does not have  
half of start up time, the Feedback UVLO comparator is accurate information of current, this protection only pro-  
enabled. The FB UVLO threshold is set to be half of vides certain level of over current protection. MOSFET  
voltage at the positive input of error amplifier. With this should design such that it can survive with high pulse  
set up, if the output is short before soft start, the current for a short period of time.  
Feedback UVLO comparator can catch it and turn off  
The value of the capacitor on enable pin to ground  
the driver. The short circuit operation waveform during and the resistor value of voltage divider on enable pin  
normal operation and during the soft start are shown as should be big enough to keep enable pin high during  
follows.  
short. Otherwise, once output shorts, the input bus volt-  
age drops, the chip is disabled before Feedback UVLO  
takes effect, and the system goes into hiccup status.  
This phenomena is easy to be found during system  
startup, if related resistor and capacitor value is not big  
enough.  
CH3-FB voltage  
0.5V/DIV  
CH1-SW voltage  
10V/DIV  
CH4-load current  
10A/DIV  
CH2-Output voltage  
1V/DIV  
Figure 15 - Operation waveforms during short con-  
CH4-load current  
10A/DIV  
dition.  
Figure 17 -Hiccup with start up at short.  
CH2-output voltage  
1V/DIV  
Layout Considerations  
The layout is very important when designing high  
frequency switching converters. Layout will affect noise  
pickup and can cause a good design to perform with  
less than expected results.  
CH4-load current  
10A/DIV  
Start to place the power components, make all the  
connection in the top layer with wide, copper filled ar-  
eas. The inductor, output capacitor and the MOSFET  
should be close to each other as possible. This helps to  
reduce the EMI radiated by the power traces due to the  
high switching currents through them. Place input ca-  
pacitor directly to the drain of the high-side MOSFET, to  
Figure 16 - Feedback UVLO with start up at  
short.  
Rev. 2.0  
11/18/05  
16  
NX2113/2113A  
reduce the ESR replace the single input capacitor with  
two parallel units. The feedback part of the system should  
be kept away from the inductor and other noise sources,  
and be placed close to the IC. In multilayer PCB use  
one layer as power ground plane and have a control cir-  
cuit ground (analog ground), to which all signals are ref-  
erenced.  
The goal is to localize the high current path to a  
separate loop that does not interfere with the more sen-  
sitive analog control function. These two grounds must  
be connected together on the PC board layout at a single  
point.  
Rev. 2.0  
11/18/05  
17  
NX2113/2113A  
TYPICAL APPLICATION  
Dual power supply (+5V BIAS,+12V BUS)  
L2 1uH  
Vin  
+12V  
C5  
1uF  
Cin  
C4  
47uF  
39uF,31mohm  
C6  
D1  
R5  
Vin  
1uF  
10  
+5V  
C5  
1uF  
6
1
5
R5  
1k  
C7  
0.1uF  
BST  
Vcc PVcc  
M1  
L1 4.7uH  
7
9
8
2
Hdrv  
EN  
R6  
1k  
Vout  
10  
4
Comp  
SW  
+2.5V,4A  
C2  
Co  
C1  
100pF  
10nF  
2 x (680uF,36mohm)  
M2  
Ldrv  
Fb  
R4  
10k  
PGnd/Gnd  
3
R1 10k 1%  
R2  
4.7k 1%  
Figure 18 -Application of NX2113 for 5V bias and 12V input bus  
Single power supply (+11V to +24V BUS)  
L2 1uH  
Vin  
+11~25V  
R5  
C4  
C5  
1uF  
Cin  
3k  
R8  
76.8k  
47uF  
2 x (47uF,60mohm)  
2N3904  
C6  
1uF  
R5  
10  
R6  
12.7k  
D1  
R9  
10k  
TL431  
C8  
1uF  
R7  
10k  
5
1
6
C7  
0.1uF  
BST  
Vcc  
PVcc  
M1  
L1 4.7uH  
7
9
8
2
Hdrv  
EN  
Vout  
10  
4
Comp  
Fb  
SW  
+1.6V,5A  
C2  
Co  
10nF  
2 x (680uF,36mohm)  
M2  
C1  
100pF  
Ldrv  
R4  
10k  
PGnd Gnd  
3
11  
R1  
10k 1%  
R2  
4.7k 1%  
Figure 19 -Application of NX2113 for high input bus application  
Rev. 2.0  
11/18/05  
18  
NX2113/2113A  
TYPICALAPPLICATION  
Single Supply 5V Input  
L2 1uH  
Vin  
+5V  
C4  
10uF  
X7R  
R5  
10  
D1  
C6  
1uF  
C5  
1uF  
Cin  
3 x 22uF  
X7R  
C8  
1uF  
6
5
1
C7  
0.1uF  
BST  
Vcc  
PVcc  
M1  
L1 3.3uH  
7
2
Hdrv  
SW  
EN  
Vout  
9
10  
Comp  
+1.2V,4A  
C1  
4.7pF  
R4  
120k  
Co  
10 x 22uF  
8
M2  
4
X7R  
Ldrv  
Fb  
C2  
330pF  
PGnd Gnd  
3
11  
R1  
10k 1%  
C3  
R2  
20k 1%  
R3  
787  
820pF  
Figure 20 - Application of NX2113 A for 5V input and 1.6V output with ceramic output capacitors  
Rev. 2.0  
11/18/05  
19  
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