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NX2116ACMTR

型号：

NX2116ACMTR

描述：

具有电流限制，电源正常及过电压同步PWM控制器[ SYNCHRONOUS PWM CONTROLLER WITH CURRENT LIMIT, POWER GOOD & OVER VOLTAGE ]

品牌：

MICROSEMI[ Microsemi ]

页数：

14 页

PDF大小：

408 K

下载PDF手册
NX2116/2116A/2116B/2117/2117A  
SYNCHRONOUS PWM CONTROLLER WITH  
CURRENT LIMIT, POWER GOOD & OVER VOLTAGE  
PRELIMINARY DATA SHEET  
Pb Free Product  
FEATURES  
DESCRIPTION  
n
n
Bus voltage operation from 2V to 25V  
Power Good indicator available in NX2116  
The NX2116/2117 family of products are synchronous  
Buck controller IC designed for step down DC to DC  
converter applications. They are optimized to convert  
bus voltages from 2V to 25V to as low as 0.8V output  
voltage. The NX2116 and 2117 offer an Enable pin that  
can be used to program the converter's start up voltage  
using an external divider from bus voltage. These prod-  
ucts operate at fixed internal frequency of 300kHz, ex-  
cept that NX2116A operates at 600kHz and 2116B at  
1MHz frequency. These products employ loss-less cur-  
rent limiting protection by sensing the Rdson of syn-  
chronous MOSFET followed by latch out feature. Feed-  
back under voltage triggers Hiccup.  
n Fixed 300kHz, 600kHz and 1MHz for NX2116 and  
300kHz, 600kHz for NX2117 family.  
n Internal Digital Soft Start Function  
n Less than 50 nS adaptive deadband  
n Enable pin to program BUS UVLO for NX2116/2117  
n
n
Programmable current limit triggers latch out by  
sensing Rdson of  
Synchronous MOSFET  
No negative spike at Vout during startup and  
shutdown  
APPLICATIONS  
n
n
n
Graphic Card on board converters  
Other features are; 5V gate drive, Power good indica-  
tor, Adaptive deadband control, Internal digital soft start;  
Vcc undervoltage lock out and shutdown capability via  
the enable pin or comp pin.  
Memory Vddq Supply  
On board DC to DC such as 2V to 3.3V, 2.5V or  
1.8V  
n
ADSL Modem  
TYPICAL APPLICATION  
L2 1uH  
Vin1  
+12V  
C5  
C3  
Cin  
1uF  
39uF  
270uF,18mohm  
D1  
R3  
10  
Vin2  
+5V  
MBR0530T1  
C4  
1uF  
4
1
R5  
68k  
C7  
BST  
Hdrv  
Vcc  
0.1uF  
M1  
6
8
2
EN  
2N3904  
OFF  
R8  
10k  
R6  
12.4k  
L1 1uH  
Vout  
10  
9
ON  
SW  
OCP  
Comp  
R7  
+1.8V,9A  
C2  
1.5nF  
Co  
C1  
33pF  
10k  
2x (220uF,12mohm)  
R11 3.7k  
7
M2  
3
5
Ldrv  
Fb  
R4  
17.4k  
11  
+5V  
Pgood  
Gnd  
R10 1k  
R1 20k  
R2  
16k  
R9  
2.61k  
C8  
1nF  
Figure 1 - Typical applicationOof 2R11D6ERING INFORMATION  
Device  
Temperature  
0 to 70oC  
0 to 70o C  
0 to 70o C  
0 to 70o C  
0 to 70o C  
Package  
MLPD-10L  
MLPD-10L  
MLPD-10L  
MSOP-10L  
MSOP-10L  
Frequency  
300kHz  
600kHz  
1MHz  
300kHz  
600kHz  
Pb-Free  
Yes  
NX2116CMTR  
NX2116ACMTR  
NX2116BCMTR  
NX2117CUTR  
NX2117ACUTR  
Yes  
Yes  
Yes  
Yes  
Rev. 3.0  
03/14/06  
1
NX2116/2116A/2116B/2117/2117A  
ABSOLUTE MAXIMUM RATINGS  
VCC to GND & BST to SW voltage .................... -0.3V to 6.5V  
BST to GND Voltage ........................................ -0.3V to 35V  
SW to GND ...................................................... -2V to 35V  
All other pins .................................................... -0.3V to VCC+0.3V or 6.5V  
Storage Temperature Range ............................... -65oC to 150oC  
Operating Junction Temperature Range ............... -40oC to 125oC  
ESD Susceptibility ........................................... 2kV  
CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to  
the device. This is a stress only rating and operation of the device at these or any other conditions above those  
indicated in the operational sections of this specification is not implied.  
PACKAGE INFORMATION  
NX2116/2116A/2116B  
NX2117/2117A  
10-LEAD PLASTIC MLPD  
10-LEAD PLASTIC MSOP  
qJA » 200oC/W  
qJA » 52oC/W  
BST  
BST  
1
2
3
1
10  
9
10  
9
SW  
SW  
OCP  
HDrv 2  
OCP  
COMP  
HDrv  
LDrv  
Gnd  
(PAD)  
GND  
3
8
COMP  
8
7 FB  
4
5
LDrv  
VCC  
FB  
EN  
VCC  
4
5
7
6
EN  
6
PGOOD  
ELECTRICAL SPECIFICATIONS  
Unless otherwise specified, these specifications apply over Vcc = 5V, and TA= 0 to 70oC. Typical values refer to TA  
= 25oC. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient  
temperature.  
PARAMETER  
Reference Voltage  
Ref Voltage  
SYM  
Test Condition  
Min  
TYP  
MAX Units  
VREF  
0.8  
0.2  
V
Ref Voltage line regulation  
Supply Voltage(Vcc)  
VCC Voltage Range  
VCC Supply Current (Static)  
VCC Supply Current  
(Dynamic)  
%
VCC  
5
3
V
4.5  
5.5  
ICC (Static) Outputs not switching  
ICC CLOAD=3300pF  
(Dynamic) FS=300kHz  
mA  
mA  
TBD  
Supply Voltage(VBST  
)
VBST Supply Current (Static)  
IBST (Static) Outputs not switching  
TBD  
TBD  
mA  
mA  
VBST Supply Current  
(Dynamic)  
IBST  
CLOAD=3300pF  
(Dynamic) FS=300kHz  
Rev. 3.0  
03/14/06  
2
NX2116/2116A/2116B/2117/2117A  
PARAMETER  
Under Voltage Lockout  
VCC-Threshold  
SYM  
Test Condition  
Min  
TYP  
MAX Units  
VCC_UVLO VCC Rising  
VCC_Hyst VCC Falling  
4
V
V
3.8  
4.2  
VCC-Hysteresis  
0.2  
Oscillator  
Frequency  
FS  
2116, 2117  
2116A,2117A  
2116B  
300  
600  
1000  
1.5  
kHz  
kHz  
kHz  
V
Ramp-Amplitude Voltage  
Max Duty Cycle  
Min Duty Cycle  
VRAMP  
95  
%
%
0
Error Amplifiers  
Transconductance  
Input Bias Current  
EN & SS  
2000  
10  
umho  
nA  
Ib  
Soft Start time  
Tss  
NX2116,NX2117  
NX2116A, NX2117A  
NX2116B  
6.8  
mS  
Enable HI Threshold  
Enable Hysterises  
1.25  
150  
V
mV  
High Side Driver  
(CL=3300pF)  
Output Impedance , Sourcing Rsource(Hdrv)  
Current  
I=200mA  
I=200mA  
0.9  
ohm  
ohm  
Output Impedance , Sinking  
Current  
Rsink(Hdrv)  
0.65  
Rise Time  
THdrv(Rise)  
THdrv(Fall)  
VBST-VSW=4.5V  
VBST-VSW=4.5V  
50  
50  
30  
ns  
ns  
ns  
Fall Time  
Deadband Time  
Tdead(L to Ldrv going Low to Hdrv going  
H)  
High, 10%-10%  
Low Side Driver  
(CL=3300pF)  
Output Impedance, Sourcing Rsource(Ldrv)  
Current  
I=200mA  
I=200mA  
0.9  
0.5  
ohm  
ohm  
Output Impedance, Sinking  
Current  
Rsink(Ldrv)  
Rise Time  
TLdrv(Rise)  
TLdrv(Fall)  
10% to 90%  
90% to 10%  
50  
50  
30  
ns  
ns  
ns  
Fall Time  
Deadband Time  
Tdead(H to SW going Low to Ldrv going  
L)  
High, 10% to 10%  
OCP Adjust  
OCP current  
40  
uA  
Power Good(Pgood)  
Threshold Voltage as % of  
Vref  
Hysteresis  
FB ramping up  
90  
5
%
%
Rev. 3.0  
03/14/06  
3
NX2116/2116A/2116B/2117/2117A  
PIN DESCRIPTIONS  
PIN SYMBOL  
PIN DESCRIPTION  
Power supply voltage. A high freq 1uF ceramic capacitor is placed as close as possible to  
and connected to this pin and ground pin. The maximum rating of this pin is 5V.  
VCC  
This pin supplies voltage to high side FET driver. A high freq 0.1uF ceramic capacitor is  
placed as close as possible to and connected to these pins and respected SW pins.  
BST  
Ground pin.  
GND  
This pin is the error amplifier inverting input. It is connected via resistor divider to the  
output of the switching regulator to set the output DC voltage. When FB pin voltage is  
lower than 0.6V, hiccup circuit starts to recycle the soft start circuit after 2048 switching  
cycles.  
FB  
This pin is connected to the drain of the external low side MOSFET via resistor and is the  
input of the over current protection(OCP) comparator. An internal current source 40uA is  
flown to the external resistor which sets the OCP voltage across the Rdson of the low side  
MOSFET. Current limit point is this voltage divided by the Rds-on. Once this threshold is  
reached the Hdrv and Ldrv pins are latched out.  
OCP  
This pin is connected to source of high side FET and provides return path for the high side  
driver. It is also used to hold the low side driver low until this pin is brought low by the  
action of high side turning off. LDRV can only go high if SW is below 1V threshold .  
SW  
High side gate driver output.  
Low side gate driver output.  
HDRV  
LDRV  
An open drain output that requires a pull up resistor to Vcc or a voltage lower than Vcc.  
When FB pin reaches 90% of the reference voltage PGOOD transitions from LO to HI  
state.  
PGOOD  
A resistor divider is connected from the respective switcher BUS voltages to these pins  
that holds off the controller's soft start until this threshold is reached.An external low cost  
Transistor can be connected to this pin for external enable control.  
EN  
This pin is the output of error amplifier and is used to compensate the voltage control  
feedback loop. This pin can also be used to perform a shutdown if pulled lower than 0.3V.  
COMP  
Rev. 3.0  
03/14/06  
4
NX2116/2116A/2116B/2117/2117A  
BLOCK DIAGRAM  
VCC  
FB  
Hiccup Logic  
0.6V  
1.25V  
0.8V  
OC  
Bias  
Generator  
BST  
UVLO  
POR  
START  
HDRV  
EN  
1.25/1.15  
SW  
OC  
Control  
Logic  
START  
0.8V  
PWM  
VCC  
OSC  
ramp  
Digital  
start Up  
S
LDRV  
Q
R
OC  
FB  
0.6V  
CLAMP  
40uA  
1.3V  
CLAMP  
COMP  
OCP  
Latch Out  
START  
OCP  
comparator  
PGOOD  
GND  
FB  
0.9Vref  
/0.85Vref  
Figure 2 - Simplified block diagram of the NX2116  
Rev. 3.0  
03/14/06  
5
NX2116/2116A/2116B/2117/2117A  
APPLICATION INFORMATION  
V -VOUT VOUT  
1
IN  
DIRIPPLE  
=
=
´
´
LOUT  
V
F
S
Symbol Used In Application Information:  
IN  
...(2)  
VIN  
- Input voltage  
- Output voltage  
- Output current  
12V-1.8V 1.8v  
1
´
´
= 2.55A  
1uH  
12V 600kHz  
VOUT  
IOUT  
∆VRIPPLE - Output voltage ripple  
- Working frequency  
Output Capacitor Selection  
FS  
Output capacitor is basically decided by the  
amount of the output voltage ripple allowed during steady  
state(DC) load condition as well as specification for the  
load transient. The optimum design may require a couple  
of iterations to satisfy both condition.  
∆IRIPPLE - Inductor current ripple  
Design Example  
The following is typical application for NX2116A,  
the schematic is figure 1.  
VIN = 12V  
Based on DC Load Condition  
The amount of voltage ripple during the DC load  
condition is determined by equation(3).  
VOUT=1.8V  
DIRIPPLE  
FS=600kHz  
DVRIPPLE = ESR´ DIRIPPLE  
+
...(3)  
8´ F ´ COUT  
IOUT=9A  
S
∆VRIPPLE <=20mV  
Where ESR is the output capacitors' equivalent  
series resistance,COUT is the value of output capacitors.  
Typically when large value capacitors are selected  
such as Aluminum Electrolytic,POSCAP and OSCON  
types are used, the amount of the output voltage ripple  
is dominated by the first term in equation(3) and the  
second term can be neglected.  
∆VDROOP<=100mV @ 9A step  
Output Inductor Selection  
The selection of inductor value is based on induc-  
tor ripple current, power rating, working frequency and  
efficiency. Larger inductor value normally means smaller  
ripple current. However if the inductance is chosen too  
large, it brings slow response and lower efficiency. Usu-  
ally the ripple current ranges from 20% to 40% of the  
output current. This is a design freedom which can be  
decided by design engineer according to various appli-  
cation requirements. The inductor value can be calcu-  
lated by using the following equations:  
For this example, POSCAP are chosen as output  
capacitors, the ESR and inductor current typically de-  
termines the output voltage ripple.  
DVRIPPLE  
DIRIPPLE  
20mV  
2.55A  
ESRdesire  
=
=
= 7.8mW  
...(4)  
If low ESR is required, for most applications, mul-  
tiple capacitors in parallel are better than a big capaci-  
tor. For example, for 20mV output ripple, POSCAP  
2R5TPE220MC with 12mW are chosen.  
V -VOUT VOUT  
1
IN  
LOUT  
=
´
´
DIRIPPLE  
V
F
S
IN  
...(1)  
IRIPPLE =k ´ IOUTPUT  
E S R E ´ DIR IPPLE  
N =  
where k is between 0.2 to 0.4.  
Select k=0.3, then  
...(5)  
D VR IPPLE  
Number of Capacitor is calculated as  
12V-1.8V 1.8V  
1
LOUT  
=
´
´
12mW´ 2.56A  
N =  
0.3´ 9A 12V 600kHz  
20mV  
LOUT =0.94uH  
N =1.5  
Choose inductor from COILCRAFT DO3316P-  
102HC with L=1uH is a good choice.  
Current Ripple is recalculated as  
The number of capacitor has to be round up to a  
integer. Choose N =2.  
If ceramic capacitors are chosen as output ca  
Rev. 3.0  
03/14/06  
6
NX2116/2116A/2116B/2117/2117A  
pacitors, both terms in equation (3) need to be evalu- of output capacitor. For low frequency capacitor such  
ated to determine the overall ripple. Usually when this as electrolytic capacitor, the product of ESR and ca-  
type of capacitors are selected, the amount of capaci-  
tance per single unit is not sufficient to meet the tran-  
sient specification, which results in parallel configura-  
tion of multiple capacitors .  
pacitance is high and L £ Lcrit is true. In that case, the  
transient spec is dependent on the ESR of capacitor.  
In most cases, the output capacitors are multiple  
capacitors in parallel. The number of capacitors can be  
calculated by the following  
For example, one 100uF, X5R ceramic capacitor  
with 2mW ESR is used. The amount of output ripple is  
ESRE ´ DIstep  
VOUT  
N =  
+
´ t 2  
...(9)  
2.56A  
DV  
2´ L´ CE ´ DV  
tran  
tran  
DV  
= 2mW´ 2.55A +  
=10.4mV  
RIPPLE  
8´ 600kHz´ 100uF  
where  
0
if L £ Lcrit  
ì
Although this meets DC ripple spec, however it  
needs to be studied for transient requirement.  
Based On Transient Requirement  
Typically, the output voltage droop during transient  
is specified as:  
ï
L´ DI  
t =  
í
ï
î
step  
...(10)  
- ESRE ´ CE  
if L ³ Lcrit  
VOUT  
For example, assume voltage droop during tran-  
sient is 100mV for 9A load step.  
DVDROOP <DVTRAN @ step load ∆ISTEP  
If the POSCAP 2R5TPE220MC(220uF, 12mW ) is  
used, the critical inductance is given as  
During the transient, the voltage droop during the  
transient is composed of two sections. One Section is  
dependent on the ESR of capacitor, the other section is  
a function of the inductor, output capacitance as well as  
input, output voltage. For example, for the overshoot,  
when load from high load to light load with a ∆ISTEP  
transient load, if assuming the bandwidth of system is  
high enough, the overshoot can be estimated as the fol-  
lowing equation.  
ESRE ´ CE ´ VOUT  
Lcrit  
=
=
DIstep  
12mW´ 220mF´ 1.8V  
= 0.56mH  
9A  
The selected inductor is 1uH which is bigger than  
critical inductance. In that case, the output voltage tran-  
sient not only dependent on the ESR, but also capaci-  
tance.  
VOUT  
´ t 2  
number of capacitors is  
DVovershoot = ESR ´ DIstep  
+
...(6)  
2´ L´ COUT  
where is the a function of capacitor, etc.  
L ´ DIstep  
t
t =  
- ESRE ´ CE  
VOUT  
0
if L £ Lcrit  
ì
ï
1mH ´ 9A  
=
- 12mW´ 220mF = 2.36us  
t = L´ DI  
í
1.8V  
step  
...(7)  
...(8)  
- ESR ´ COUT  
if L ³ Lcrit  
ï
VOUT  
î
ESRE ´ DIstep  
VOUT  
where  
ESR ´ COUT ´ VOUT ESRE ´ CE ´ VOUT  
N =  
+
´ t 2  
DV  
2´ L´ CE ´ DV  
tran  
tran  
Lcrit  
=
=
12mW´ 9A  
DIstep  
DIstep  
=
+
100mV  
where ESRE and CE represents ESR and capaci-  
tance of each capacitor if multiple capacitors are used  
in parallel.  
1.8V  
´ (2.36us)2  
2´ 1mH´ 220mF´ 100mV  
=1.3  
The above equation shows that if the selected out-  
put inductor is smaller than the critical inductance, the  
voltage droop or overshoot is only dependent on the ESR  
The number of capacitors has to satisfied both ripple  
and transient requirement. Overall, we can choose N=2.  
Rev. 3.0  
03/14/06  
7
NX2116/2116A/2116B/2117/2117A  
It should be considered that the proposed equa-  
1
tion is based on ideal case, in reality, the droop or over-  
shoot is typically more than the calculation. The equa-  
tion gives a good start. For more margin, more capaci-  
tors have to be chosen after the test. Typically, for high  
frequency capacitor such as high quality POSCAP es-  
pecially ceramic capacitor, 20% to 100% (for ceramic)  
more capacitors have to be chosen since the ESR of  
capacitors is so low that the PCB parasitic can affect  
the results tremendously. More capacitors have to be  
selected to compensate these parasitic parameters.  
FZ1  
FZ2  
=
=
=
=
...(11)  
...(12)  
...(13)  
...(14)  
2´ p ´ R4 ´ C2  
1
2´ p ´ (R2 + R3 )´ C3  
1
F
P1  
2´ p ´ R3 ´ C3  
1
F
P2  
C1 ´ C2  
2´ p ´ R4 ´  
C1 + C2  
where FZ1,FZ2,FP1 and FP2 are poles and zeros in  
the compensator. Their locations are shown in figure 4.  
The transfer function of type III compensator for  
transconductance amplifier is given by:  
Compensator Design  
Due to the double pole generated by LC filter of the  
power stage, the power system has 180o phase shift ,  
and therefore, is unstable by itself. In order to achieve  
accurate output voltage and fast transient  
response,compensator is employed to provide highest  
possible bandwidth and enough phase margin.Ideally,the  
Bode plot of the closed loop system has crossover fre-  
quency between1/10 and 1/5 of the switching frequency,  
phase margin greater than 50o and the gain crossing  
0dB with -20dB/decade. Power stage output capacitors  
usually decide the compensator type. If electrolytic  
capacitors are chosen as output capacitors, type II com-  
pensator can be used to compensate the system, be-  
cause the zero caused by output capacitor ESR is lower  
than crossover frequency. Otherwise type III compensa-  
tor should be chosen.  
Ve  
1- gm ´ Zf  
=
VOUT  
1+ gm ´ Zin + Zin /R1  
For the voltage amplifier, the transfer function of  
compensator is  
Ve  
- Zf  
=
VOUT  
Zin  
To achieve the same effect as voltage amplifier,  
the compensator of transconductance amplifier must  
satisfy this condition: R4>>2/gm. And it would be desir-  
able if R1||R2||R3>>1/gm can be met at the same time.  
Zf  
Vout  
Zin  
R3  
C1  
A. Type III compensator design  
C2  
R4  
R2  
R1  
For low ESR output capacitors, typically such as  
Sanyo oscap and poscap, the frequency of ESR zero  
caused by output capacitors is higher than the cross-  
over frequency. In this case, it is necessary to compen-  
sate the system with type III compensator. The follow-  
ing figures and equations show how to realize the type III  
compensator by transconductance amplifier.  
C3  
Fb  
Ve  
gm  
Vref  
Figure 3 - Type III compensator using  
transconductance amplifier  
Rev. 3.0  
03/14/06  
8
NX2116/2116A/2116B/2117/2117A  
Case 1: FLC<FO<FESR  
Choose R1=16kW.  
3. Set zero FZ2 = FLC and Fp1 =FESR  
.
4. Calculate R4 and C3 with the crossover  
frequency at 1/10~ 1/5 of the switching frequency. Set  
FO=50kHz.  
power stage  
LC  
F
40dB/decade  
1
1
1
C3=  
´ (  
-
)
2´ p´ R2  
F
F
p1  
z2  
1
1
1
=
´ (  
-
)
2´ p ´ 20kW 7.6kHz 60.3kHz  
loop gain  
=916pF  
ESR  
F
VOSC 2´ p ´ FO ´ L  
R4 =  
=
´
´ Cout  
20dB/decade  
V
C3  
1.5V 2´ p ´ 50kHz ´ 1uH  
in  
´
´ 440uF  
compensator  
12V  
=17.2kW  
1nF  
Choose C3=1nF, R4=17.4kW.  
5. Calculate C2 with zero Fz1 at 75% of the LC  
double pole by equation (11).  
FZ1  
FO  
FP2  
FZ2  
FP1  
1
C2 =  
2´ p ´ FZ1 ´ R4  
Figure 4 - Bode plot of Type III compensator  
1
=
2´ p ´ 0.75´ 7.6kHz ´ 17.4kW  
= 1.6nF  
Design example for type III compensator are in  
order. The crossover frequency has to be selected as  
FLC<FO<FESR, and FO<=1/10~1/5Fs.  
Choose C2=1.5nF.  
6. Calculate C1 by equation (14) with pole Fp2 at  
half the switching frequency.  
1.Calculate the location of LC double pole FLC  
and ESR zero FESR  
.
1
C1 =  
1
FLC  
=
=
2´ p ´ R4 ´ F  
P2  
2 ´ p ´ LOUT ´ COUT  
1
1
=
2´ p ´ 17.4kW´ 300kHz  
= 30pF  
2 ´ p ´ 1uH ´ 440uF  
= 7.6kHz  
Choose C1=33pF  
7. Calculate R3 by equation (13).  
1
FESR  
=
2 ´ p ´ ESR ´ COUT  
1
1
R3 =  
2´ p ´ F ´ C3  
=
P1  
2 ´ p ´ 6mW´ 440uF  
1
= 60.3kHz  
=
2´ p ´ 60.3kHz ´ 1nF  
= 2.64kW  
2. Set R2 equal to 20kW.  
R2 ´ VREF  
20kW´ 0.8V  
Choose R3=2.61kW.  
R1=  
=
= 16kW  
VOUT -VREF  
1.8V-0.8V  
Rev. 3.0  
03/14/06  
9
NX2116/2116A/2116B/2117/2117A  
Case 2: FLC<FESR<FO  
2. Set R2 equal to 10kW.  
R2 ´ VREF  
10kW´ 0.8V  
R1=  
=
= 8kW  
VOUT -VREF  
1.8V-0.8V  
Choose R1=8kW.  
power stage  
3. Set zero FZ2 = FLC and Fp1 =FESR  
4. Calculate C3 .  
.
LC  
F
40dB/decade  
1
1
1
C3 =  
´ (  
-
)
2´ p ´ R2  
F
F
p1  
ESR  
F
z2  
1
1
1
=
´ (  
-
)
loop gain  
2´ p ´ 10kW 2.9kHz 8.2kHz  
=3.5nF  
Choose C3=3.3nF.  
5. Calculate R3 .  
20dB/decade  
compensator  
1
R3 =  
2´ p ´ F ´ C3  
P1  
1
=
2´ p ´ 8.2kHz´ 3.3nF  
= 5.9kW  
FZ1  
FO  
FP2  
FZ2  
F
P1  
Choose R3 =5.9kW.  
6. Calculate R4 with FO=60kHz.  
VOSC 2´ p ´ F ´ L R2 ´ R3  
Figure 5 - Bode plot of Type III compensator  
(FLC<FESR<FO)  
O
R4 =  
´
´
V
ESR  
R2 +R3  
in  
1.5V 2´ p ´ 60kHz´ 1uH 10kW´ 5.9kW  
=
´
´
If electrolytic capacitors are used as output  
capacitors, typical design example of type III  
compensator in which the crossover frequency is  
selected as FLC<FESR<FO and FO<=1/10~1/5Fs is shown  
as the following steps. Here two SANYO MV-WG1500  
with 13 mW is chosen as output capacitor.  
12V  
=26.9kW  
Choose R4=26.7kW.  
6.5mW  
10kW+ 5.9kW  
5. Calculate C2 with zero Fz1 at 75% of the LC  
double pole by equation (11).  
1
C2 =  
1. Calculate the location of LC double pole FLC  
2´ p ´ FZ1 ´ R4  
and ESR zero FESR  
.
1
=
2´ p ´ 0.75´ 2.9kHz´ 26.7kW  
= 2nF  
1
F
=
=
LC  
2´ p ´ LOUT ´ COUT  
Choose C2=2.2nF.  
1
6. Calculate C1 by equation (14) with pole Fp2 at  
half the switching frequency.  
2´ p ´ 1uH´ 3000uF  
= 2.9kHz  
1
C1 =  
2´ p ´ R4 ´ F  
P2  
1
F
=
ESR  
1
2´ p ´ ESR´ COUT  
=
2´ p ´ 26.7kW´ 300kHz  
= 20pF  
1
=
2´ p ´ 6.5mW´ 3000uF  
= 8.2kHz  
Choose C1=22pF.  
Rev. 3.0  
03/14/06  
10  
NX2116/2116A/2116B/2117/2117A  
B. Type II compensator design  
If the electrolytic capacitors are chosen as power  
stage output capacitors, usually the Type II compensa-  
tor can be used to compensate the system.  
Vout  
R2  
Fb  
Type II compensator can be realized by simple RC  
circuit without feedback as shown in figure 7. R3 and C1  
introduce a zero to cancel the double pole effect. C2  
introduces a pole to suppress the switching noise. The  
following equations show the compensator pole zero lo-  
cation and constant gain.  
Ve  
R3  
gm  
R1  
Vref  
C2  
C1  
R1  
Gain=gm ´  
´ R3  
... (15)  
... (16)  
... (17)  
R1+R2  
Figure 7 - Type II compensator with  
1
transconductance amplifier  
F =  
z
2´ p ´ R3 ´ C1  
1
For this type of compensator, FO has to satisfy  
FLC<FESR<<FO<=1/10~1/5Fs.  
F »  
p
2´ p ´ R3 ´ C2  
The following is parameters for type II compensa-  
tor design. Input voltage is 12V, output voltage is 1.8V,  
output inductor is 1uH, output capacitors are two 1500uF  
with 13mW electrolytic capacitors.  
power stage  
1.Calculate the location of LC double pole FLC  
40dB/decade  
and ESR zero FESR  
.
1
loop gain  
F
=
=
LC  
2 ´ p ´ LOUT ´ COUT  
1
20dB/decade  
2 ´ p ´ 1uH ´ 3000uF  
= 2.9kHz  
1
compensator  
F
=
ESR  
2´ p ´ ESR ´ COUT  
Gain  
1
=
2´ p ´ 6.5mW´ 3000uF  
= 8.2kHz  
2.Set R2 equal to 1kW.  
R2 ´ VREF  
P
F
F
F
Z
LCFESR  
FO  
1kW´ 0.8V  
R1=  
=
= 800W  
Figure 6 - Bode plot of Type II compensator  
VOUT -VREF 1.8V-0.8V  
Choose R1=806W.  
3. Set crossover frequency at 1/10~ 1/5 of the  
swithing frequency, here FO=60kHz.  
4.Calculate R3 value by the following equation.  
Rev. 3.0  
03/14/06  
11  
NX2116/2116A/2116B/2117/2117A  
Vout  
4.Calculate R3 value by the following equation.  
VOSC 2´ p ´ FO ´ L VOUT  
R2  
R1  
Fb  
1
R3 =  
´
´
´
V
RESR  
gm VREF  
in  
1.5V 2´ p ´ 60kHz´ 1uH  
1
=
´
´
Vref  
12V  
6.5mW  
2.0mA/V  
1.8V  
0.8V  
´
Voltage divider  
=8.15kW  
Figure 8 - Voltage divider  
Choose R3 =8.2kW.  
5. Calculate C1 by setting compensator zero FZ  
at 75% of the LC double pole.  
Input Capacitor Selection  
Input capacitors are usually a mix of high frequency  
ceramic capacitors and bulk capacitors. Ceramic ca-  
pacitors bypass the high frequency noise, and bulk ca-  
pacitors supply switching current to the MOSFETs. Usu-  
ally 1uF ceramic capacitor is chosen to decouple the  
high frequency noise.The bulk input capacitors are de-  
cided by voltage rating and RMS current rating. The RMS  
current in the input capacitors can be calculated as:  
1
C1=  
2´ p ´ R3 ´ Fz  
1
=
2´ p ´ 8.2kW´ 0.75 ´ 2.9kHz  
=8.9nF  
Choose C1=8.2nF.  
F
6. Calculate C2 by setting compensator pole  
at half the swithing frequency.  
p
IRMS = IOUT ´ D ´ 1-D  
1
VOUT  
C 2 =  
D =  
p ´ R 3 ´ Fs  
V
IN  
...(19)  
1
=
VIN = 12V, VOUT=1.8V, IOUT=9A, using equation (19),  
the result of input RMS current is 3.2A.  
p ´ 8 .2k W ´ 3 0 0 k H z  
= 1 2 9 p F  
For higher efficiency, low ESR capacitors are rec-  
ommended. One Sanyo OS-CON 16SP180M 16V 180uF  
20mW with 3.4A RMS rating is chosen as input bulk  
capacitors.  
Choose C1=120pF.  
Output Voltage Calculation  
Output voltage is set by reference voltage and ex-  
ternal voltage divider. The reference voltage is fixed at  
0.8V. The divider consists of two ratioed resistors so  
that the output voltage applied at the Fb pin is 0.8V when  
the output voltage is at the desired value. The following  
equation and picture show the relationship between  
VOUT , VREF and voltage divider.  
Power MOSFETs Selection  
The power stage requires two N-Channel power  
MOSFETs. The selection of MOSFETs is based on  
maximum drain source voltage, gate source voltage,  
maximum current rating, MOSFET on resistance and  
power dissipation. The main consideration is the power  
loss contribution of MOSFETs to the overall converter  
efficiency. In this design example, two IRFR3709Z are  
used. They have the following parameters: VDS=30V,RDSON  
R 2 ´ VREF  
R1=  
...(18)  
VOUT -VREF  
where R2 is part of the compensator, and the value  
of R1 value can be set by voltage divider.  
=6.5mW,QGATE =17nC.  
There are two factors causing the MOSFET power  
loss:conduction loss, switching loss.  
Conduction loss is simply defined as:  
See compensator design for R1 and R2 selection.  
Rev. 3.0  
03/14/06  
12  
NX2116/2116A/2116B/2117/2117A  
sired voltage decided by the feedback resistor divider.  
P
HCON =IOUT2 ´ D´ RDS(ON) ´ K  
LCON=IOUT2 ´ (1- D)´ RDS(ON) ´ K  
PTOTAL =P + P  
P
...(20)  
Vbus  
HCON  
LCON  
where the RDS(ON) will increases as MOSFET junc-  
tion temperature increases, K is RDS(ON) temperature  
dependency. As a result, RDS(ON) should be selected for  
the worst case, in which K approximately equals to 1.4  
at 125oC according to IRFR3709Z datasheet. Conduc-  
tion loss should not exceed package rating or overall  
system thermal budget.  
POR  
R1  
R2  
Digital  
start  
up  
OFF  
10k  
EN  
ON  
1.25V/  
1.15V  
Figure 9 - Enable and Shut down the NX2116  
with Enable pin.  
Switching loss is mainly caused by crossover con-  
duction at the switching transition. The total switching  
loss can be approximated.  
The start up of NX2116 can be programmed through  
resistor divider at Enable pin. For example, if the input  
bus voltage is12V and we want NX2116 starts when Vbus  
is above 9V. We can select using the following equa-  
tion.  
1
PSW  
=
´ V ´ IOUT ´ TSW ´ F  
IN S  
...(21)  
2
where IOUT is output current, TSW is the sum of TR  
and TF which can be found in mosfet datasheet, and FS  
is switching frequency. Switching loss PSW is frequency  
dependent.  
(9V - 1.25V)´ R2  
R1 =  
1.25V  
The NX2116 can be turned off by pulling down the  
Enable pin by extra signal MOSFET as shown in the  
above Figure. When Enable pin is below 1.25V, the digi-  
tal soft start is reset to zero. In addition, all the high side  
and low side driver is off and no negative spike will be  
generated during the turn off.  
Also MOSFET gate driver loss should be consid-  
ered when choosing the proper power MOSFET.  
MOSFET gate driver loss is the loss generated by dis-  
charging the gate capacitor and is dissipated in driver  
circuits.It is proportional to frequency and is defined as:  
P
= (QHGATE ´ VHGS + QLGATE ´ VLGS )´ FS  
...(22)  
gate  
where QHGATE is the high side MOSFETs gate  
Over Current Protection  
charge,QLGATE is the low side MOSFETs gate charge,VHGS  
is the high side gate source voltage, and VLGS is the low  
Over current protection is achieved by sensing cur-  
rent through the low side MOSFET. An internal current  
source of 40uA flows through an external resistor con-  
nected from OCP pin to SW node sets the over current  
protection threshold. When synchronous FET is on, the  
voltage at node SW is given as  
side gate source voltage.  
This power dissipation should not exceed maxi-  
mum power dissipation of the driver device.  
Soft Start and Enable  
VSW =-IL ´ RDSON  
NX2116 has digital soft start for switching control-  
ler and has one enable pin for this start up. When the  
Power Ready (POR) signal is high and the voltage at  
enable pin is above 1.25V the internal digital counter  
starts to operate and the voltage at positive input of Error  
amplifier starts to increase, the feedback network will  
force the output voltage follows the reference and starts  
the output slowly. After 2048 cycles, the soft start is  
complete and the output voltage is regulated to the de-  
The voltage at pin OCP is given as  
IOCP ´ ROCP +VSW  
When the voltage is below zero, the over current  
occurss as shown in figure 10.  
Rev. 3.0  
03/14/06  
13  
NX2116/2116A/2116B/2117/2117A  
vbus  
I
OCP  
40uA  
OCP  
R
SW  
OCP  
OCP  
comparator  
Figure 10 - Over current protection  
The over current limit can be set by the following  
equation  
ISET  
I
OCP ´ ROCP  
=
K ´ RDSON  
If MOSFET RDSON=6.5mW, the worst case thermal  
consideration K=1.5 and the current limit is set at 15A,  
then  
I
SET ´ K ´ RDSON 15A ´ 1.5´ 6.5mW  
ROCP  
=
=
= 3.656kW  
IOCP  
40uA  
Choose ROCP=3.7kW  
Layout Considerations  
The layout is very important when designing high  
frequency switching converters. Layout will affect noise  
pickup and can cause a good design to perform with  
less than expected results.  
Start to place the power components, make all the  
connection in the top layer with wide, copper filled ar-  
eas. The inductor, output capacitor and the MOSFET  
should be close to each other as possible. This helps to  
reduce the EMI radiated by the power traces due to the  
high switching currents through them. Place input ca-  
pacitor directly to the drain of the high-side MOSFET, to  
reduce the ESR replace the single input capacitor with  
two parallel units. The feedback part of the system should  
be kept away from the inductor and other noise sources,  
and be placed close to the IC. In multilayer PCB use  
one layer as power ground plane and have a control cir-  
cuit ground (analog ground), to which all signals are ref-  
erenced.  
The goal is to localize the high current path to a  
separate loop that does not interfere with the more sen-  
sitive analog control function. These two grounds must  
be connected together on the PC board layout at a single  
point.  
Rev. 3.0  
03/14/06  
14  
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