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IZ74HC174A

型号：

IZ74HC174A

描述：

六路D触发器与普通时钟和复位高性能硅栅CMOS[ Hex D Flip-Flop with Common Clock and Reset High-Performance Silicon-Gate CMOS ]

品牌：

INTEGRAL[ INTEGRAL CORP. ]

页数：

6 页

PDF大小：

55 K

下载PDF手册
TECHNICAL DATA  
IN74HC174A  
Hex D Flip-Flop with  
Common Clock and Reset  
High-Performance Silicon-Gate CMOS  
The IN74HC174A is identical in pinout to the LS/ALS174. The  
device inputs are compatible with standard CMOS outputs; with pullup  
resistors, they are compatible with LS/ALSTTL outputs.  
This device consists of six D flip-flops with common Clock and  
Reset inputs. Each flip-flop is loaded with a low-to-high transition of  
the Clock input. Reset is asynchronous and active-low.  
·
·
·
·
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2.0 to 6.0 V  
Low Input Current: 1.0 mA  
ORDERING INFORMATION  
IN74HC174AN Plastic  
IN74HC174AD SOIC  
IZ74HC174A Chip  
High Noise Immunity Characteristic of CMOS Devices  
TA = -55° to 125° C for all packages  
PIN ASSIGNMENT  
LOGIC DIAGRAM  
FUNCTION TABLE  
Inputs  
Clock  
X
Output  
Reset  
L
D
X
H
L
Q
L
PIN 16=VCC  
PIN 8 = GND  
H
H
H
L
H
L
X
X
no change  
no change  
H
X = Don’t care  
L = LOW voltage level  
H = HIGH voltage level  
INTEGRAL  
1
IN74HC174A  
MAXIMUM RATINGS*  
Symbol  
Parameter  
Value  
-0.5 to +7.0  
-1.5 to VCC +1.5  
-0.5 to VCC +0.5  
±20  
Unit  
V
VCC  
DC Supply Voltage (Referenced to GND)  
DC Input Voltage (Referenced to GND)  
DC Output Voltage (Referenced to GND)  
DC Input Current, per Pin  
V
IN  
V
VOUT  
IIN  
V
mA  
mA  
mA  
mW  
IOUT  
ICC  
DC Output Current, per Pin  
±25  
DC Supply Current, VCC and GND Pins  
±50  
PD  
Power Dissipation in Still Air, Plastic DIP+  
SOIC Package+  
750  
500  
Tstg  
TL  
Storage Temperature  
-65 to +150  
260  
°C  
°C  
Lead Temperature, 1,5 mm from Case for 4 Seconds  
(Plastic DIP or SOIC Package)  
*Maximum Ratings are those values beyond which damage to the device may occur.  
Functional operation should be restricted to the Recommended Operating Conditions.  
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C  
SOIC Package: : - 7 mW/°C from 65° to 125°C  
RECOMMENDED OPERATING CONDITIONS  
Symbol  
VCC  
Parameter  
Min  
2.0  
0
Max  
6.0  
Unit  
V
DC Supply Voltage (Referenced to GND)  
DC Input Voltage, Output Voltage (Referenced to GND)  
Operating Temperature, All Package Types  
V , VOUT  
IN  
VCC  
V
TA  
-55  
+125  
°C  
ns  
tr, tf  
Input Rise and Fall Time (Figure 1)  
VCC =2.0 V  
VCC =4.5 V  
VCC =6.0 V  
0
0
0
1000  
500  
400  
This device contains protection circuitry to guard against damage due to high static voltages or electric  
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages  
to this high-impedance circuit. For proper operation, V and VOUT should be constrained to the range GND£(V or  
IN  
IN  
VOUT)£VCC.  
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused  
outputs must be left open.  
INTEGRAL  
2
IN74HC174A  
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)  
VCC  
V
Guaranteed Limit  
Symbol  
Parameter  
Test Conditions  
-55°C  
to  
£85  
°C  
£125  
°C  
Unit  
V
25°C  
V
IH  
Minimum High-Level  
Input Voltage  
VOUT³ VCC-0.1 V  
or £0.1 V  
êIOUTê£ 20 mA  
2.0  
4.5  
6.0  
1.5  
3.15  
4.2  
1.5  
3.15  
4.2  
1.5  
3.15  
4.2  
V
IL  
Maximum Low -Level  
Input Voltage  
VOUT£0.1 V  
or ³ VCC-0.1 V  
êIOUTê £ 20 mA  
2.0  
4.5  
6.0  
0.5  
1.35  
1.8  
0.5  
1.35  
1.8  
0.5  
1.35  
1.8  
V
VOH  
Minimum High-Level  
Output Voltage  
V =V or V  
IL  
êIOUTê £ 20 mA  
2.0  
4.5  
6.0  
1.9  
4.4  
5.9  
1.9  
4.4  
5.9  
1.9  
4.4  
5.9  
V
IN  
IH  
V =V or V  
IL  
IN  
IH  
êIOUTê £ 4.0 mA  
êIOUTê £ 5.2 mA  
4.5  
6.0  
3.98  
5.48  
3.84  
5.34  
3.7  
5.2  
VOL  
Maximum Low-Level  
Output Voltage  
V = V or V  
IH  
êIOUTê £ 20 mA  
2.0  
4.5  
6.0  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
V
IN  
IL  
V = V or V  
IH  
IN  
IL  
êIOUTê £ 4.0 mA  
êIOUTê £ 5.2 mA  
4.5  
6.0  
0.26  
0.26  
0.33  
0.33  
0.4  
0.4  
IIN  
Maximum Input  
Leakage Current  
V =VCC or GND  
6.0  
±0.1  
±1.0  
±1.0  
mA  
mA  
IN  
ICC  
Maximum Quiescent  
Supply Current  
(per Package)  
V =VCC or GND  
6.0  
4.0  
40  
160  
IN  
IOUT=0mA  
INTEGRAL  
3
IN74HC174A  
AC ELECTRICAL CHARACTERISTICS(CL=50pF, Input tr=tf=6.0 ns, V = 0 V, V =Vcc)  
IL  
IH  
VCC  
V
Guaranteed Limit  
Symbol  
fmax  
Parameter  
-55°C  
£85°C  
£125°C  
Unit  
MHz  
ns  
to  
25°C  
Maximum Clock Frequency (50% Duty Cycle)  
(Figures 1 and 4)  
2.0  
4.5  
6.0  
6.0  
30  
35  
4.8  
24  
28  
4.0  
20  
24  
tPLH, tPHL Maximum Propagation Delay, Clock to Q (Figures  
1 and 4)  
2.0  
4.5  
6.0  
110  
22  
19  
140  
28  
24  
165  
33  
28  
tPHL  
Maximum Propagation Delay , Reset to Q  
(Figures 2 and 4)  
2.0  
4.5  
6.0  
110  
21  
19  
140  
28  
24  
160  
32  
27  
ns  
tTLH, tTHL Maximum Output Transition Time, Any Output  
(Figures 1 and 4)  
2.0  
4.5  
6.0  
75  
15  
13  
95  
19  
16  
110  
22  
19  
ns  
CIN  
Maximum Input Capacitance  
-
10  
10  
10  
pF  
Power Dissipation Capacitance (Per Enabled  
Output)  
Typical @25°C,VCC=5.0 V  
CPD  
Used to determine the no-load dynamic power  
consumption: PD=CPDVCC2f+ICCVCC  
62  
pF  
TIMING REQUIREMENTS (CL=50pF,Input tr=tf=6.0 ns, V = 0 V, V =Vcc)  
IL  
IH  
VCC  
V
Guaranteed Limit  
Symbol  
tSU  
Parameter  
-55 °C to  
25°C  
£85°C  
£125°C  
Unit  
Minimum Setup Time, Data to  
Clock (Figure 3)  
2.0  
4.5  
6.0  
50  
10  
9
65  
13  
11  
75  
15  
13  
ns  
ns  
ns  
ns  
ns  
ns  
th  
trec  
tw  
Minimum Hold Time, Clock to  
Data (Figure 3)  
2.0  
4.5  
6.0  
5
5
5
5
5
5
5
5
5
Minimum Recovery Time,  
Reset Inactive to Clock (Figure  
2)  
2.0  
4.5  
6.0  
5
5
5
5
5
5
5
5
5
Minimum Pulse Width, Clock  
(Figure 1)  
2.0  
4.5  
6.0  
75  
15  
13  
95  
19  
16  
110  
22  
19  
tw  
Minimum Pulse Width, Reset  
(Figure 2)  
2.0  
4.5  
6.0  
75  
15  
13  
95  
19  
16  
110  
22  
19  
tr, tf  
Maximum Input Rise and Fall  
Times (Figure 1)  
2.0  
4.5  
6.0  
1000  
500  
400  
1000  
500  
400  
1000  
500  
400  
INTEGRAL  
4
IN74HC174A  
tw  
VCC  
t
t
r
f
RESET  
Q
50%  
VCC  
90%  
50%  
10%  
GND  
CLOCK  
tPHL  
GND  
tw  
50%  
1/f  
max  
tPLH  
tPHL  
trec  
Q
90%  
50%  
10%  
VCC  
CLOCK  
50%  
GND  
tTLH  
tTHL  
Figure 1. Switching Waveforms  
Figure 2. Switching Waveforms  
TEST POINT  
VALID  
VCC  
DATA  
50%  
DEVICE  
UNDER  
TEST  
OUTPUT  
GND  
tsu  
th  
*
L
C
VCC  
CLOCK  
50%  
GND  
Figure 3. Switching Waveforms  
Figure 4. Test Circuit  
EXPANDED LOGIC DIAGRAM  
INTEGRAL  
5
IN74HC174A  
CHIP PAD DIAGRAM  
Chip marking  
13  
12  
14  
11  
15  
10  
09  
16  
08  
07  
01  
02  
03  
04  
05  
06  
1.6 + 0.03  
Chip marking :15HC174  
Location of marking (mm): left lower corner x = 0.110, y = 0.870; right lower corner x = 0.240, y = 0.900  
Chip thickness: 0.46 ± 0.02 mm  
PAD LOCATION  
Pad No  
Pad size, mm  
Symbol  
Location (left lower corner), mm  
X
Y
01  
02  
03  
04  
05  
06  
07  
08  
09  
10  
11  
12  
13  
14  
15  
16  
Reset  
Q0  
D0  
D1  
Q1  
D2  
Q2  
GND  
Clock  
Q3  
D3  
Q4  
D4  
D5  
Q5  
Vcc  
0.115  
0.115  
0.325  
0.580  
0.850  
1.145  
1.345  
1.370  
1.365  
1.355  
1.155  
0.880  
0.620  
0.320  
0.125  
0.115  
0.340  
0.140  
0.115  
0.115  
0.115  
0.115  
0.140  
0.355  
0.815  
1.045  
1.065  
1.065  
1.065  
1.065  
1.045  
0.660  
0.12´ 0.12  
0.12´ 0.12  
0.12´ 0.12  
0.12´ 0.12  
0.12´ 0.12  
0.12´ 0.12  
0.12´ 0.12  
0.12´ 0.16  
0.12´ 0.12  
0.12´ 0.12  
0.12´ 0.12  
0.12´ 0.12  
0.12´ 0.12  
0.12´ 0.12  
0.12´ 0.12  
0.12´ 0.19  
Note: Location is given as per passivation layer  
INTEGRAL  
6
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