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5T93GL06NLGI8

型号：

5T93GL06NLGI8

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

18 页

PDF大小：

211 K

下载PDF手册
2.5V LVDS, 1:6 Glitchless Clock Buffer  
TERABUFFER™ II  
5T93GL06  
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016 DATA SHEET  
General Description  
Features  
The 5T93GL06 2.5V differential clock buffer is a user- selectable  
differential input to six LVDS outputs. The fanout from a differential  
input to six LVDS outputs reduces loading on the preceding driver  
and provides an efficient clock distribution network. The 5T93GL06  
can act as a translator from a differential HSTL, eHSTL, LVEPECL  
(2.5V), LVPECL (3.3V), CML, or LVDS input to LVDS outputs. A  
single-ended 3.3V / 2.5V LVTTL input can also be used to translate  
to LVDS outputs. The redundant input capability allows for a  
glitchless change-over from a primary clock source to a secondary  
clock source up to 650MHz. Selectable inputs are controlled by SEL.  
During the switchover, the output will disable low for up to three clock  
cycles of the previously-selected input clock. The outputs will remain  
low for up to three clock cycles of the newly-selected clock, after  
which the outputs will start from the newly-selected input. A FSEL  
pin has been implemented to control the switchover in cases where  
a clock source is absent or is driven to DC levels below the minimum  
specifications.  
• Guaranteed low skew: <40ps (maximum)  
• Very low duty cycle distortion: <100ps (maximum)  
• High speed propagation delay: <2ns (maximum)  
• Up to 800MHz operation  
• Glitchless input clock switching up to 650MHz  
• Selectable inputs  
• Hot insertable and over-voltage tolerant inputs  
• 3.3V/2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL  
(3.3V), CML or LVDS input interface  
• Selectable differential inputs to six LVDS outputs  
• Power-down mode  
• At power-up, FSEL should be LOW  
• 2.5V VDD  
• -40°C to 85°C ambient operating temperature  
• Available in VFQFN package  
The 5T93GL06 outputs can be asynchronously enabled/ disabled.  
When disabled, the outputs will drive to the value selected by the GL  
pin. Multiple power and grounds reduce noise.  
• Recommends IDT5T9306 if glitchless input selection is not  
required  
• Not Recommended for New Designs  
• For functional replacement use 8SLVD1208  
Applications  
• Clock distribution  
Pin Assignment  
28 27 26 25 24 23 22  
1
2
3
4
5
6
7
G
PD  
20 VDD  
Q4  
21  
VDD  
19  
Q1  
Q1  
GND  
18 Q4  
VDD  
17  
VDD  
A1  
16 A2  
15 A2  
A1  
8
9
10 11 12 13 14  
28-Lead VFQFN  
4.8mm x 4.8mm x 0.925mm package body  
K Package  
Top View  
5T93GL06 REVISION C 3/16/15  
1
©2015 Integrated Device Technology, Inc.  
5T93GL06 DATA SHEET  
Block Diagram  
GL  
G
Q1  
Q1  
OUTPUT  
CONTROL  
PD  
Q2  
Q2  
OUTPUT  
CONTROL  
A1  
A1  
1
0
Q3  
Q3  
OUTPUT  
CONTROL  
A2  
A2  
Q4  
Q4  
OUTPUT  
CONTROL  
Q5  
Q5  
OUTPUT  
CONTROL  
SEL  
FSEL  
Q6  
Q6  
OUTPUT  
CONTROL  
2.5V LVDS, 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER™ II  
2
REVISION C 3/16/15  
5T93GL06 DATA SHEET  
Table 1. Pin Descriptions  
Name  
Type  
Description  
A[1:2]  
Input  
Input  
Adjustable (1, 4) Clock input. A[1:2] is the "true" side of the differential clock input.  
Complementary clock inputs. A[1:2] is the complementary side of A[1:2].  
For LVTTL single-ended operation, A[1:2] should be set to the desired toggle voltage for  
Adjustable (1, 4) A[1:2]:  
A[1:2]  
3.3V LVTTL VREF = 1650mV  
2.5V LVTTL VREF = 1250mV  
Gate control for differential outputs Q1 and Q1 through Q6 and Q6. When G is HIGH, the  
G
Input  
Input  
LVTTL  
LVTTL  
differential outputs are asynchronously driven to the level designated by GL(2). When G is  
LOW, the differential outputs are active.  
Specifies output disable level. If HIGH, “true” outputs disable HIGH and “complementary”  
outputs disable LOW. If LOW, “true” outputs disable LOW  
and “complementary” outputs disable HIGH.  
GL  
Q[1:2]  
Q[1:2]  
Output  
Output  
LVDS  
LVDS  
Clock outputs.  
Complementary clock outputs.  
Reference clock select. When LOW, selects A2 and A2.  
When HIGH, selects A1 and A1.  
SEL  
PD  
Input  
Input  
LVTTL  
LVTTL  
Power-down control. Shuts off entire chip. If LOW, the device goes into low power mode.  
Inputs and outputs are disabled. Both “true” and “complementary” outputs will pull to VDD.  
Set HIGH for normal operation.(3)  
At a rising edge, FSEL forces select to the input designated by SEL. Apply a  
LOW-to-HIGH transition to force an input selection. Set to logic LOW level at startup and  
if a forced input selection is not needed.  
FSEL  
Input  
LVTTL  
VDD  
Power  
Power  
Power supply for the device core and inputs.  
Ground.  
GND  
NOTES:  
1.  
Inputs are capable of translating the following interface standards:  
Single-ended 3.3V and 2.5V LVTTL levels  
Differential HSTL and eHSTL levels  
Differential LVEPECL (2.5V) and LVPECL (3.3V) levels  
Differential LVDS levels  
Differential CML levels  
2.  
3.  
4.  
Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control  
signals to minimize the possibility of runt pulses or be able to tolerate them in down stream circuitry.  
It is recommended that the outputs be disabled before entering power-down mode. It is also recommended that the outputs remain  
disabled until the device completes power-up after asserting PD.  
The user must take precautions with any differential input interface standard being used in order to prevent instability when there is  
no input signal.  
Table 2. Pin Characteristics (TA = +25°C, F = 1.0MHz)  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
CIN  
Input Capacitance  
3
pF  
NOTE: This parameter is measured at characterization but not tested.  
2.5V LVDS, 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER™ II  
3
REVISION C 3/16/15  
5T93GL06 DATA SHEET  
Function Tables  
Table 3A. Gate Control Output Table  
Control Output  
Outputs  
GL  
0
G
0
1
0
1
Q[1:6]  
Q[1:6]  
Toggling  
HIGH  
Toggling  
LOW  
0
1
Toggling  
HIGH  
Toggling  
LOW  
1
Table 3B. Input Selection Table  
Selection SEL pin  
Inputs  
A2/A2  
A1/A1  
0
1
Absolute Maximum Ratings  
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress  
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC  
Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.  
Item  
Rating  
Power Supply Voltage, VDD  
Input Voltage, VI  
-0.5V to +3.6V  
-0.5V to +3.6V  
Output Voltage, VO  
Not to exceed 3.6V  
-0.5 to VDD +0.5V  
Storage Temperature, TSTG  
Junction Temperature, TJ  
-65C to 150C  
150C  
Recommended Operating Range  
Symbol  
TA  
Description  
Minimum  
Typical  
+25  
Maximum  
+85  
Units  
C  
Ambient Operating Temperature  
Internal Power Supply Voltage  
-40  
2.3  
VDD  
2.5  
2.7  
V
REVISION C 3/16/15  
4
2.5V LVDS, 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER™ II  
5T93GL06 DATA SHEET  
DC Electrical Characteristics  
Table 4A. LVDS Power Supply DC Characteristics(1), TA = -40°C to 85°C  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical(2)  
Maximum  
Units  
Quiescent VDD  
Power Supply Current  
VDD = Max., All Input Clocks = LOW(2)  
Outputs enabled  
;
IDDQ  
240  
mA  
Total Power  
VDD Supply Current  
VDD = 2.7V;  
FREFERENCE Clock = 800MHz  
ITOT  
IPD  
250  
5
mA  
mA  
Total Power Down  
Supply Current  
PD = LOW  
NOTE 1: These power consumption characteristics are for all the valid input interfaces and cover the worst case conditions.  
NOTE 2: The true input is held LOW and the complementary input is held HIGH.  
Table 4B. LVTTL DC Characteristics(1), TA = -40°C to 85°C  
Symbol  
IIH  
Parameter  
Test Conditions  
VDD = 2.7V  
Minimum  
Typical(2)  
Maximum  
Units  
µA  
µA  
V
Input High Current  
Input Low Current  
Clamp Diode Voltage  
DC Input Voltage  
DC Input High Voltage  
DC Input Low Voltage  
5
5
IIL  
VDD = 2.7V  
VIK  
VDD = 2.3V, IIN = -18mA  
-0.7  
-1.2  
3.6  
VIN  
-0.3  
1.7  
V
VIH  
V
VIL  
0.7  
V
DC Input Threshold Crossing  
Voltage  
VTHI  
VDD/2  
V
3.3V LVTTL  
2.5V LVTTL  
1.65  
1.25  
V
V
VREF  
Single-Ended Reference Voltage (3)  
NOTE 1: See Recommended Operating Range table.  
NOTE 2: Typical values are at VDD = 2.5V, +25°C ambient.  
NOTE 3: For A[1:2] single-ended operation, A[1:2] is tied to a DC reference voltage.  
Table 4C. Differential DC Characteristics(1), TA = -40°C to 85°C  
Symbol  
IIH  
Parameter  
Test Conditions  
VDD = 2.7V  
Minimum  
Typical(4)  
Maximum  
Units  
µA  
µA  
V
Input High Current  
5
5
IIL  
Input Low Current  
VDD = 2.7V  
VIK  
Clamp Diode Voltage  
DC Input Voltage  
DC Differential Voltage(2)  
DC Common Mode Input Voltage(3)  
VDD = 2.3V, IIN = -18mA  
-0.7  
-1.2  
3.6  
VIN  
-0.3  
0.1  
V
VDIF  
VCM  
V
0.05  
VDD  
V
NOTE 1: See Recommended Operating Range table.  
NOTE 2: VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is  
the "complement" input level. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC  
differential voltage must be achieved to guarantee switching to a new state.  
NOTE 3: VCM specifies the maximum allowable range of (VTR + VCP) /2.  
NOTE 4: Typical values are at VDD = 2.5V, +25°C ambient.  
2.5V LVDS, 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER™ II  
5
REVISION C 3/16/15  
5T93GL06 DATA SHEET  
Table 4D. LVDS DC Characteristics(1), TA = -40°C to 85°C  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical(2)  
Maximum  
Units  
Differential Output Voltage for the  
True Binary State  
VOT(+)  
247  
454  
mV  
Differential Output Voltage for the  
False Binary State  
VOT(–)  
VOT  
VOS  
247  
454  
50  
mV  
mV  
V
Change in VOT Between  
Complementary Output States  
Output Common Mode Voltage  
(Offset Voltage)  
1.125  
1.2  
1.375  
Change in VOS Between  
Complementary Output States  
VOS  
IOS  
50  
24  
12  
mV  
mA  
mA  
Outputs Short Circuit Current  
VOUT+ and VOUT– = 0V  
VOUT+ = VOUT–  
12  
6
Differential Outputs Short Circuit  
Current  
IOSD  
NOTE 1: See Recommended Operating Range table.  
NOTE 2: Typical values are at VDD = 2.5V, +25°C ambient.  
AC Electrical Characteristics  
Table 5A. HSTL Differential Input AC Characteristics, TA = -40°C to 85°C  
Symbol  
VDIF  
VX  
Parameter  
Input Signal Swing(1)  
Differential Input Signal Crossing Point(2)  
Value  
Units  
V
1
750  
50  
mV  
%
DH  
Duty Cycle  
VTHI  
tR / tF  
Input Timing Measurement Reference Level(3)  
Input Signal Edge Rate(4)  
Crossing Point  
2
V
V/ns  
NOTE 1.The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE)  
environment. This device meets the VDIF (AC) specification under actual use conditions.  
NOTE 2.A 750mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment.  
This device meets the VX specification under actual use conditions.  
NOTE 3.In all cases, input waveform timing is marked at the differential cross-point of the input signals.  
NOTE 4.The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.  
REVISION C 3/16/15  
6
2.5V LVDS, 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER™ II  
5T93GL06 DATA SHEET  
Table 5B. eHSTL AC Differential Input Characteristics, TA = -40°C to 85°C  
Symbol  
VDIF  
VX  
Parameter  
Input Signal Swing(1)  
Differential Input Signal Crossing Point(2)  
Value  
Units  
V
1
900  
mV  
%
DH  
Duty Cycle  
50  
VTHI  
tR / tF  
Input Timing Measurement Reference Level(3)  
Input Signal Edge Rate(4)  
Crossing Point  
2
V
V/ns  
NOTE 1.The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE)  
environment. This device meets the VDIF (AC) specification under actual use conditions.  
NOTE 2.A 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment.  
This device meets the VX specification under actual use conditions.  
NOTE 3.In all cases, input waveform timing is marked at the differential cross-point of the input signals.  
NOTE 4.The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.  
Table 5C. LVEPECL (2.5V) and LVPECL (3.3V) Differential Input AC Characteristics, TA = -40°C to 85°C  
Symbol  
Parameter  
Input Signal Swing(1)  
Maximum  
Units  
mV  
mV  
mV  
%
VDIF  
732  
LVEPECL  
LVPECL  
1082  
VX  
Differential Input Cross Point Voltage(2)  
1880  
DH  
Duty Cycle  
50  
VTHI  
tR / tF  
Input Timing Measurement Reference Level(3)  
Input Signal Edge Rate(4)  
Crossing Point  
2
V
V/ns  
NOTE 1.The 732mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE)  
environment. This device meets the VDIF (AC) specification under actual use conditions.  
NOTE 2.A 1082mV LVEPECL (2.5V) and 1880mV LVPECL (3.3V) crossing point level is specified to allow consistent, repeatable results in an  
automatic test equipment (ATE) environment. This device meets the VX specification under actual use conditions.  
NOTE 3.In all cases, input waveform timing is marked at the differential cross-point of the input signals.  
NOTE 4.The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.  
Table 5D. LVDS Differential Input AC Characteristics, TA = -40°C to 85°C  
Symbol  
VDIF  
VX  
Parameter  
Input Signal Swing(1)  
Differential Input Cross Point Voltage(2)  
Maximum  
Units  
mV  
V
400  
1.2  
DH  
Duty Cycle  
50  
%
VTHI  
tR / tF  
Input Timing Measurement Reference Level(3)  
Input Signal Edge Rate(4)  
Crossing Point  
2
V
V/ns  
NOTE 1.The 400mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE)  
environment. This device meets the VDIF (AC) specification under actual use conditions.  
NOTE 2.A 1.2V crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This  
device meets the VX specification under actual use conditions.  
NOTE 3.In all cases, input waveform timing is marked at the differential cross-point of the input signals.  
NOTE 4.The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.  
2.5V LVDS, 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER™ II  
7
REVISION C 3/16/15  
5T93GL06 DATA SHEET  
Table 5E. AC Differential Input Characteristics(1), TA = -40°C to 85°C  
Symbol  
VDIF  
VX  
Parameter  
Minimum  
0.1  
Typical  
Maximum  
3.6  
Units  
AC Differential Voltage(2)  
Differential Input Cross Point Voltage  
Common Mode Input Voltage Range(3)  
Input Voltage  
V
V
V
V
0.05  
VDD  
VCM  
VIN  
0.05  
VDD  
-0.3  
3.6  
NOTE 1.The output will not change state until the inputs have crossed and the minimum differential voltage range defined by VDIF has been  
met or exceeded.  
NOTE 2.VDIF specifies the minimum input voltage (VTR – VCP) required for switching where VTR is the “true” input level and VCP is the  
“complement” input level. The AC differential voltage must be achieved to guarantee switching to a new state.  
NOTE 3.VCM specifies the maximum allowable range of (VTR + VCP) /2.  
Table 5F. AC Characteristics(1,5), TA = -40°C to 85°C  
Symbol  
tsk(o)  
tsk(p)  
tsk(pp)  
tpLH  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
ps  
Same Device Output Pin-to-Pin Skew (2)  
Pulse Skew(3)  
Part-to-Part Skew(4)  
40  
115  
300  
2
ps  
ps  
Propagation Delay, Low-to-High  
Propagation Delay, High-to-Low  
Frequency Range(6)  
1.5  
1.5  
ns  
A Crosspoint to  
Qn/Qn Crosspoint  
tpHL  
2
ns  
fo  
800  
MHz  
Output Gate Enable Crossing  
VTHI-to-Qn/Qn Crosspoint  
tPGE  
3.5  
3.5  
ns  
ns  
Output Gate Enable Crossing  
VTHI-to-Qn/Qn Crosspoint Driven to  
GL Designated Level  
tPGD  
tPWRDN  
tPWRUP  
PD Crossing VTHI-to-Qn = VDD, Qn = VDD  
100  
100  
µS  
µS  
Output Gate Disable Crossing VTHI to  
Qn/Qn Driven to Designated Level  
NOTE: Characterized at 300MHz, unless otherwise noted.  
NOTE 1. AC propagation measurements should not be taken within the first 100 cycles of startup.  
NOTE 2. Skew measured between crosspoints of all differential output pairs under identical input and output interfaces, transitions and load  
conditions on any one device.  
NOTE 3. Skew measured is the difference between propagation delay times tpHL and tpLH of any single differential output pair under identical  
input and output interfaces, transitions and load conditions on any one device.  
NOTE 4. Skew measured is the magnitude of the difference in propagation times between any single differential output pair of two devices,  
given identical transitions and load conditions at identical VDD levels and temperature.  
NOTE 5. All parameters are tested with a 50% input duty cycle.  
NOTE 6. Guaranteed by design but not production tested.  
REVISION C 3/16/15  
8
2.5V LVDS, 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER™ II  
5T93GL06 DATA SHEET  
Differential AC Timing Waveforms  
Output Propagation and Skew Waveforms  
1/fo  
+ VDIF  
VDIF = 0  
- VDIF  
A[1:2] - A[1:2]  
tPHL  
tPLH  
+ VDIF  
VDIF = 0  
- VDIF  
Qn - Qn  
tSK(O)  
tSK(O)  
+ VDIF  
VDIF = 0  
- VDIF  
Qm - Qm  
NOTE 1: Pulse skew is calculated using the following expression:  
tsk(p) = |tpHL – tpLH|  
Note that the tpHL and tpLH shown above are not valid measurements for this calculation because they are not taken from the same pulse.  
NOTE 2: AC propagation measurements should not be taken within the first 100 cycles of startup.  
Differential Gate Disabled/Endable Showing Runt Pulse Generation  
+ VDIF  
VDIF = 0  
- VDIF  
A[1:2] - A[1:2]  
VIH  
VTHI  
VIL  
GL  
G
tPLH  
VIH  
VTHI  
VIL  
tPGE  
tPGD  
+ VDIF  
VDIF = 0  
- VDIF  
Qn - Qn  
NOTE 1: As shown, it is possible to generate runt pulses on gate disable and enable of the outputs. It is the user’s responsibility to time the G  
signal to avoid this problem.  
2.5V LVDS, 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER™ II  
9
REVISION C 3/16/15  
5T93GL06 DATA SHEET  
Glitchless Output Operation with Switching Input Clock Selection  
+ VDIF  
VDIF = 0  
- VDIF  
A1 - A1  
+ VDIF  
VDIF = 0  
- VDIF  
A2 - A2  
SEL  
VIH  
VTHI  
VIL  
+ VDIF  
VDIF = 0  
- VDIF  
Qn - Qn  
1. When SEL changes, the output clock goes LOW on the falling edge of the output clock up to three cycles later. The output then stays LOW  
for up to three clock cycles of the new input clock. After this, the output starts with the rising edge of the new input clock.  
2. AC propagation measurements should not be taken within the first 100 cycles of startup.  
FSEL Operation for When Current Clock Dies  
1. When the differential on the selected clock goes below the minimum DC differential, the outputs clock goes to an unknown state. When this  
happens, the SEL pin should be toggled and FSEL asserted in order to force selection of the new input clock. The output clock will start up  
after a number of cycles of the newly-selected input clock.  
2. The FSEL pin should stay asserted until the problem with the dead clock can be fixed in the system.  
3. It is recommended that the FSEL be tied LOW for systems that use only one input. If this is not possible, the user must guarantee that the  
unused input have a differential greater than or equal to the minimum DC differential specified in the datasheet.  
REVISION C 3/16/15  
10  
2.5V LVDS, 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER™ II  
5T93GL06 DATA SHEET  
FSEL Operation for When Opposite Clock Dies  
1. When the differential on the non-selected clock goes below the minimum DC differential, the outputs clock goes to an unknown state. When  
this happens, the FSEL pin should be asserted in order to force selection of the new input clock. The output clock will start up after a number  
of cycles of the newly-selected input clock.  
2. The FSEL pin should stay asserted until the problem with the dead clock can be fixed in the system.  
3. It is recommended that the FSEL be tied LOW for systems that use only one input. If this is not possible, the user must guarantee that the  
unused input have a differential greater than or equal to the minimum DC differential specified in the datasheet.  
Selection of Input While Protecting Against When Opposite Clock Dies  
+VDIF  
A1 - A1  
A2 - A2  
FSEL  
SEL  
VDIF=0  
-VDIF  
+VDIF  
VDIF=0  
-VDIF  
VIH  
VTHI  
VIL  
VIH  
VTHI  
VIL  
+VDIF  
VDIF=0  
-VDIF  
Qn - Qn  
1. If the user holds FSEL HIGH, the output will not be affected by the deselected input clock.  
2. The output will immediately be driven to LOW once FSEL is asserted. This may cause glitching on the output. The output will restart with  
the input clock selected by the SEL pin.  
3. If the user decides to switch input clocks, the user must de-assert FSEL, then assert FSEL after toggling the SEL input pin. The output will  
be driven LOW and will restart with the input clock selected by the SEL pin.  
2.5V LVDS, 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER™ II  
11  
REVISION C 3/16/15  
5T93GL06 DATA SHEET  
Power Down Timing  
+VDIF  
VDIF=0  
-VDIF  
A1 - A1  
+VDIF  
VDIF=0  
-VDIF  
A2 - A2  
VIH  
VTHI  
VIL  
G
VIH  
VTHI  
VIL  
PD  
+VDIF  
VDIF=0  
-VDIF  
Qn - Qn  
NOTE 1: It is recommended that outputs be disabled before entering power-down mode. It is also recommended that the outputs remain  
disabled until the device completes power-up after asserting PD.  
NOTE 2: The Power Down Timing diagram assumes that GL is HIGH.  
NOTE 3: It should be noted that during power-down mode, the outputs are both pulled to VDD. In the Power Down Timing diagram this is  
shown when Qn/Qn goes to VDIF = 0.  
REVISION C 3/16/15  
12  
2.5V LVDS, 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER™ II  
5T93GL06 DATA SHEET  
Test Circuits and Conditions  
Test Circuit for Differential Input  
~50  
VIN  
Transmission Line  
VDD/2  
A
A
D.U.T.  
Pulse  
Generator  
~50  
VIN  
Transmission Line  
-VDD/2  
Scope  
50  
50  
Table 6A. Differential Input Test Conditions  
Symbol  
VDD = 2.5V 0.2V  
Unit  
VTHI  
Crossing of A and A  
V
2.5V LVDS, 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER™ II  
13  
REVISION C 3/16/15  
5T93GL06 DATA SHEET  
Test Circuit for DC Outputs and Power Down Tests  
VDD  
A
A
Qn  
Qn  
Pulse  
Generator  
RL  
RL  
D.U.T.  
VOS  
VOD  
Test Circuit for Propagation, Skew, and Gate Enable/Disable Timing  
VDD/2  
SCOPE  
CL  
Z = 50  
A
A
Qn  
Qn  
Pulse  
Generator  
50  
50  
D.U.T.  
Z = 50  
CL  
-VDD/2  
Table 6B. Differential Input Test Conditions  
Symbol  
VDD = 2.5V 0.2V  
Unit  
pF  
pF  
0(1)  
8(1,2)  
50  
CL  
RL  
NOTE 1: Specifications only apply to “Normal Operations” test condition. The TIA/EIA specification load is for reference only.  
NOTE 2: The scope inputs are assumed to have a 2pF load to ground. TIA/EIA – 644 specifies 5pF between the output pair.  
With CL = 8pF, this gives the test circuit appropriate 5pF equivalent load.  
REVISION C 3/16/15  
14  
2.5V LVDS, 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER™ II  
5T93GL06 DATA SHEET  
Recommended Landing Pattern  
6.30  
4.80  
N
1
2
3
5.20  
4.80 6.30  
0.35  
0.65  
5.20  
2.5V LVDS, 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER™ II  
15  
REVISION C 3/16/15  
5T93GL06 DATA SHEET  
Ordering Information  
Table 7. Ordering Information  
XXXXX  
XX  
X
Device Type  
Package  
Process  
I
-40°C to + 85°C (Industrial)  
VFQFN - Green  
NLG  
2.5V LVDS 1:6 Glitchless Clock Buffer  
5T93GL06  
Terabuffer™ II  
REVISION C 3/16/15  
16  
2.5V LVDS, 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER™ II  
5T93GL06 DATA SHEET  
Revision History Sheet  
Rev  
Table  
Page  
Description of Change  
Date  
T3A  
T3B  
4
4
Added Gate Control Output Table.  
Added Input Selection Table.  
Converted datasheet format.  
B
8/17/09  
1
3
Pin Assignment - added GND pad to diagram.  
C
T1  
T5F  
T7  
Pin Description Table - updated FSEL description.  
10/1/09  
10 - 11  
FSEL Operation diagrams, NOTE 3, corrected word “HIGH” to “LOW” in sentence.  
8
1
Added NOTE: Characterized at 300MHz, unless otherwise noted.  
NRND - Not Recommended for New designs  
C
C
C
1/18/13  
3/16/15  
3/10/16  
16  
Ordering Information - Removed leaded device, PDN N-13-11.  
Updated datasheet format.  
1
Product Discontinuation Notice - Last time buy expires September 7, 2016.  
PDN N-16-02  
2.5V LVDS, 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER™ II  
17  
REVISION C 3/16/15  
Corporate Headquarters  
6024 Silver Creek Valley Road  
San Jose, CA 95138 USA  
Sales  
Tech Support  
email: clocks@idt.com  
1-800-345-7015 or 408-284-8200  
Fax: 408-284-2775  
www.IDT.com  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in  
this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined  
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether  
express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This  
document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.  
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably  
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or  
other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as  
those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any  
circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.  
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected  
names, logos and designs, are the property of IDT or their respective third party owners.  
Copyright ©2015 Integrated Device Technology, Inc.. All rights reserved.  
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