NW6005
Enhanced Type II Caller ID Decoder
FSK Demodulation
Mode ‘1’(CB0 is high)
The key part among the functions offered by NW6005 is FSK
demodulation. This function is implemented by several stages:
first, the carrier detector provides an indication of the presence
of signal at the bandpass filter output; second, the device’s
dual mode serial interface allows convenient extraction of the
8-bit data words in the demodulated FSK bit stream.
In this mode, the received byte is stored on chip. The
microcontroller supplies read pulses (DCLK) to shift the register
contents serially out of the NW6005, onto the DATA pin. The
NW6005 asserts DR to denote the word boundary and indicate
to the microprocessor that a new word has become available.
Internal to the device, the demodulated data bits are sampled
and stored. Midway through the stop bit, the 8 data bits and
the stop bit are parallel loaded into an 9-bit shift register and
DR goes low. The contents of register are shifted out to DATA
pin on DCLK’s rising edge with LSB (Least Significant Bit) out
first. If DCLK begins while DR is low, DR will return to high
upon the first DCLK rising edge. This feature allows the
associated interrupt to be cleared by the first read pulse.
Otherwise, DR stays low for half a nominal bit time (1/2400
sec) and then returns to high. After the last bit (Most Significant
Bit) has been read, additional DCLKs are ignored. Fig. 18 shows
the timing diagram of Mode ‘1’ operation.
The FSK characteristics are different in BT, ETSI and Bellcore
specifications. The signal frequencies in BT and ETSI
correspond to ITU-T V.23; the Bellcore frequencies correspond
to Bell 202. The NW6005 is compatible with both formats. It
also meets the signal characteristics by setting the Tip/Ring
input OP amp at unity gain in 5 V operation.
ITU-T V.23
Bell 202
Mark Freq.
(‘1’)
1300 Hz ± 1.5%
1200 Hz ± 1%
Space Freq.
(‘0’)
2100 Hz ± 1.5%
2200 Hz ± 1%
Reading the stop bit is a method of checking framing errors. If
it’s certain that there is no framing error would occur, the
microcontroller only needs to send 8 DCLK pulses to shift the
data byte out. After the checksum byte has be received, all 9
bits should be read and framing error checked.
For 3 V operation, the FSK receiver becomes easier to accept
lower level signals than in 5 V operation. The Tip/Ring input OP
amp gain should be reduced to maintain the FSK reject level.
FSK Carrier Detection
Serial FSK Interface
The carrier detector detects the presence of a signal of sufficient
amplitude at the output of the FSK bandpass filter. If the signal
is qualified by a digital algorithm, it set the CD output to low
indicating a successful carrier detection. NW6005 supplies a
10 ms hysteresis to allow for momentary signal drop out once
CD has been activated. When there is no activity at the FSK
bandpass filter output for 10 ms, CD is released.
The three wire DATA, DCLK and DR form the data interface of
the FSK demodulation. The DATApin is the serial data pin that
outputs data to external devices. The DCLK pin is the data
clock which is used in Mode ‘1’ and is generated by an exter-
nal device. The DR pin is the data ready signal used in Mode
‘1’, also an output from the NW6005 to external devices. DR/
STD pin is a dual purpose output pin, when FSK function is
selected it is DR.
When CD is inactive (high), the raw output of the FSK de-
modulator is ignored by the FSK data output interface. In
mode‘0’, the DATApin is forced high. In mode ‘1’, the internal
shift register is not updated. If DCLK is clocked, DATA is un-
defined.
The FSK interface provides the mechanism to extract the 8-bit
data words in the demodulated FSK bit stream without the
need either for an external UART or for the CPE’s
microcontroller to perform the function in software. Two modes
are selectable via control of the device’s CB0 pin: Mode ‘0’
(CB0 is low), where the FSK bit stream is output directly; Mode
‘1’ (CB0 is high), where the data byte and the stop bit are
stored in a 9 bit buffer.
Since signals such as DT-AS, DTMF tones and speech are
within the FSK frequency band and thus may activate the car-
rier detector. The NW6005 should be put into DT-AS or power
down mode when FSK is not expected to avoid false carrier
detection and false demodulation.
Mode ‘0’(CB0 is low)
In this mode, the device demodulates the incoming FSK signal,
and output the data directly to the DATA pin. DCLK and DR
pins are unused. Fig. 19 and Fig. 20 shows the timing diagram
of Mode ‘0’ operation.
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