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NW6003

型号:

NW6003

描述:

II型来电显示解码器[ TYPE II CALLER ID DECODER ]

品牌:

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数:

21 页

PDF大小:

306 K

NW6003  
TYPE II CALLER ID DECODER  
FEATURES  
DESCRIPTION  
·
1200 baud Bell 202 and ITU-T V.23 Frequency Shift Keying (FSK)  
Demodulation  
The NW6003 device is a single-chip, 3/5 Volt CMOS caller ID and  
call waiting detection circuit. It can receive signals following Bellcore  
GR-30-CORE & SR-TSV-002476, BT SIN227 & SIN242, and CCA TW/  
P&E/312 specifications.  
·
Compliant with three specifications:  
Bellcore GR-30-CORE & SR-TSV-002476  
British Telecom (BT) SIN227 & SIN242  
Cable Communication Association (CCA) TW/P&E/312  
Bellcore “CPE Alerting Signal (CAS)” and British Telecom “Idle  
State and Loop State Tone Alert Signal” detection  
Ring and line reversal detection  
High sensitivity with -40 dBV input Tone and FSK Detection  
Serial data interface to microcontroller  
3 V ±10% or 5 V ±10% operation  
The NW6003 provides 1200 baud Bell 202 and ITU-T V.23 FSK  
demodulation. It allows a microcontroller to extract data from it via a  
serial interface. In addition, the NW6003 offers Idle State and Loop  
State Tone Alert Signal and line reversal detection capability for BT  
CLIP, ring burst detection for the CCA CLIP, and ring and CAS  
detection for Bellcore CID.  
·
·
·
·
·
·
·
·
Low power CMOS with powerdown mode  
Operating temperature range: -40 °C to +85 °C  
Packages available:  
The device can be used in feature or cordless phones for BT  
Calling Line Identity Presentation (CLIP), CCA CLIP and Bellcore  
Calling Identity Delivery (CID) systems. It can also be used in caller ID  
boxes, modem, fax machines, answering machines, database query  
systems and Computer Telephony Integration (CTI) systems.  
NW6003-XS 24 pin SOIC  
(where ‘X’ is the revision ID)  
FUNCTIONAL BLOCK DIAGRAM  
TRIGOUT  
TRIGIN  
TRIGRC  
OSCIN  
Oscillator  
Line Reverse  
and  
INT  
OSCOUT  
Interrupt  
Generator  
Ring Detector  
3 V/5 V  
Detector  
STD  
Guard Time  
ST/GT  
VREF  
Bias  
Generator  
PWDN  
Dual Tone  
Detector  
EST  
CAP  
CD  
DCLK  
DATA  
DR  
IN +  
IN -  
+
FSK  
Demodulator  
Data/Timing Recovery  
-
MODE  
FSKEN  
GS  
Figure 1. Block Diagram  
The IDT logo is a registered trademark of Integrated Device Technology, Inc  
INDUSTRIAL TEMPERATURE RANGE  
JULY 2002  
ã 2002 Integrated Device Technology, Inc.  
DSC-6047/2  
NW6003 TYPE II CALLER ID DECODER  
INDUSTRIAL TEMPERATURE RANGE  
PIN INFORMATION  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
VCC  
ST/GT  
EST  
IN+  
IN-  
2
3
GS  
4
STD  
INT  
VREF  
CAP  
5
6
CD  
TRIGIN  
TRIGRC  
7
DR  
8
DATA  
DCLK  
FSKEN  
PWDN  
TM  
TRIGOUT  
MODE  
9
10  
11  
12  
OSCIN  
OSCOUT  
GND  
Figure 2. Pin Assignment  
Name  
IN+  
Type Pin No.  
Description  
I
I
1
2
3
Non-inverting Input of the gain adjustable op amp.  
Inverting Input of the gain adjustable op amp.  
Gain Select Output of the gain adjustable op amp.  
IN-  
GS  
O
Select the op amp gain by adjusting the resistor ratio in the feed-back resistor network.  
Reference Voltage.  
This output is used to bias the input op amp. It is typically VCC/2.  
Capacitor Connector.  
A 0.1mF decoupling capacitor should be connected between this pin and GND.  
Trigger Input.  
This is a Schmitt trigger input used for ring detection and line reversal detection.  
Trigger Resistor and Capacitor Connector.  
VREF  
CAP  
O
O
4
5
6
7
TRIGIN  
TRIGRC  
I
I/O  
This pin is connected to VCC and GND through resistor and capacitor. The RC value  
decides the time delay from TRIGIN going inactive (low) to TRIGOUT becoming inactive  
(high). See Fig.6 for reference.  
TRIGOUT  
MODE  
O
I
8
9
Trigger Output.  
This is a Schmitt trigger buffer output indicating the detection of line reversal and/or ringing.  
Serial FSK Interface MODE Select.  
A low level on this pin sets the interface to mode '0', while a high level sets it to mode '1'.  
OSCIN  
I
10 Oscillator Input.  
A 3.579545 MHz crystal or ceramic resonator should be connected between this pin and  
the OSCOUT. It can also be driven by an external clock source.  
11 Oscillator Output.  
OSCOUT  
O
A 3.579545 MHz crystal or ceramic resonator should be connected between this pin and  
and OSCIN. When OSCIN is driven by an external clock, this pin should be left floating.  
12 Ground.  
GND  
TM  
--  
I
13 Test Mode. Must be connected to GND for normal operation.  
2
NW6003 TYPE II CALLER ID DECODER  
PIN INFORMATION (CONTINUED)  
Name Type Pin No.  
INDUSTRIAL TEMPERATURE RANGE  
Description  
PWDN  
I
14 Power Down.  
This is an active high Schmitt trigger input. When active, the device enters a minimal  
TRIGRC  
TRIGOUT  
.
power state by disabling all internal functional circuits except TRIGIN,  
It must be low for normal operation.  
and  
FSKEN  
I
15 FSK Enable.  
When this pin is high, FSK demodulation is enabled. This pin should be set low to disable  
the FSK demodulator from reacting to extraneous signals such as speech, alert signal etc.  
DCLK I/NC  
16 Data Clock.  
In mode '0' (MODE pin low), this pin is unused. In mode '1' (MODE pin high), this pin is an  
input, Data Clock is provided by microcontroller.  
DATA  
O
17 Data Output.  
In mode '0', data appears on this pin once demodulated. In mode '1', data is shifted out on the  
rising edge of DCLK, which is supplied by microcontroller.  
O/NC  
18 Data Ready Output.  
DR  
In mode '0', this pin is unused. In mode '1', this pin indicates to the microcontroller that 8-bit  
data is ready. Microcontroller initializes the DCLK signal to read out the data.  
19 FSK Carrier Detect .  
This is an active low CMOS output signal to indicate the presence of in-band FSK signal.  
20 Interrupt.  
CD  
INT  
O
OD  
This is an active low open drain output. This pin is used to interrupt the microcontroller when  
TRIGOUT or DR is low, or STD is high. It remains low until all three signals become inactive.  
21 Dual Tone Alert Signal Delayed Steering Output.  
An active high signal to indicate the detection of a "guard time qualified" Dual Tone Alert Signal.  
22 Dual Tone Alert Signal Early Steering Output.  
STD  
EST  
O
O
This pin is an active high output to indicate the detection of Dual Tone Alert Signal.  
23 Dual Tone Alert Signal Steering Input/Guard Time.  
ST/GT  
I/O  
It's a CMOS output and an input of voltage comparator. If the voltage at this pin is greater than  
voltage threshold (See Fig-6), STD is asserted high to indicate that a dual tone has been  
detected. A voltage less than threshold enables the device to accept a new dual tone. External  
RC are connected to EST and VCC pins.  
VCC  
--  
24 3/5 V Power Supply.  
Abbreviation Index  
CAS ----------------------------------------------------------- CPE Alerting Signal  
CDS ----------------------------------------------------------- Caller Display Service  
CID ------------------------------------------------------------ Calling Identity Delivery  
CIDCW ------------------------------------------------------- Calling Identity Delivery on Call Waiting  
CLIP ---------------------------------------------------------- Calling Line Identity Presentation  
CNAM -------------------------------------------------------- Calling Name Delivery  
CND ---------------------------------------------------------- Calling Number Delivery  
CNIC --------------------------------------------------------- Calling Number Identification Circuit  
CO ------------------------------------------------------------- Central Office  
CTI ----------------------------------------------------------- Computer Telephony Integration  
TE -------------------------------------------------------------- Terminal Equipment  
3
NW6003 TYPE II CALLER ID DECODER  
INDUSTRIAL TEMPERATURE RANGE  
BLOCK DESCRIPTION  
FUNCTIONAL DESCRIPTION  
The NW6003 requires a 3.579545 MHz system clock and consists  
of four major functional blocks: Analog Input Circuit, CLIP/CID Call  
Arrival Detection, Dual Tone Alert Signal Dectection, and FSK  
Demodulation.  
CALLER ID SPECS SUPPORTED  
The NW6003 is a type II Caller ID device with Call Waiting  
capability. It supports Bellcore, BT and CCA specifications. The major  
differences between above specs are as follows (refer to Figure 13, ANALOG INPUT CIRCUIT  
Figure 14, Figure 15, Figure 16 and Figure 17):  
The input signal is processed by the Analog Input Circuit block,  
BELLCORE  
which is comprised of an operational amplifier and a bias source  
(VREF). VREF is the output of a low impedance voltage source used  
to bias the input op amp, and is typically equal to VCC/2. The gain  
adjustable op amp is also used to select the input gain by connecting  
a feedback resistor between GS and the IN- pin. Figure 3 shows the  
necessary connections with the A/B line inputs. In single-ended  
configuration, the gain adjustable op amp is connected as shown in  
Figure 4.  
Bellcore GR-30-CORE and SR-TSV-002476 define the  
requirement for the signaling services of Calling Number Delivery  
(CND), Calling Name Delivery (CNAM) and Calling Identity Delivery  
on Call Waiting (CIDCW).  
In CND or CNAM service, information of the calling party is  
embedded in the silent interval between the first and second ringings.  
The NW6003 can detect the first ringing and then demodulate the  
incoming Bell-202 FSK data. In CIDCW service, information about an  
incoming caller is sent to the subscriber who is engaged in another  
call. A CPE Alerting Signal (CAS) indicates that a CIDCW data is  
incoming. The NW6003 can detect the alerting signal and demodulate  
the incoming FSK information which contains CIDCW data. The  
demodulated data is output onto the serial interface.  
VREF  
NW6003  
R3  
R4  
C1  
C2  
R1  
R2  
IN+  
IN-  
A
B
BRITISH TELECOM  
R5  
GS  
BT SIN227 and SIN242 define the signal interface between the  
Central Office (CO) and the Terminal Equipment (TE) for the Caller  
Display Service (CDS). CDS provides CLIP (Calling Line Identity  
Presentation) that delivers to an idle state (on hook) TE the identity of  
an incoming caller before the first ring.  
Voltage Gain  
Av = R5/R1  
Differential Input Amplifier  
C1=C2  
Input Impedance  
Zin =2ÖR1²+ (1/wC)²  
R1=R2 (For unity gain R5=R2)  
R3=(R4R5)/(R4+R5)  
A polarity reversal on the A and B wires (see Figure 6) indicates the  
arrival of a CDS call. After that comes an Idle State Tone Alert Signal,  
and then Caller ID FSK information transmitted in ITU-T V.23 format.  
When the subscriber is engaged in a call, the arrival of information  
about another incoming call is indicated by a Loop State Tone Alert  
Signal. The NW6003 can detect the line reversal and tone alert  
signal, it can also demodulate the incoming ITU-T V.23 FSK signals.  
Figure 3. Differential Input Gain Control Circuit  
NW6003  
IN+  
Rin  
C
IN-  
Input  
CABLE COMMUNICATION ASSOCIATION  
Rf  
GS  
The CCA caller identity specification TW/P&E/312 defines a  
different CDS TE interface. In this specificaiton, data is transmitted  
after a single burst of ringing rather than before the first ringing cycle,  
as specified in the BT. The Idle State Tone Alert Signal is not required  
in this case. The CCA specifies that data can be transmitted in either  
Bell-202 or ITU-T V.23 format. The NW6003 can detect the ring burst,  
and then demodulate either of the FSK format.  
Voltage Gain  
Av = Rf / Rin  
VREF  
Figure 4. Single-ended Input Gain Control Circuit  
4
NW6003 TYPE II CALLER ID DECODER  
INDUSTRIAL TEMPERATURE RANGE  
CLIP/CID CALL ARRIVAL DETECTION  
Figure 6 shows the typical application circuit to detect the CLIP/CID  
call arrival signals. The diode bridge works for both single ended and  
balanced ring signals. R1 and R2 are used to set the maximum  
loading and must be of some value to achieve balanced loading. The  
ring signal is attenuated by R1, R3 and R4 resistor devider before  
being applied to pin TRIGIN. The attenuation value is determined by  
the detection of minimal ring voltage and maximum noise tolerance  
between Ring/Tip and ground.  
Ring Signal  
VT+  
VT-  
TRIGIN  
VT+  
TRIGRC  
When no signal is applied to telephone line, TRIGIN will be at  
ground and pin TRIGOUT will stay inactive high. If TRIGIN increases  
from ground to VT+ (Schmitt trigger high going threshold voltage), C3  
gets discharged, TRIGRC becomes low and TRIGOUT is asserted.  
The low going TRIGOUT can be used to interrupt or wake up the  
microcontroller. When TRIGIN signal drops below VT- (Schmitt trigger  
low going threshold voltage), C3 will start to charge up through R5C3  
time constant. After TRIGRC pin reaches above the threshhold voltage  
(VT+), TRIGOUT becomes inactive high and it stops to interrupt the  
microcontroller. To ensure the minimum TRIGOUT low interval and to  
filter the ring signal to get a smooth envelope output, the RC time  
constant should be greater than the maximum cycle time of the Ring  
Signal.  
TRIGOUT  
Figure 5. TRIGIN, TRIGRC and TRIGOUT Operation  
Line Reversal Detection for BT: British Telecom uses the line  
polarity reverse (+15 V to -15V between the two lines slewing in 30  
ms) to indicate the arrival of an incoming CDS call. When line reverse  
occurs, TRIGIN increases over VT+ and TRIGOUT signal becomes  
active low. When reversal is over, TRIGIN falls below VT- and  
TRIGOUT returns inactive high.  
Ring Detection for Bellcore: Bellcore recommends that the CID  
FSK data be transmitted between first and second ringings. The circuit  
in Figure 6 will generate a ring envelope signal at pin TRIGOUT for  
the ring voltage of 40 Vrms or greater. R5 and C3 are used to filter the  
ring signal to provide the envelope output.  
Ring Burst Detection for CCA: The CCA requires the TE to  
detect a single burst of ringing followed by the FSK data. The ring  
pulse may varies from 30 to 75 Vrms with pulse duration 200 - 450  
ms.  
Note:  
C1= 0.1 mF  
R1 = 500K  
Minimal triggerable ring voltage (peak to  
Tip/A  
NW6003  
peak) is:  
Vpp(max ring)=  
2(VT+(max)(R1+R3+R4)/R4+0.7)  
R3 = 200K  
TRIGIN  
R4 = 300K  
Tolerance to noise between Tip/Ring and Vss  
is:  
Vmax noise=  
C2= 0.1 mF  
R2 = 500K  
R5 = 330K  
Ring/B  
TRIGRC  
VT+(min)(R1+R3+R4)/R4+0.7  
N
C3 = 0.22 mF  
Suggested RC component value:  
10K W < R5 < 500K W.  
47 nF < C3 < 0.68 mF  
Time constant is:  
T=R5×C3×In(VCC/(VCC-VT+))  
VT+(min) = 0.7 VCC  
VT+(max) = 0.5 VCC  
TRIGOUT  
ToMicrocontroller  
Figure 6. CLIP/CID Call Arrival Detection Circuit  
5
NW6003 TYPE II CALLER ID DECODER  
INDUSTRIAL TEMPERATURE RANGE  
DUAL TONE ALERT SIGNAL DETECTION  
Figure 7 shows the operation of the guard time circuit and Figure 8  
shows the waveform of the EST, ST/GT and STD pins. The total  
recognition time is tREC = tDP + tGP, where tDP is the tone present detection  
time and tGP is the tone present guard time. The total absent time is tABS  
= tDA + tGA, where tDA is the tone absent detection time and tGA is the tone  
absent guard time. The guard time is the RC time constant for the  
capacitor charge to VCC or discharge to GND. To get the unequal  
present and absent guard time, a diode can be connected as shown  
in Figure 9 to provide different RC time constant (varying resistance  
value) during charging and discharging.  
BT specifies a Dual Tone Alert Signal in both idle (on-hook) state  
and loop (off-hook) state, while Bellcore specifies a similar Dual Tone  
Alert Signal called CPE Alerting Signal (CAS) in off-hook state. The  
low and high tone frequencies of two different systems are as follows:  
BT  
Bellcore  
Low Tone Frequency  
High Tone Frequency  
2130 Hz ± 1.1%  
2750 Hz ± 1.1%  
2130 Hz ± 0.5%  
2750 Hz ± 0.5%  
VCC  
The incoming Alert Signal goes through anti-alias filter and then is  
separated into high band and low band by two bandpass filters. The  
tone detection algorithm examines the filter outputs to validate the  
arrival of the Dual Tone Alert Signal. The EST pin becomes active  
when both tones are detected. The EST is only the preliminary  
indication, it must be qualified by the “guard time” as required by  
Bellcore and BT (a minimum duration for valid signals). STD is the  
guard time qualified CAS/Dual Tone Alert Signal detection output, it  
indicates the correct detection.  
tGP < tGA  
C
tGP=RPCIn((VCC-Vd(RP/R2))/  
ST/GT  
EST  
(VCC-VTGT-Vd(RP/R2)))  
tGA=R1CIn(VCC/VTGT)  
RP=R1R2/(R1+R2)  
R 1  
R 2  
Vd=diode forward voltage  
VCC  
tGP > tGA  
C
tGP=R1CIn(VCC/(VCC-VTGT))  
tGA=RPCIn((VCC-Vd(RP/R2))/  
(VTGT-Vd(RP/R2)))  
RP=R1R2/(R1+R2)  
Vd=diode forward voltage  
ST/GT  
VCC  
VCC  
Q1  
NW6003  
R 1  
R 2  
Dual tone detected  
EST  
P
+
-
ST/GT  
VTGT  
Figure 9. Guard Time Circuits with Unequal Present  
and Absent Times  
Comparator  
Q2  
N
EST  
STD  
Figure 7. Guard Time Circuit of Dual Tone Alert Signal Detection  
Tip/  
Ring  
Alerting Signal  
tDP  
tDA  
EST  
ST/GT  
STD  
tGP  
tGA  
VTGT  
VTGT  
tABS  
tREC  
Q1  
ON  
Switch  
Q2  
Switch  
ON  
ON  
Figure 8. Guard Time Waveform  
6
NW6003 TYPE II CALLER ID DECODER  
INDUSTRIAL TEMPERATURE RANGE  
FSK DEMODULATION  
Mode ‘0’  
In this mode, data transfer is initiated by the NW6003. The device  
demodulates the incoming FSK signal, and output the data directly to  
the DATA pin. Figure 24 shows the timing diagram of Mode ‘0’  
operation.  
The key part among the functions offered by NW6003 is FSK  
demodulation. This function is implemented by several stages: first,  
the carrier detector provides an indication of the presence of signal at  
the bandpass filter output; second, the device’s dual mode serial  
interface allows convenient extraction of the 8-bit data words in the  
demodulated FSK bit stream.  
Mode ‘1’  
In this mode, the microcontroller supplies read pulses (DCLK) to  
shift the 8-bit data words out of the NW6003, onto the DATA pin. The  
NW6003 asserts DR to denote the word boundary and indicate to the  
microprocessor that a new word has become available. Internal to the  
device, the demodulated data bits are sampled and stored. After the  
8th bit, the word is parallelly loaded into an 8-bit shift register and DR  
goes low. The contents of shift register are shifted out to DATA pin on  
DCLK’s rising edge with LSB (Least Significant Bit) out first. If DCLK  
begins while DR is low, DR will return to high upon the first DCLK. This  
feature allows the associated interrupt to be cleared by the first read  
pulse. Otherwise, DR stays low for half a nominal bit time (1/2400 sec)  
and then returns to high. After the last bit (Most Significant Bit) has  
been read, additional DCLKs are ignored. Figure 22 shows the timing  
diagram of Mode ‘1’ operation.  
The FSK characteristics are different in BT and Bellcore  
specifications. The BT’s signal frequencies correspond to ITU-T V.23;  
the Bellcore frequencies correspond to Bell 202. The CCA requires  
that TE be able to receive both ITU-T V.23 and Bell 202 signals. The  
NW6003 is compatible with both formats. It also meets the signal  
characteristics by setting the input op amp at unity gain in 5 V  
operation.  
ITU-T V.23  
Bell 202  
Mark Freq. (‘1’)  
Space Freq. (‘0’)  
1300 Hz ± 1.5%  
2100 Hz ± 1.5%  
1200 Hz ± 1%  
2200 Hz ± 1%  
The Dual Tone Alert Signal, speech and DTMF tones are in the  
same frequency band as FSK, they will be demodulated and generate  
false data. To avoid it, FSKEN pin is used to disable the FSK  
modulation when FSK signal is not expected.  
FSK CARRIER DETECTION  
The carrier detector provides an indication of the presence of a  
signal in the FSK frequency band. It detects the presence of a signal  
of sufficient amplitude at the output of the FSK bandpass filter. If the  
signal is qualified by a digital algorithm, the CD output becomes low to  
indicate carrier detection. An 8 ms hysteresis is provided to allow for  
momentary signal drop out once CD has been activated. And when  
there is no activity at the FSK bandpass filter output for 8 ms, CD is  
released.  
When CD is inactive (high), the raw output of the FSK  
demodulator is ignored by the FSK data output interface. In mode ‘0’,  
the DATA pin is forced high. In mode ‘1’, the internal shift register is  
not updated. No DR is generated. If DCLK is clocked, DATA is  
undefined.  
SERIAL FSK INTERFACE  
The three wire DATA, DCLK and DR form the data interface of the  
FSK demodulation. The DATA pin is the serial data pin that outputs  
data to external devices. The DCLK pin is the data clock which is  
generated by an external device. The DR pin is the data ready signal,  
also an output from the NW6003 to external devices. This interface  
provides the mechanism to extract the 8-bit data words in the  
demodulated FSK bit stream. Two modes are selectable via control of  
the device’s MODE pin: Mode ‘0’ (MODE pin is low), where data  
transfer is initiated by the NW6003; Mode ‘1’ (MODE pin is high),  
where the data transfer is initiated by an external microcontroller.  
7
NW6003 TYPE II CALLER ID DECODER  
INDUSTRIAL TEMPERATURE RANGE  
When the system is first powered up, TRIGOUT will be low (C3 at  
TRIGRC has no initial charge) and STD will be high if PWDN is low  
(no charge across the capacitor at ST/GT pin in Figure 7), interrupt  
signal will be generated. The microcontroller should ignore interrupts  
OTHER FUNCTIONS  
POWER-DOWN MODE  
The device provides the power down feature to reduce the power from these sources on the initial power up until there is sufficient time  
consumption. By activating the PWDN pin (high), the gain adjustable to charge the capacitors. Also, by asserting PWDN high immediately  
op amp, oscillator and all other internal circuits besides the ring after system power up, STD will become low and no interrupt will be  
detection circuit are all disabled. The TRIGIN, TRIGRC and TRIGOUT generated. In power-down mode, EST and comparator output are  
pins are not affected, the device can still react to call arrival indicator forced low, the charging switch will turn on, and the capacitor at ST/GT  
and activate the interrupt to wake up the microcontroller.  
pin will charge up more rapidly.  
CRYSTAL OSCILLATOR  
BIAS VOLTAGE GENERATOR  
A 3.579545 MHz crystal oscillator or other external clock source is  
The bias voltage generator provides a low impedance voltage  
required for NW6003. The crystal can be directly connected between source equal to VCC/2 on pin VREF and is used to bias the op amp.  
OSCIN and OSCOUT pins without any external component. If an To reduce the noise, a 0.1 mF capacitor should be connected between  
external clock source is used, OSCIN pin should be driven by the CAP and GND pins.  
clock source and OSCOUT pin is left floating or is used to drive other  
devices. Figure 10 shows some applications.  
(a) Connection of One Device with Crystal Oscillator  
NW6003  
OSCIN  
OSCOUT  
3.579545MHz  
(b) Common Crystal Connection of Several Devices Sharing  
One Timing Source  
NW6003  
OSCIN  
NW6003  
OSCIN  
NW6003  
OSCIN  
OSCOUT  
OSCOUT  
OSCOUT  
to the next device  
3.579545MHz  
Figure 10. Applicaiton of Clock Driven Circuit  
INTERRUPT  
The NW6003 provides an open drain interrupt output INT to  
interrupt the microcontroller. Either TRIGOUT low, STD high or DR low  
will activate the INT and it will remain active ‘low’ until all of these three  
pins return to an inactive state. The microcontroller should read these  
pins through input ports to detect the interrupt type (TRIGOUT, STD or  
DR) and to make the correspondent response.  
8
NW6003 TYPE II CALLER ID DECODER  
INDUSTRIAL TEMPERATURE RANGE  
APPLICATION INFORMATION  
1.0  
APPLICATION CIRCUITS  
0.9  
0.8  
Figure 11 shows the typical NW6003 application circuit. For 5 V  
operation, the gain ratio of the op amp is set to unity to optimize the  
electrical characteristics. As the power supply voltage drops, the  
threshold of tone and FSK detectors will be lower. To meet the BT and  
Bellcore tone reject level requirements, the gain of the op amp should  
be adjusted according to the graph in Figure 12.  
0.7  
0.678  
0.6  
0.5  
It should be noted that the glitch with sufficient amplitude appears  
on the tip and ring interface will be falsely detected. One way to avoid  
such false detection is to use the photo-coupler LED between the  
diode bridge and TRIGIN pin.  
3
4
5
6
2
7
Nominal VCC(Volts)  
BELLCORE/BT/CCAAPPLICATIONS  
464kW  
The NW6003 supports three specifications: Bellcore, BT and CCA.  
Figure 13 shows the timing diagram of Bellcore on-hook data  
transmission, and Figure 14 shows Bellcore off-hook data  
transmission. The BT operations are shown in Figure 15 and Figure  
16, and the CCA operation in Figure 17.  
Gain Ratio of op amp =  
R1 + R4  
Figure 12. Gain Ratio as a Function of Nominal VCC  
VCC  
VCC  
22 nF 5%  
R1 1%  
R4 1%  
Tip/A  
NW6003  
0.1mF  
C
VCC  
ST/GT  
EST  
IN+  
VCC  
VCC  
IN-  
464K 1%  
60K4  
1%  
22 nF 5%  
R1' 1%  
R4' 1%  
GS  
Ring/B  
100K  
R3 R2  
53K6  
1%  
VREF  
CAP  
STD  
0.1 mF  
INT  
CD  
DR  
VCC  
TRIGIN  
VCC  
0.1  
0.1  
mF 5%  
500K  
330K  
TRIGRC  
200K  
DATA  
TRIGOUT  
MODE  
DCLK  
0.22  
mF  
300K  
mF 5%  
500K  
FSKEN  
OSCIN  
OSCOUT  
GND  
PWDN  
TM  
¨
¨
¨
For VCC = 5V ±10%, R1 = R1’ = 430 kW, R4 = R4’ = 34 kW.  
For VCC = 3V ±10%, R1 = R1’ = 620 kW, R4 = R4’ = 63 k4.  
Resistor tolerance 5% and capacitor tolerance 10% unless  
otherwise specified.  
¨
¨
¨
Crystal frequency 3.579545 MHz with 0.1%tolerance.  
For BT application, C = 0.1 mF ±5%, R2 = R3 = 422K ±1%.  
For Bellcore application, C = 0.1 mF ±5%, R2 = 266K ±1%,  
R3= 825K ±1%.  
Figure 11. Typical Application Circuit  
9
NW6003 TYPE II CALLER ID DECODER  
INDUSTRIAL TEMPERATURE RANGE  
1st Ringing  
Ch. Seizure  
Mark  
Message  
2nd Ringing  
A/B Wires  
A
Note 1  
B
C
D
E
F
TRIGOUT  
INT  
...  
...  
Note 4  
Note 2  
PWDN  
Note 2  
Note 5  
Note 3  
FSKEN  
CD  
DR  
...  
...  
DCLK  
DATA  
..101010..  
Data  
Figure 13. Bellcore On-hook Data Transmission Timing Diagram  
Notes:  
1) A= 2 sec typ., B= 250 - 500 ms, C= 250 ms, D= 150ms, E depends on data length, Max C+D+E = 2.9 - 3.7 sec, F ³ 200 ms.  
2) In a battery operated CPE, NW6003 may be enabled only after the end of ringing to conserve power.  
3) The microcontroller in the CPE powers down the NW6003 after CD goes inactive.  
4) The microcontroller times out if CD is not activated on the 2nd ring and puts the device into Power-down mode.  
5) FSKEN may be set always high while the CPE is on-hook. To prevent the FSK demodulator from reacting to other inband signals such as speech, CAS or DTMT tones. The designer may choose  
to set FSKEN low during the period that FSK signal is not expected.  
10  
NW6003 TYPE II CALLER ID DECODER  
INDUSTRIAL TEMPERATURE RANGE  
CPE mutes handset and  
disable keypad  
CPE unmutes handset and  
enable keypad  
CPE off-hook  
CPE sends  
ACK  
Note 2  
CAS  
Mark  
Message  
A/B wires  
Note 1  
A
B
C
D
E
F
G
Note 3  
PWDN  
Note 5  
Note 4  
Note 6  
FSKEN  
STD  
INT  
...  
CD  
DR  
...  
DCLK  
DATA  
Data  
Figure 14. Bellcore Off-hook Data Transmission Timing Diagram  
Notes:  
1) A= 75 - 85 ms, B= 0 -100 ms, C= 55 - 65 ms, D= 0 - 500 ms, E= 58 - 75ms, F depends on data length, G£ 50 ms.  
2) If AC power is not available, the designer may use the line power when the CPE goes off-hook and use battery power while on-hook. The CPE should also be CID (on-hook) capable .  
3) If the end office fails to send the FSK signal, the CPE should disable FSKEN to unmute the handset and enable the keypad after this interval.  
4) When FSK signal is not expected, the FSKEN pin should be set low to disable the FSK demodulator.  
5) FSKEN should be high as soon as the CPE has finished sending the acknowledgement signal ACK.  
6) FSKEN should be low when CD become inactive.  
11  
NW6003 TYPE II CALLER ID DECODER  
INDUSTRIAL TEMPERATURE RANGE  
Line Reversal  
Alerting  
Signal  
Ch. Seizure  
Mark  
Message  
Ring  
A/B Wires  
A
B
C
D
E
F
G
Note 1  
TRIGOUT  
INT  
...  
...  
PWDN  
STD  
15 ±1 ms  
Current Wetting Pulse  
50 - 150 ms  
<120 m A  
< 0.5 mA (optional)  
TE DC load  
TE AC load  
20 ±5 ms  
Note 2  
Note 3  
Zss  
Note 4  
FSKEN  
CD  
DR  
...  
...  
DCLK  
DATA  
..101010..  
Data  
Figure 15. BT Idle State (on-hook) Data Transmission Timing Diagram  
Notes:  
1) A³ 100ms, B=88 - 110 ms, C³ 45 ms (up to 5 sec), D= 80 -262 ms, E= 45 - 75 ms, F£ 2.5 sec (typ. 500 ms), G³ 200 ms.  
2) By choosing tGA=15 ms, tABS will be 15-25 ms (refer to Figure 8). Current wetting pulse and AC/DC load should be applied right after the STD falling edge.  
3) AC and DC loads should be removed between 50-150 ms after the end of the FSK signal. The NW6003 may go to power down mode to save power.  
4) FSKEN should be set low to disable the FSK demodulator, when the FSK signal is not expected.  
12  
NW6003 TYPE II CALLER ID DECODER  
INDUSTRIAL TEMPERATURE RANGE  
TE in loop state (off-hook)  
Speech path disabled  
ACK  
Speech path restored  
Start Point  
Note 2  
Alert Signal  
Mark  
Message  
A/B wires  
A
B
C
D
E
F
G
H
Note 1  
Note 3  
PWDN  
Note 5  
Note 4  
Note 6  
FSKEN  
STD  
INT  
...  
CD  
DR  
...  
DCLK  
DATA  
Data  
Figure 16. BT Loop State (Off-hook) Data Transmission Timing Diagram  
Notes:  
1) A= 40 - 50 ms, B= 80 - 85 ms, C£ 100 ms, D= 65 - 75 ms, E= 5- 100ms, F = 45 - 75 ms, G depends on data length, H £ 100 ms.  
2) If AC power is not available, the designer may use the line power when the TE goes into loop state (off-hook) and use battery power while on-hook.  
3) If the end office fails to send the FSK signal, the TE should disable FSKEN to unmute the handset and enable the keypad after this interval.  
4) When FSK signal is not expected, the FSKEN pin should be set low to disable the FSK demodulator.  
5) FSKEN should be high as soon as the TE has finished sending the acknowledgement signal ACK.  
6) FSKEN should be low when CD become inactive.  
13  
NW6003 TYPE II CALLER ID DECODER  
INDUSTRIAL TEMPERATURE RANGE  
1st Ring  
Ring Burst  
Ch. Seizure  
Mark  
Data Packet  
A/B Wires  
TRIGOUT  
INT  
A
B
C
D
E
Note 1  
F
Note 2  
Note 2  
PWDN  
50 - 150 ms  
250 - 400 ms  
TE DC load  
TE AC load  
Note 3  
Note 4  
£ 25 ms  
FSKEN  
8 ms  
CD  
DR  
...  
...  
DCLK  
DATA  
..100110..  
Data  
Figure 17. CCA Caller Display Service Timing Diagram  
Notes:  
1) A = 200 - 450 ms, B ³ 500 ms, C= 80 - 262 ms, D= 45 -262 ms, E£ 2.5 s (typ. 500 ms), F ³ 200 ms.  
2) TRIGOUT indicates the ring envelope.  
3) AC and DC loads should be applied between 250 - 400 ms after the ring burst and should be removed between 50 to 150 ms after the end of FSK signal.  
4) FSKEN should be set low when FSK signal is not expected.  
14  
NW6003 TYPE II CALLER ID DECODER  
INDUSTRIAL TEMPERATURE RANGE  
MAXIMUM RATING - Exceeding the following listed values may cause permament damage.  
Power Supply Voltage: -0.3 V to 7 V  
Voltage on any pin other than supplies: GND - 0.3 V to VCC + 1 V  
Current at any pin other than supplies: £ 20 mA  
Storage Temperature: -65 °C to +150 °C  
RECOMMENDED OPERATING CONDITIONS  
Operating Temperature: -40 °C to +85 °C  
Power Supply Voltage: 3 V ± 10% or 5 V ± 10%  
Clock Frequency: 3.579545 MHz ± 0.1%  
Input Voltage: 0 V to VCC  
CRYSTAL SPECIFICATIONS  
Frequency: 3.579545 MHz  
Resonancy tolerance: ± 0.1%( -40°C to +85°C)  
Resonance mode: Parallel  
Load capacitance: 18 pF  
Maximum series resistance: 150 W  
Maximum drive level(mW): 2 mW  
DC ELECTRICAL CHARACTERISTICS  
Test  
Conditions  
Parameter  
ICCS  
Pin  
Description  
Min  
Typ  
Max  
Units  
Power Supply Standby  
Current  
Operating Supply  
Current  
0.5  
10  
m
A
Test 1  
Test 2  
ICC  
VCC  
±
VCC = 5 V 10%  
2.5  
1.8  
3.8  
2.7  
mA  
mA  
±
VCC = 3 V 10%  
Schmitt Trigger Input  
High Threshold  
Schmitt Trigger Input  
Low Threshold  
Schmitt Hysteresis  
CMOS Input High  
Voltage  
VT+  
0.5VCC  
0.7VCC  
0.5VCC  
V
TRIGIN  
TRIGRC  
PWDN  
VT-  
VHYS  
VIH  
0.3VCC  
0.2  
V
V
V
DCLK  
MODE  
0.7VCC  
VCC  
CMOS Input Low  
Voltage  
VIL  
FSKEN  
GND  
-0.8  
0.3VCC  
V
TRIGOUT  
, DCLK, DATA,  
Output High Sourcing  
Current  
DR CD  
IOH  
mA  
VOH=0.9VCC  
,
, STD, EST,  
ST/GT  
Test 1: All inputs are VCC/GND except for oscillator pins. No analog input. Output unloaded. PWDN = VCC.  
Test 2: All inputs are VCC/GND except for oscillator pins. No analog input. Ouput unloaded. PWDN = GND, FEKEN = VCC.  
15  
NW6003 TYPE II CALLER ID DECODER  
INDUSTRIAL TEMPERATURE RANGE  
DC ELECTRICAL CHARACTERISTICS (CONTINUED)  
Parameter  
Pin  
Description  
Min  
Typ  
Max  
Units  
Test Conditions  
TRIGOUT  
, DCLK, DATA,  
, STD, EST,  
Output Low Sinking  
Current  
DR CD  
mA  
IOL  
,
2
VOL = 0.1VCC  
TRIGRC INT  
ST/GT,  
,
Iin1  
Iin2  
IN+, IN-, TRIGIN  
PWDN, DCLK  
MODE, FSKEN  
Input Current  
Input Current  
1
mA  
mA  
10  
Vin = VCC to GND  
TRIGRC  
A
m
IOZ1  
Output High Impedance  
Current  
1
IOZ2  
IOZ3  
ST/GT  
5
mA  
mA  
Vout = VCC to GND  
No Load  
INT  
10  
0.5VCC-  
0.05  
0.5VCC+  
0.05  
V
kW  
V
VREF  
RREF  
VTGT  
VREF  
Output Voltage  
Output Resistance  
Comparator Threshold  
Voltage  
2
0.5VCC-  
0.05  
0.5VCC+  
0.05  
ST/GT  
AC ELECTRICAL CHARACTERISTICS  
DUAL TONE ALERT SIGNAL DETECTION  
Parameter  
Description  
Low Tone Frequency  
High Tone Frequency  
Min  
Typ  
2130  
2750  
Max  
Units  
Hz  
Hz  
Notes  
FL  
FH  
Nominal frequency  
Nominal frequency  
Within this range, tones are  
accepted.  
Outside this range, tones are  
rejected.  
FDA  
FDR  
Frequency Deviation Accept  
Frequency Deviation Reject  
Accept Signal Level per tone  
Reject Signal Level per tone  
1.1%  
3.5%  
-40  
-37.78  
-2  
0.22  
-46  
-43.78  
7
dBV  
dBm  
dBV  
dBm  
The gain setting as in Figure 3.  
Production tested at 3 V 10%,  
SIGAC  
SIGRJ  
TA  
±
±
or 5 V 10%.  
Positive and Negative Twist  
Accept #  
dB  
Both tones have the same  
amplitude and at nominal  
SNR  
Signal to Noise Ratio  
20  
dB  
frequencies. Band limited random  
noise 300-3400 Hz. Measurement  
valid only when tone is present.  
# Twist = 20 log ( fH amplitude / f amplitude ).  
L
16  
NW6003 TYPE II CALLER ID DECODER  
INDUSTRIAL TEMPERATURE RANGE  
AC ELECTRICAL CHARACTERISTICS (CONTINUED)  
GAIN ADJUSTABLE OP AMP  
Parameter  
IIN  
Description  
Input Leakage Current  
Min  
Typ  
Max  
0.8  
Units  
mA  
Test Conditions  
£
£
GND VIN VCC  
RIN  
Input Resistance  
15  
W
M
VOS  
Input Offset Voltage  
25  
mV  
dB  
dB  
dB  
MHz  
V
PSRR  
CMRR  
AVOL  
fC  
VO  
CL  
Power Supply Rejection Ratio  
Common Mode Rejection  
DC Open Loop Voltage Gain  
Unity Gain Bandwidth  
45  
40  
40  
0.3  
0.4  
1kHz ripple on VCC  
£
£
VCMmin VIN VCMmax  
Output Voltage Swing  
VCC -0.4  
100  
³
W
Load 50 k  
Maximum Capacitive Load (GS)  
Maximum Resistive Load (GS)  
Common Mode Range Voltage  
pF  
kW  
RL  
VCM  
50  
1.0  
VCC-1.0  
FSK DETECTION  
Parameter  
Description  
Min  
Typ  
Max  
-8  
-5.78  
398.1  
Units  
dBV  
dBm  
Notes  
Production tested at VCC =3V 10%,  
±
-40  
-37.78  
10.0  
ID  
±
Input Detection Level  
or 5V 10%. Both mark and space  
mVrms  
have the same amplitude.  
TR  
Transmission Rate  
Input Frequency Detection  
Bell 202 ‘1’ (mark)  
1188  
1200  
1200  
1212  
baud  
FMARK  
1188  
1212  
Hz  
Input Frequency Detection  
Bell 202 ‘0’ (space)  
Input Frequency Detection  
ITU-T V.23 ‘1’ (mark)  
Input Frequency Detection  
ITU-T V.23 0 (space)  
Positive and Negative Twist Accept *  
FSPACE  
FMARK  
2178  
2200  
1300  
2100  
2222  
Hz  
Hz  
1280.5  
1319.5  
FSPACE  
TA  
2068.5  
-10  
2131.5  
10  
Hz  
dB  
Both mark and space have the same  
amplitude and at nominal frequencies.  
Band limited random noise: 200-3400  
Hz. Present only when FSK signal is  
present. #  
SNR  
Signal to Noise Ratio  
20  
dB  
* Twist = 20 log ( fH amplitude / f amplitude ).  
L
# BT band is 200-3400 Hz, while Bellcore band is 0-4 kHz.  
Notes:  
dBV = decibels above or below a reference voltage of 1 Vrms.  
dBm = decibels above or below a reference power of 1 mW into 600 ohms, 0 dBm = 0.7746 Vrms.  
17  
NW6003 TYPE II CALLER ID DECODER  
INDUSTRIAL TEMPERATURE RANGE  
AC TIMING CHARACTERISTICS  
POWER UP/DOWN AND FSK DETECTION  
Parameter  
Description  
Power Up Time  
Power Down Time  
Min  
Typ  
Max  
50  
1
Units  
ms  
ms  
Test Conditions  
t1  
t2  
t3  
t4  
25  
ms  
CD  
CD  
Input FSK to  
Input FSK to  
Hysteresis  
low delay  
high delay  
8
8
ms  
ms  
t5  
DUAL TONE ALERT SIGNAL  
Parameter  
Description  
Min  
0.5  
0.1  
Typ  
Max  
10  
8
Units  
ms  
ms  
Test Conditions  
t6  
t7  
Alert Signal Present Detect Time  
Alert Signal Absent Detect Time  
PWDN  
OSCOUT  
t1  
t2  
Figure 18. Power Up/Down Timing  
Tip/Ring  
FSK Signal  
CD  
t3  
t4  
Figure 19. FSK Detection Time  
Tip/Ring  
Alert Signal  
EST  
t6  
t7  
Figure 20. Dual Tone Alert Signal Detection Time  
18  
NW6003 TYPE II CALLER ID DECODER  
INDUSTRIAL TEMPERATURE RANGE  
AC TIMING CHARACTERISTICS (CONTINUED)  
SERIAL INTERFACE (MODE ‘1’)  
Parameter  
t11  
Description  
DCLK Cycle Time  
Min  
1
Typ  
Max  
Units  
m
s
Test Conditions  
t12  
t13  
t14  
t15  
t16  
t17  
m
s
m
s
ns  
ns  
ns  
DCLK High Time  
DCLK Low Time  
DCLK Rise Time  
DCLK Fall Time  
0.3  
0.3  
20  
20  
500  
500  
DR  
DCLK Low Setup to  
DCLK Low Hold Time after  
ns  
DR  
t13  
t12  
DCLK  
t14  
t15  
t11  
Figure 21. DCLK Timing in Mode ‘1’  
Nth byte  
b7  
(N+1)th byte  
Internal  
Demodulated Bit  
Stream  
start  
b0  
b1  
b2  
b3  
b4  
b5  
b6  
b7  
stop  
start  
stop  
Note 1  
Note 2  
DR  
t16  
t17  
DCLK  
DATA  
b1 b2 b3  
b5  
b6  
(N-1)th byte  
b7  
b0  
b4  
b6 b7  
b0  
Nth byte  
Figure 22. Serial Data Interface Timing in MODE ‘1’  
Notes:  
1. DCLK clears DR.  
2. DR not cleared by DCLK, low for a maximum time of 1/2 bit width.  
19  
NW6003 TYPE II CALLER ID DECODER  
INDUSTRIAL TEMPERATURE RANGE  
SERIAL INTERFACE (MODE ‘0’)  
Parameter  
Description  
Min  
1188  
Typ  
1200  
1
Max  
1212  
5
200  
200  
Units  
baud  
ms  
ns  
ns  
Test Conditions  
R
D
Data Rate  
1
t21  
t22  
t23  
Input FSK to DATA Delay  
DATA Rise Time  
DATA Fall Time  
2
2
Test conditions:  
1. FSK input data at 1200 ± 12 buad.  
2. Load of 50 pF.  
DATA  
t22  
t23  
Figure 23. DATA Output Timing in Mode ‘0’  
Nth byte  
(N+1)th byte  
start  
0
stop start  
stop start  
TIP/RING  
DATA  
b7  
1
b0 b1 b2 b3 b4 b5 b6 b7  
1
0
b0 b1 b2 b3 b4 b5 b6 b7  
1
0
b0 b1  
t21  
Nth byte  
start  
(N+1)th byte  
start  
start  
b7  
b0 b1 b2 b3 b4 b5 b6 b7  
b0 b1 b2 b3 b4 b5 b6 b7  
b0
stop  
stop  
Figure 24. Serial Data Interface Timing in MODE ‘0’  
20  
PHYSICAL DIMENSIONS in Millimeters  
Notes:  
1) All dimensions in inches  
2) Form radius MIN. .010 but not to exceed .030  
3) Lead tip coplanarityafter form to be within .004  
4) REF. JEDEC MS-13  
0.018 Typ.  
Typ.  
0.015 × 45 DEG  
0.016 Min.  
0.050 Max.  
0.604 ± 0.005  
Figure 25. NW6003-XS 24 Pin SOIC Package Diagram  
CORPORATE HEADQUARTERS  
2975 Stender Way  
Santa Clara, CA 95054  
for SALES:  
for Tech Support:  
408-330-1552  
email: telecomhelp@idt.com  
800-345-7015 or 408-727-6116  
fax: 408-492-8674  
www.idt.com  
21  
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