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5T9304EJI

型号：

5T9304EJI

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

17 页

PDF大小：

342 K

下载PDF手册
LVDS, 1:4 Clock Buffer Terabuffer™  
IDT5T9304I  
NRND  
DATA SHEET  
NRND – Not Recommend for New Designs  
General Description  
Features  
The IDT5T9304I differential clock buffer is a user-selectable  
differential input to four LVDS outputs. The fanout from a differential  
input to four LVDS outputs reduces loading on the preceding driver  
and provides an efficient clock distribution network. The IDT5T9304I  
can act as a translator from a differential HSTL, eHSTL, LVEPECL  
(2.5V), LVPECL (3.3V), CML, or LVDS input to LVDS outputs. A  
single-ended 3.3V / 2.5V LVTTL input can also be used to translate  
to LVDS outputs. The redundant input capability allows for an  
asynchronous change-over from a primary clock source to a  
secondary clock source. Selectable reference inputs are controlled  
by SEL.  
• Guaranteed low skew: 50ps (maximum)  
• Very low duty cycle distortion: 125ps (maximum)  
• Propagation delay: 1.9ns (maximum)  
• Up to 450MHz operation  
• Selectable inputs  
• Hot insertable and over-voltage tolerant inputs  
• 3.3V/2.5V LVTTL, HSTL eHSTL, LVEPECL (2.5V),  
LVPECL (3.3V), CML or LVDS input interface  
• Selectable differential inputs to four LVDS outputs  
• 2.5V VDD  
• -40°C to 85°C ambient operating temperature  
• Available in standard (RoHS 5) and lead-free (RoHS 6) packages  
• NOT RECOMMENDED FOR NEW DESIGNS  
The IDT5T9304I outputs can be asynchronously enabled/disabled.  
When disabled, the outputs will drive to the value selected by the GL  
pin. Multiple power and grounds reduce noise.  
Applications  
• Clock distribution  
Pin Assignment  
A2  
A2  
GND  
PD  
1
2
24  
23  
GND  
VDD  
RESERVED  
VDD  
3
4
22  
21  
5
6
7
8
20  
19  
18  
17  
Q3  
Q3  
Q4  
Q1  
Q1  
Q2  
Q4  
Q2  
VDD  
SEL  
G
VDD  
GL  
A1  
9
16  
15  
14  
13  
10  
11  
12  
GND  
A1  
IDT5T9304I  
24-Lead TSSOP, E-Pad  
4.40mm x 7.8mm x 0.925mm  
G Package  
Top View  
IDT5T9304I REVISION B MAY 15, 2013  
1
©2013 Integrated Device Technology, Inc.a  
IDT5T9304I Data Sheet  
2.5V LVDS, 1:4 CLOCK BUFFER TERABUFFER™  
Block Diagram  
GL  
G
Q1  
Q1  
OUTPUT  
CONTROL  
PD  
Q2  
Q2  
OUTPUT  
CONTROL  
A1  
A1  
1
0
Q3  
Q3  
OUTPUT  
CONTROL  
A2  
A2  
Q4  
Q4  
OUTPUT  
CONTROL  
SEL  
IDT5T9304I REVISION B MAY 15, 2013  
2
©2013 Integrated Device Technology, Inc.a  
IDT5T9304I Data Sheet  
2.5V LVDS, 1:4 CLOCK BUFFER TERABUFFER™  
Table 1. Pin Descriptions  
Number  
Name  
Type  
Description  
1, 12, 22  
GND  
Power  
LVTTL  
Power supply return for all power.  
Power-down control. Shuts off entire chip. If LOW, the device goes into low  
power mode. Inputs and outputs are disabled. Both Qx and Qx outputs will  
pull to VDD. Set HIGH for normal operation.(3)  
2
PD  
Input  
3
RESERVED  
VDD  
Reserved  
Reserved pin.  
4, 9, 16, 21  
Power  
LVDS  
Power supply for the device core and inputs.  
5, 7,  
18, 20  
Q1, Q2,  
Q4, Q3  
Output  
Output  
Input  
Complementary differential clock outputs.  
Differential clock outputs.  
6, 8,  
17, 19  
Q1, Q2,  
Q4, Q3  
LVDS  
Reference clock select. When LOW, selects A2 and A2. When HIGH,  
selects A1 and A1.  
10  
SEL  
LVTTL  
Gate control for differential outputs Q1 and Q1 through Q4 and Q4. When G  
is LOW, the differential outputs are active. When G is HIGH, the differential  
11  
G
Input  
Input  
LVTTL  
outputs are asynchronously driven to the level designated by GL(2)  
.
13, 24  
A1, A2  
Adjustable (1, 4) Clock input. A[1:2] is the "true" side of the differential clock input.  
Complementary clock inputs. A[1:2] is the complementary side of A[1:2].  
For LVTTL single-ended operation, A[1:2] should be set to the desired  
14, 23  
A1, A2  
GL  
Input  
Input  
Adjustable (1, 4) toggle voltage for A[1:2]:  
3.3V LVTTL VREF = 1650mV  
2.5V LVTTL VREF = 1250mV  
Specifies output disable level. If HIGH, Qx outputs disable HIGH and Qx  
outputs disable LOW. If LOW, Qx outputs disable LOW and Qx outputs  
disable HIGH.  
15  
LVTTL  
NOTES:  
1.  
Inputs are capable of translating the following interface standards:  
Single-ended 3.3V and 2.5V LVTTL levels  
Differential HSTL and eHSTL levels  
Differential LVEPECL (2.5V) and LVPECL (3.3V) levels  
Differential LVDS levels  
Differential CML levels  
2.  
3.  
4.  
Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control  
signals to minimize the possibility of runt pulses or be able to tolerate them in down stream circuitry.  
It is recommended that the outputs be disabled before entering power-down mode. It is also recommended that the outputs remain  
disabled until the device completes power-up after asserting PD.  
The user must take precautions with any differential input interface standard being used in order to prevent instability when there is  
no input signal.  
Table 2. Pin Characteristics (TA = +25°C, F = 1.0MHz)  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
CIN  
Input Capacitance  
3
pF  
NOTE: This parameter is measured at characterization but not tested.  
IDT5T9304I REVISION B MAY 15, 2013  
3
©2013 Integrated Device Technology, Inc.a  
IDT5T9304I Data Sheet  
2.5V LVDS, 1:4 CLOCK BUFFER TERABUFFER™  
Function Tables  
Table 3A. Gate Control Output Table  
Control Output  
Outputs  
GL  
0
G
0
1
0
1
Q[1:4]  
Toggling  
LOW  
Q[1:4]  
Toggling  
HIGH  
0
1
Toggling  
HIGH  
Toggling  
LOW  
1
Table 3B. Input Selection Table  
Selection SEL pin  
Inputs  
A2, A2  
A1, A1  
0
1
Absolute Maximum Ratings  
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress  
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC  
Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.  
Item  
Rating  
Power Supply Voltage, VDD  
Input Voltage, VI  
-0.5V to + 3.6V  
-0.5V to + 3.6V  
Output Voltage, VO  
Not to exceed 3.6V  
-0.5 to VDD + 0.5V  
Storage Temperature, TSTG  
Junction Temperature, TJ  
-65C to 150C  
150C  
Recommended Operating Range  
Symbol  
TA  
Description  
Minimum  
-40  
Typical  
25  
Maximum  
Units  
C  
Ambient Operating Temperature  
Internal Power Supply Voltage  
85  
VDD  
2.3  
2.5  
2.7  
V
IDT5T9304I REVISION B MAY 15, 2013  
4
©2013 Integrated Device Technology, Inc.a  
IDT5T9304I Data Sheet  
2.5V LVDS, 1:4 CLOCK BUFFER TERABUFFER™  
DC Electrical Characteristics  
Table 4A. LVDS Power Supply DC Characteristics(1), VDD = 2.5V 0.2V, TA = -40°C to 85°C  
Symbol Parameter  
Test Conditions  
Minimum  
Typical(2)  
Maximum  
Units  
VDD = Max.,  
All Input Clocks = LOW(2)  
Output enabled  
IDDQ  
Quiescent VDD Power Supply Current  
;
240  
mA  
VDD = 2.7V;  
REFERENCE Clock = 450MHz  
ITOT  
IPD  
Total Power VDD Supply Current  
Total Power Down Supply Current  
250  
5
mA  
mA  
F
PD = LOW  
NOTE 1. These power consumption characteristics are for all the valid input interfaces and cover the worst case conditions.  
NOTE 2. The true input is held LOW and the complementary input is held HIGH.  
Table 4B. LVCMOS/LVTTL DC Characteristics(1), VDD = 2.5V 0.2V, TA = -40°C to 85°C  
Symbol Parameter  
Test Conditions  
VDD = 2.7V  
Minimum  
Typical(2)  
Maximum  
Units  
µA  
µA  
V
IIH  
Input High Current  
5
5
IIL  
Input Low Current  
VDD = 2.7V  
VIK  
VIN  
VIH  
VIL  
VTHI  
Clamp Diode Voltage  
DC Input Voltage  
VDD = 2.3V, IIN = -18mA  
-0.7  
-1.2  
3.6  
-0.3  
1.7  
V
DC Input High Voltage  
DC Input Low Voltage  
DC Input Threshold Crossing Voltage  
V
0.7  
V
VDD/2  
1.65  
V
3.3V LVTTL  
2.5V LVTTL  
V
VREF  
Single-Ended Reference Voltage (3)  
1.25  
V
NOTE 1. See Recommended Operating Range table.  
NOTE 2. Typical values are at VDD = 2.5V, +25°C ambient.  
NOTE 3. For A[1:2] single-ended operation, A[1:2] is tied to a DC reference voltage.  
Table 4C. Differential DC Characteristics(1), VDD = 2.5V 0.2V, TA = -40°C to 85°C  
Symbol  
IIH  
Parameter  
Test Conditions  
VDD = 2.7V  
Minimum  
Typical(2)  
Maximum  
Units  
µA  
µA  
V
Input High Current  
5
5
IIL  
Input Low Current  
VDD = 2.7V  
VIK  
Clamp Diode Voltage  
VDD = 2.3V, IIN = -18mA  
-0.7  
-1.2  
3.6  
VIN  
DC Input Voltage  
-0.3  
0.1  
V
VDIF  
VCM  
DC Differential Voltage(3)  
DC Common Mode Input Voltage  
V
0.05  
VDD  
V
NOTE 1. See Recommended Operating Range table.  
NOTE 2. Typical values are at VDD = 2.5V, +25°C ambient.  
NOTE 3. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is  
the "complement" input level. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC  
differential voltage must be achieved to guarantee switching to a new state.  
NOTE 4. VCM specifies the maximum allowable range of (VTR + VCP) /2.  
IDT5T9304I REVISION B MAY 15, 2013  
5
©2013 Integrated Device Technology, Inc.a  
IDT5T9304I Data Sheet  
2.5V LVDS, 1:4 CLOCK BUFFER TERABUFFER™  
Table 4D. LVDS DC Characteristics(1), VDD = 2.5V 0.2V, TA = -40°C to 85°C  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical(2)  
Maximum  
Units  
Differential Output Voltage for the  
True Binary State  
VOT(+)  
247  
454  
mV  
Differential Output Voltage for the  
False Binary State  
VOT(–)  
VOT  
VOS  
247  
454  
50  
mV  
mV  
V
Change in VOT Between Complementary  
Output States  
Output Common Mode Voltage  
(Offset Voltage)  
1.125  
1.2  
1.375  
50  
Change in VOS Between Complementary  
Output States  
VOS  
mV  
IOS  
Outputs Short Circuit Current  
VOUT+ and VOUT– = 0V  
VOUT+ = VOUT–  
12  
6
24  
12  
mA  
mA  
IOSD  
Differential Outputs Short Circuit Current  
NOTE 1. See Recommended Operating Range table.  
NOTE 2. Typical values are at VDD = 2.5V, +25°C ambient.  
AC Electrical Characteristics  
Table 5A. HSTL Differential Input AC Characteristics, VDD = 2.5V 0.2V, TA = -40°C to 85°C  
Symbol  
VDIF  
VX  
Parameter  
Input Signal Swing(1)  
Differential Input Signal Crossing Point(2)  
Value  
Units  
1
V
mV  
%
750  
DH  
Duty Cycle  
50  
VTHI  
tR / tF  
Input Timing Measurement Reference Level(3)  
Input Signal Edge Rate(4)  
Crossing Point  
2
V
V/ns  
NOTE 1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE)  
environment. This device meets the VDIF (AC) specification under actual use conditions.  
NOTE 2. A 750mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment.  
This device meets the VX specification under actual use conditions.  
NOTE 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.  
NOTE 4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.  
Table 5B. eHSTL AC Differential Input Characteristics, VDD = 2.5V 0.2V, TA = -40°C to 85°C  
Symbol  
VDIF  
VX  
Parameter  
Input Signal Swing(1)  
Differential Input Signal Crossing Point(2)  
Value  
Units  
V
1
900  
mV  
%
DH  
Duty Cycle  
50  
VTHI  
tR / tF  
Input Timing Measurement Reference Level(3)  
Input Signal Edge Rate(4)  
Crossing Point  
2
V
V/ns  
NOTE 1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE)  
environment. This device meets the VDIF (AC) specification under actual use conditions.  
NOTE 2. A 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment.  
This device meets the VX specification under actual use conditions.  
NOTE 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.  
NOTE 4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.  
IDT5T9304I REVISION B MAY 15, 2013  
6
©2013 Integrated Device Technology, Inc.a  
IDT5T9304I Data Sheet  
2.5V LVDS, 1:4 CLOCK BUFFER TERABUFFER™  
Table 5C. LVEPECL (2.5V) and LVPECL (3.3V) Differential Input AC Characteristics, VDD = 2.5V 0.2V, TA = -40°C to 85°C  
Symbol  
Parameter  
Input Signal Swing(1)  
Maximum  
Units  
mV  
mV  
mV  
%
VDIF  
732  
LVEPECL  
LVPECL  
1082  
VX  
Differential Input Cross Point Voltage(2)  
1880  
DH  
Duty Cycle  
50  
VTHI  
tR / tF  
Input Timing Measurement Reference Level(3)  
Input Signal Edge Rate(4)  
Crossing Point  
2
V
V/ns  
NOTE 1. The 732mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE)  
environment. This device meets the VDIF (AC) specification under actual use conditions.  
NOTE 2. A 1082mV LVEPECL (2.5V) and 1880mV LVPECL (3.3V) crossing point level is specified to allow consistent, repeatable results in an  
automatic test equipment (ATE) environment. This device meets the VX specification under actual use conditions.  
NOTE 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.  
NOTE 4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.  
Table 5D. LVDS Differential Input AC Characteristics, TA = -40°C to 85°C  
Symbol  
VDIF  
VX  
Parameter  
Input Signal Swing(1)  
Differential Input Cross Point Voltage(2)  
Maximum  
Units  
mV  
V
400  
1.2  
DH  
Duty Cycle  
50  
%
VTHI  
tR / tF  
Input Timing Measurement Reference Level(3)  
Input Signal Edge Rate(4)  
Crossing Point  
2
V
V/ns  
NOTE 1. The 400mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE)  
environment. This device meets the VDIF (AC) specification under actual use conditions.  
NOTE 2. A 1.2V crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This  
device meets the VX specification under actual use conditions.  
NOTE 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.  
NOTE 4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.  
Table 5E. AC Differential Input Characteristics(1), VDD = 2.5V 0.2V, TA = -40°C to 85°C  
Symbol  
VDIF  
VX  
Parameter  
Minimum  
0.1  
Typical  
Maximum  
3.6  
Units  
AC Differential Voltage(2)  
Differential Input Cross Point Voltage  
Common Mode Input Voltage Range(3)  
Input Voltage  
V
V
V
V
0.05  
VDD  
VCM  
VIN  
0.05  
VDD  
-0.3  
3.6  
NOTE 1. The output will not change state until the inputs have crossed and the minimum differential voltage range defined by VDIF has been  
met or exceeded.  
NOTE 2. VDIF specifies the minimum input voltage (VTR – VCP) required for switching where VTR is the “true” input level and VCP is the  
“complement” input level. The AC differential voltage must be achieved to guarantee switching to a new state.  
NOTE 3. VCM specified the maximum allowable range of (VTR + VCP) /2.  
IDT5T9304I REVISION B MAY 15, 2013  
7
©2013 Integrated Device Technology, Inc.a  
IDT5T9304I Data Sheet  
2.5V LVDS, 1:4 CLOCK BUFFER TERABUFFER™  
Table 5F. AC Characteristics(1,5), VDD = 2.5V 0.2V, TA = -40°C to 85°C  
Symbol  
tsk(o)  
tsk(p)  
tsk(pp)  
tpLH  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
50  
Units  
ps  
Same Device Output Pin-to-Pin Skew (2)  
Pulse Skew(3)  
Part-to-Part Skew(4)  
125  
ps  
300  
ps  
Propagation Delay, Low-to-High  
Propagation Delay, High-to-Low  
Frequency Range(6)  
1.7  
1.7  
1.9  
ns  
A Crosspoint to Qn, Qn  
Crosspoint  
tpHL  
1.9  
ns  
fo  
450  
MHz  
Output Gate Enable Crossing  
VTHI-to-Qn/Qn Crosspoint  
tPGE  
3.5  
3.5  
ns  
ns  
Output Gate Enable Crossing  
VTHI-to-Qn/Qn Crosspoint Driven to  
Designated Level  
tPGD  
tPWRDN  
tPWRUP  
tR / tF  
PD Crossing VTHI-to-Qn = VDD, Qn = VDD  
100  
100  
700  
µS  
µS  
ps  
Output Gate Disable Crossing VTHI to  
Qn/Qn Driven to Designated Level  
Output Rise/Fall Time(6)  
20% to 80%  
125  
NOTE. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is  
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium  
has been reached under these conditions.  
NOTE 1. AC propagation measurements should not be taken within the first 100 cycles of startup.  
NOTE 2. Skew measured between Crosspoint of all differential output pairs under identical input and output interfaces, transitions and load  
conditions on any one device.  
NOTE 3. Skew measured is the difference between propagation delay times tpHL and tpLH of any differential output pair under identical input  
and output interfaces, transitions and load conditions on any one device.  
NOTE 4. Skew measured is the magnitude of the difference in propagation times between any single differential output pair of two devices,  
given identical transitions and load conditions at identical VDD levels and temperature.  
NOTE 5. All parameters are tested with a 50% input duty cycle.  
NOTE 6. Guaranteed by design but not production tested.  
IDT5T9304I REVISION B MAY 15, 2013  
8
©2013 Integrated Device Technology, Inc.a  
IDT5T9304I Data Sheet  
2.5V LVDS, 1:4 CLOCK BUFFER TERABUFFER™  
Applications Information  
EPAD Thermal Release Path  
In order to maximize both the removal of heat from the package and  
the electrical performance, a land pattern must be incorporated on  
the Printed Circuit Board (PCB) within the footprint of the package  
corresponding to the exposed metal pad or exposed heat slug on the  
package, as shown in Figure 1. The solderable area on the PCB, as  
defined by the solder mask, should be at least the same size/shape  
as the exposed pad/slug area on the package to maximize the  
thermal/electrical performance. Sufficient clearance should be  
designed on the PCB between the outer edges of the land pattern  
and the inner edges of pad pattern for the leads to avoid any shorts.  
and dependent upon the package power dissipation as well as  
electrical conductivity requirements. Thus, thermal and electrical  
analysis and/or testing are recommended to determine the minimum  
number needed. Maximum thermal and electrical performance is  
achieved when an array of vias is incorporated in the land pattern. It  
is recommended to use as many vias connected to ground as  
possible. It is also recommended that the via diameter should be 12  
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is  
desirable to avoid any solder wicking inside the via during the  
soldering process which may result in voids in solder between the  
exposed pad/slug and the thermal land. Precautions should be taken  
to eliminate any solder voids between the exposed heat slug and the  
land pattern. Note: These recommendations are to be used as a  
guideline only. For further information, refer to the Application Note  
on the Surface Mount Assembly of Amkor’s Thermally/Electrically  
Enhance Leadframe Base Package, Amkor Technology.  
While the land pattern on the PCB provides a means of heat transfer  
and electrical grounding from the package to the board through a  
solder joint, thermal vias are necessary to effectively conduct from  
the surface of the PCB to the ground plane(s). The land pattern must  
be connected to ground through these vias. The vias act as “heat  
pipes”. The number of vias (i.e. “heat pipes”) are application specific  
SOLDER  
SOLDER  
SOLDER  
EXPOSED HEAT SLUG  
PIN  
PIN  
LAND PATTERN  
(GROUND PAD)  
PIN PAD  
GROUND PLANE  
PIN PAD  
THERMAL VIA  
Figure 1. Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale)  
IDT5T9304I REVISION B MAY 15, 2013  
9
©2013 Integrated Device Technology, Inc.a  
IDT5T9304I Data Sheet  
2.5V LVDS, 1:4 CLOCK BUFFER TERABUFFER™  
Differential AC Timing Waveforms  
Output Propagation and Skew Waveforms  
1/fo  
+ VDIF  
V
DIF = 0  
A
[1:2] - A[1:2]  
- VDIF  
t
PHL  
t
PLH  
+ VDIF  
V
DIF = 0  
- VDIF  
Qn - Qn  
t
SK(O)  
t
SK(O)  
+ VDIF  
V
DIF = 0  
- VDIF  
Qm - Qm  
NOTE 1: Pulse skew is calculated using the following expression:  
tsk(p) = |tpHL – tpLH|  
Note that the tpHL and tpLH shown above ae not valid measurements for this calculation because they are not taken from the same pulse.  
NOTE 2: AC propagation measurements should not be taken within the first 100 cycles of startup.  
Differential Gate Disabled/Endable Showing Runt Pulse Generation  
+ VDIF  
V
DIF = 0  
A
[1:2] - A[1:2]  
- VDIF  
V
V
V
IH  
THI  
IL  
GL  
G
t
PLH  
V
V
V
IH  
THI  
IL  
t
PGD  
tPGE  
+ VDIF  
DIF = 0  
- VDIF  
V
Qn - Qn  
NOTE 1: As shown, it is possible to generate runt pulses on gate disable and enable of the outputs. It is the user’s responsibility to time the G  
signal to avoid this problem.  
IDT5T9304I REVISION B MAY 15, 2013  
10  
©2013 Integrated Device Technology, Inc.a  
IDT5T9304I Data Sheet  
2.5V LVDS, 1:4 CLOCK BUFFER TERABUFFER™  
Power Down Timing  
+VDIF  
V
DIF=0  
A1 - A1  
-VDIF  
+VDIF  
V
DIF=0  
A2 - A2  
-VDIF  
V
V
V
IH  
THI  
IL  
G
V
V
V
IH  
THI  
IL  
PD  
+VDIF  
DIF=0  
-VDIF  
Qn - Qn  
V
NOTE 1: It is recommended that outputs be disabled before entering power-down mode. It is also recommended that the outputs remain  
disabled until the device completes power-up after asserting PD.  
NOTE 2: The Power Down Timing diagram assumes that GL is HIGH.  
NOTE 3: It should be noted that during power-down mode, the outputs are both pulled to VDD. In the Power Down Timing diagram this is  
shown when Qn/Qn goes to VDIF = 0.  
IDT5T9304I REVISION B MAY 15, 2013  
11  
©2013 Integrated Device Technology, Inc.a  
IDT5T9304I Data Sheet  
2.5V LVDS, 1:4 CLOCK BUFFER TERABUFFER™  
Test Circuit for Differential Input  
50Ω  
Transmission Line  
V
IN  
V
DD/2  
A
A
D.U.T.  
Pulse  
Generator  
50Ω  
Transmission Line  
V
IN  
-VDD/2  
Scope  
50Ω  
50Ω  
Table 6A. Differential Input Test Conditions  
Symbol  
VDD = 2.5V 0.2V  
Unit  
VTHI  
Crossing of A and A  
V
IDT5T9304I REVISION B MAY 15, 2013  
12  
©2013 Integrated Device Technology, Inc.a  
IDT5T9304I Data Sheet  
2.5V LVDS, 1:4 CLOCK BUFFER TERABUFFER™  
Test Circuit for DC Outputs and Power Down Tests  
V
DD  
A
A
Qn  
Qn  
Pulse  
Generator  
R
L
L
D.U.T.  
V
OS  
VOD  
R
Test Circuit for Propagation, Skew, and Gate Enable/Disable Timing  
V
DD/2  
SCOPE  
CL  
= 50Ω  
A
A
Qn  
Qn  
Pulse  
Generator  
50Ω  
50Ω  
D.U.T.  
= 50Ω  
CL  
-VDD/2  
Table 6B. Differential Input Test Conditions  
Symbol  
VDD = 2.5V 0.2V  
Unit  
pF  
pF  
0(1)  
8(1,2)  
50  
CL  
RL  
NOTE 1: Specifications only apply to “Normal Operations” test condition. The TIA/EIA specification load is for reference only.  
NOTE 2: The scope inputs are assumed to have a 2pF load to ground. TIA/EIA – 644 specifies 5pF between the output pair.  
With CL = 8pF, this gives the test circuit appropriate 5pF equivalent load.  
IDT5T9304I REVISION B MAY 15, 2013  
13  
©2013 Integrated Device Technology, Inc.a  
IDT5T9304I Data Sheet  
2.5V LVDS, 1:4 CLOCK BUFFER TERABUFFER™  
Package Outline and Package Dimensions  
Package Outline - G Suffix for 24 Lead TSSOP, E-Pad  
Table 6. Package Dimensions  
All Dimensions in Millimeters  
Minimum Nominal  
Symbol  
N
Maximum  
24  
A
1.10  
0.15  
0.95  
0.30  
0.25  
0.20  
0.16  
7.90  
A1  
A2  
b
0.05  
0.85  
0.19  
0.19  
0.09  
0.09  
7.70  
0.90  
0.22  
b1  
c
c1  
D
0.127  
E
6.40 Basic  
4.40  
E1  
e
4.30  
4.50  
0.65 Basic  
0.60  
L
0.50  
5.0  
3.0  
0°  
0.70  
5.5  
3.2  
8°  
P
P1  
  
bbb  
0.076  
0.10  
IDT5T9304I REVISION B MAY 15, 2013  
14  
©2013 Integrated Device Technology, Inc.a  
IDT5T9304I Data Sheet  
2.5V LVDS, 1:4 CLOCK BUFFER TERABUFFER™  
Ordering Information  
Table 8. Ordering Information  
XX  
X
XXXXX  
Package Process  
Device Type  
I
-40 C to +85 C (Industrial)  
Thin Shrink Small Outline Package, E-Pad  
TSSOP - Green  
EJ  
EJG  
2.5V LVDS 1:4 Glitchless Clock Buffer  
Terabuffer II  
5T9304  
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the  
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal  
commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not  
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product  
for use in life support devices or critical medical instruments.  
IDT5T9304I REVISION B MAY 15, 2013  
15  
©2013 Integrated Device Technology, Inc.a  
IDT5T9304I Data Sheet  
2.5V LVDS, 1:4 CLOCK BUFFER TERABUFFER™  
Revision History Sheet  
Rev  
Table  
Page  
Description of Change  
Date  
A
9
8
Added EPAD Thermal Release Path section.  
3/12/10  
T5F  
8
AC Characteristics Table - per PCN660, changed both Propgation Delay specs from  
1.25ns typical to 1.7ns and 1.75ns maximum to 1.9ns.  
B
7/31/2012  
B
B
15  
1
Removed IDT from the Ordering Information  
Not Recommended For New Designs  
9/21/12  
5/15/13  
IDT5T9304I REVISION B MAY 15, 2013  
16  
©2013 Integrated Device Technology, Inc.a  
IDT5T9304I Data Sheet  
2.5V LVDS, 1:4 CLOCK BUFFER TERABUFFER™  
We’ve Got Your Timing Solution  
6024 Silver Creek Valley Road Sales  
Technical Support  
800-345-7015 (inside USA)  
netcom@idt.com  
San Jose, California 95138  
+408-284-8200 (outside USA) +480-763-2056  
Fax: 408-284-2775  
www.IDT.com/go/contactIDT  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,  
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not  
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the  
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any  
license under intellectual property rights of IDT or any third parties.  
IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT  
product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third  
party owners.  
Copyright 2012. All rights reserved.  
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