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5T9950PFI

型号：

5T9950PFI

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

9 页

PDF大小：

451 K

下载PDF手册
2.5V PROGRAMMABLE  
IDT5T9950/A  
SKEW PLL CLOCK DRIVER  
TURBOCLOCK™ II JR.  
FEATURES:  
DESCRIPTION:  
• Ref input is 3.3V tolerant  
The IDT5T9950is a highfanout2.5VPLLbasedclockdriverintended  
forhighperformancecomputinganddata-communicationsapplications.A  
keyfeatureoftheprogrammableskewistheabilityofoutputstoleadorlag  
the REF input signal. The IDT5T9950 has eight programmable skew  
outputs infourbanks of2.Skewis controlledby3-levelinputsignals that  
may be hard-wired to appropriate high-mid-low levels.  
• 4 pairs of programmable skew outputs  
• Low skew: 185ps same pair, 250ps all outputs  
• Selectable positive or negative edge synchronization:  
Excellent for DSP applications  
• Synchronous output enable  
• Input frequency:  
– Std: 6MHz to 160MHz  
– A: 6MHz to 200MHz  
• Output frequency:  
WhenthesOEpinisheldlow,alltheoutputsaresynchronouslyenabled.  
However, if sOE is held high, all the outputs except 2Q0 and 2Q1 are  
synchronouslydisabled. TheLOCKoutputassertstoindicatewhenPhase  
Lock has been achieved.  
– Std: 6MHz to 160MHz  
– A: 6MHz to 200MHz  
Furthermore,whenPEisheldhigh,alltheoutputsaresynchronizedwith  
thepositiveedgeoftheREFclockinput.WhenPEisheldlow,alltheoutputs  
are synchronized with the negative edge of REF. The IDT5T9950 has  
LVTTLoutputs with12mAbalanceddrive outputs.  
• 2x, 4x, 1/2, and 1/4 outputs  
• 3-level inputs for skew and PLL range control  
• PLL bypass for DC testing  
• External feedback, internal loop filter  
• 12mA balanced drive outputs  
• Low Jitter: <100ps cycle-to-cycle  
• Standard and A speed grades  
• Available in TQFP package  
FUNCTIONALBLOCKDIAGRAM  
sOE  
1Q0  
Skew  
Select  
1Q1  
3
3
1F1:0  
2F1:0  
PE TEST  
3
2Q0  
2Q1  
Skew  
Select  
3
3
3
3
REF  
PLL  
FB  
3Q0  
3Q1  
Skew  
Select  
3
3
FS  
3F1:0  
4F1:0  
4Q0  
4Q1  
Skew  
Select  
3
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
OCTOBER 2008  
1
c
2002 Integrated Device Technology, Inc.  
DSC 5869/6  
IDT5T9950/A  
2.5VPROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCKIIJR.  
INDUSTRIALTEMPERATURERANGE  
PINCONFIGURATION  
ABSOLUTEMAXIMUMRATINGS(1)  
Symbol  
Description  
Max  
–0.5 to +4.6  
–0.5 to VDD+0.5  
–0.5 to +4.6  
0.7  
Unit  
V
VDDQ, VDD Supply Voltage to Ground  
VI  
DC Input Voltage  
REF Input Voltage  
Maximum Power  
Dissipation  
V
V
32 31 30 29 28 27 26 25  
TA = 85°C  
TA = 55°C  
W
24  
23  
22  
21  
20  
19  
18  
17  
3F1  
4F0  
1
2
3
4
5
6
7
8
1F1  
1F0  
1.1  
TSTG  
Storage Temperature Range  
–65 to +150  
° C  
NOTE:  
4F1  
PE  
sOE  
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause  
permanent damage to the device. These are stress ratings only, and functional  
operation of the device at these or any other conditions above those indicated in the  
operational sections of this specification is not implied. Exposure to absolute-  
maximum-rated conditions for extended periods may affect device reliability.  
VDDQ  
VDDQ  
4Q1  
1Q0  
1Q1  
GND  
GND  
4Q0  
CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V)  
GND  
Parameter Description  
Typ. Max.  
Unit  
9
10 11 12 13 14 15 16  
CIN  
InputCapacitance  
5
7
pF  
NOTE:  
1. Capacitance applies to all inputs except TEST, FS, nF[1:0], and DS[1:0].  
TQFP  
TOP VIEW  
PINDESCRIPTION  
Pin Name  
REF  
Type  
IN  
Description  
ReferenceClockInput  
FeedbackInput  
FB  
IN  
TEST(1)  
IN  
WhenMIDorHIGH,disablesPLL(exceptforconditionsofNote1). REFgoestoalloutputs. SkewSelections(SeeControlSummary  
Table)remainineffect. SetLOWfornormaloperation.  
sOE(1)  
IN  
IN  
SynchronousOutputEnable. WhenHIGH,itstopsclockoutputs(except2Q0 and2Q1)inaLOWstate(forPE=H)-2Q0 and2Q1may  
beusedasthefeedbacksignaltomaintainphaselock. WhenTESTisheldatMIDlevelandsOEisHIGH,thenF[1:0]pinsactasoutput  
disable controls forindividualbanks whennF[1:0] =LL. SetsOE LOWfornormaloperation(has internalpull-down).  
PE  
Selectablepositiveornegativeedgecontrol. WhenLOW/HIGHtheoutputsaresynchronizedwiththenegative/positiveedgeofthereference  
clock(hasinternalpull-up).  
nF[1:0]  
FS  
IN  
3-levelinputsforselecting1of9skewtapsorfrequencyfunctions  
Selectsappropriateoscillatorcircuitbasedonanticipatedfrequencyrange. (SeeProgrammableSkewRange.)  
Fourbanksoftwooutputswithprogrammableskew  
IN  
nQ[1:0]  
VDDQ  
VDD  
OUT  
PWR  
PWR  
PWR  
Powersupplyforoutputbuffers  
Powersupplyforphaselockedloop,lockoutput,andotherinternalcircuitry  
Ground  
GND  
NOTE:  
1. When TEST = MID and sOE = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections remain in  
effect unless nF[1:0] = LL.  
2
IDT5T9950/A  
INDUSTRIALTEMPERATURERANGE  
2.5VPROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCKIIJR.  
PROGRAMMABLESKEW  
Output skew with respect to the REF input is adjustable to compensate figurations are chosen by the nF1:0 control pins. In order to minimize the  
for PCB trace delays, backplane propagation delays or to accommodate number of control pins, 3-level inputs (HIGH-MID-LOW) are used, they  
requirements for special timing relationships between clocked compo- are intended for but not restricted to hard-wiring. Undriven 3-level in-  
nents. Skew is selectable as a multiple of a time unit (tU) which ranges puts default to the MID level. Where programmable skew is not a re-  
from 782ps to 1.5625ns for Standard version and 6.25ps to 1.3ns for A quirement, the control pins can be left open for the zero skew default  
version (see Programmable Skew Range and Resolution Table). There setting. The Control Summary Table shows how to select specific skew  
are nine skew configurations available for each output pair. These con- taps by using the nF1:0 control pins.  
EXTERNALFEEDBACK  
By providing external feedback, the IDT5T9950 gives users flexibility  
An internal loop filter moderates the response of the VCO to the  
with regard to skew adjustment. The FB signal is compared with the phase detector. The loop filter transfer function has been chosen to  
input REF signal at the phase detector in order to drive the VCO. Phase provide minimal jitter (or frequency variation) while still providing accu-  
differences cause the VCO of the PLL to adjust upwards or downwards rate responses to input frequency changes.  
accordingly.  
PROGRAMMABLESKEWRANGEANDRESOLUTIONTABLE  
IDT5T9950  
FS = MID  
IDT5T9950A  
FS = MID  
FS = LOW  
1/(32 x FNOM)  
24 to 40MHz  
FS = HIGH  
1/(8 x FNOM)  
80 to 160MHz  
FS = LOW  
FS = HIGH  
Comments  
TimingUnitCalculation(tU)  
VCOFrequencyRange(FNOM)(1,2)  
SkewAdjustmentRange(3)  
MaxAdjustment:  
1/(16 x FNOM)  
40 to 80MHz  
1/(32 x FNOM) 1/(16 x FNOM) 1/(8 x FNOM)  
24 to 50MHz 48 to 100MHz 96 to 200MHz  
±7.8125ns  
±67.5°  
±18.75%  
tU =1.25ns  
tU =0.833ns  
—
±9.375ns  
±135°  
±37.5%  
—
±9.375ns  
±270°  
±75%  
—
±7.8125ns  
±67.5°  
±18.75%  
tU =1.25ns  
tU =0.833ns  
tU =0.625ns  
—
±7.8125ns  
±135°  
±7.8125ns  
±270°  
ns  
PhaseDegrees  
% of Cycle Time  
±37.5%  
—
±75%  
—
Example 1, FNOM = 25MHz  
Example 2, FNOM = 37.5MHz  
Example 3, FNOM = 50MHz  
Example 4, FNOM = 75MHz  
Example 5, FNOM = 100MHz  
Example 6, FNOM = 150MHz  
Example 7, FNOM = 200MHz  
—
—
—
—
tU =1.25ns  
tU =0.833ns  
—
—
tU =1.25ns  
tU =0.833ns  
tU =0.625ns  
—
—
—
—
—
—
tU =1.25ns  
tU =0.833ns  
—
—
tU =1.25ns  
tU =0.833ns  
tU =0.625ns  
—
—
—
—
—
—
—
NOTES:  
1. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed.  
2. The level to be set on FS is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO frequency always appears at 1Q1:0, 2Q1:0, and  
the higher outputs when they are operated in their undivided modes. The frequency appearing at the REF and FB inputs will be the same as the VCO when the output connected  
to FB is undivided. The frequency of the REF and FB inputs will be 1/2 or 1/4 the VCO frequency when the part is configured for frequency multiplication by using a divided  
output as the FB input.  
3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then adjustment range will be greater. For example  
if a 4tU skewed output is used for feedback, all other outputs will be skewed –4tU in addition to whatever skew value is programmed for those outputs. ‘Max adjustment’ range  
applies to output pairs 3 and 4 where ± 6tU skew adjustment is possible and at the lowest FNOM value.  
3
IDT5T9950/A  
2.5VPROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCKIIJR.  
INDUSTRIALTEMPERATURERANGE  
CONTROLSUMMARYTABLEFORFEEDBACKSIGNALS  
nF1:0  
LL(1)  
LM  
Skew (Pair #1, #2)  
Skew (Pair #3)  
Divide by 2  
–6tU  
Skew (Pair #4)  
Divide by 2  
–6tU  
–4tU  
–3tU  
LH  
–2tU  
–4tU  
–4tU  
ML  
–1tU  
–2tU  
–2tU  
MM  
MH  
HL  
ZeroSkew  
1tU  
ZeroSkew  
2tU  
ZeroSkew  
2tU  
2tU  
4tU  
4tU  
HM  
HH  
3tU  
6tU  
6tU  
Inverted(2)  
4tU  
Divide by 4  
NOTES:  
1. LL disables outputs if TEST = MID and sOE = HIGH.  
2. When pair #4 is set to HH (inverted), sOE disables pair #4 HIGH when PE = HIGH, sOE disables pair #4 LOW when PE = LOW.  
RECOMMENDEDOPERATINGRANGE  
Symbol  
VDD/VDDQ  
TA  
Description  
Min.  
2.3  
Typ.  
2.5  
Max.  
2.7  
Unit  
V
Power Supply Voltage  
AmbientOperatingTemperature  
-40  
+25  
+85  
° C  
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE  
Symbol  
Parameter  
Conditions  
Guaranteed Logic HIGH (REF, FB Inputs Only)  
Guaranteed Logic LOW (REF, FB Inputs Only)  
3-Level Inputs Only  
Min.  
Max.  
Unit  
V
VIH  
Input HIGH Voltage  
1.7  
—
0.7  
VIL  
InputLOWVoltage  
—
V
VIHH  
VIMM  
VILL  
IIN  
Input HIGH Voltage(1)  
InputMIDVoltage(1)  
InputLOWVoltage(1)  
InputLeakageCurrent  
(REF, FB Inputs Only)  
VDD−0.4  
VDD/2−0.2  
—
—
V
3-Level Inputs Only  
VDD/2+0.2  
0.4  
V
3-Level Inputs Only  
V
VIN = VDD or GND  
−5  
+5  
µA  
VDD = Max.  
VIN = VDD  
HIGH Level  
MID Level  
LOW Level  
—
−50  
−200  
−100  
—
+200  
+50  
—
I3  
3-Level Input DC Current (TEST, FS, nF[1:0])  
VIN = VDD/2  
µ A  
VIN = GND  
IPU  
IPD  
Input Pull-Up Current (PE)  
InputPull-DownCurrent(sOE)  
OutputHIGHVoltage  
VDD = Max., VIN = GND  
VDD = Max., VIN = VDD  
VDD = Min., IOH = −12mA  
VDD = Min., IOL = 12mA  
—
µ A  
µ A  
V
+100  
—
VOH  
VOL  
2
OutputLOWVoltage  
—
0.4  
V
NOTE:  
1. These inputs are normally wired to VDD, GND, or unconnected. Internal termination resistors bias unconnected inputs to VDD/2. If these inputs are switched, the function and  
timing of the outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are achieved.  
4
IDT5T9950/A  
INDUSTRIALTEMPERATURERANGE  
2.5VPROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCKIIJR.  
POWERSUPPLYCHARACTERISTICS  
5T9950  
5T9950A  
Symbol  
Parameter  
TestConditions(1)  
VDD = Max., TEST = MID, REF = LOW,  
PE = LOW, sOE = LOW, FS = MID  
Alloutputsunloaded  
Typ.(2) Max. Typ.(2) Max.  
Unit  
IDDQ  
QuiescentPowerSupplyCurrent  
20  
1
30  
30  
20  
1
30  
30  
mA  
ΔIDD  
Power Supply Current per Input HIGH  
(REF and FB inputs only)  
VIN = 2.3V, VDD = Max., TEST = HIGH  
μA  
FS = L  
190  
150  
130  
49  
290  
230  
200  
—
—
—
—
—
—
190  
150  
130  
—
290  
230  
200  
—
—
—
—
—
—
IDDD  
Dynamic Power Supply Current per Output FS = M  
μA/MHz  
FS = H  
FS = L  
FVCO = 40MHz, CL = 0pF  
FVCO = 50MHz, CL = 0pF  
FVCO = 80MHz, CL = 0pF  
FVCO = 100MHz, CL = 0pF  
FVCO = 160MHz, CL = 0pF  
FVCO = 200MHz, CL = 0pF  
—
56  
ITOT  
TotalPowerSupplyCurrent  
FS = M  
FS = H  
66  
—
mA  
—
80  
103  
—
—
125  
NOTES:  
1. Measurements are for divide-by-1 outputs and nF[1:0] = MM.  
2. For nominal voltage and temperature.  
INPUTTIMINGREQUIREMENTS  
5T9950  
5T9950A  
Symbol  
tR,tF  
tPWC  
Description(1)  
Maximum input rise and fall times, 0.7V to 1.7V  
Input clock pulse, HIGH or LOW  
Input duty cycle  
Min.  
—
2
Max.  
10  
Min.  
Max.  
10  
Unit  
ns/V  
ns  
—
2
—
90  
—
DH  
10  
6
10  
6
90  
%
FS = LOW  
40  
50  
FREF  
Referenceclockinputfrequency  
FS = MID  
10  
20  
80  
12  
24  
100  
200  
MHz  
FS = HIGH  
160  
NOTE:  
1. Where pulse width implied by DH is less than tPWC limit, tPWC limit applies.  
5
IDT5T9950/A  
2.5VPROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCKIIJR.  
INDUSTRIALTEMPERATURERANGE  
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE  
5T9950  
5T9950A  
Typ.  
Symbol  
FNOM  
tRPWH  
tRPWL  
tU  
Parameter  
Min.  
Typ.  
Max.  
Min.  
Max.  
Unit  
VCO Frequency Range  
SeeProgrammableSkewRangeandResolutionTable  
(1)  
REF Pulse Width HIGH  
2
2
—
—
—
—
2
2
—
—
—
—
ns  
ns  
(1)  
REF Pulse Width LOW  
ProgrammableSkewTimeUnit  
SeeControlSummaryTable  
(2,3)  
tSKEWPR  
tSKEW0  
tSKEW1  
tSKEW2  
tSKEW3  
tSKEW4  
tDEV  
Zero Output Matched-Pair Skew (xQ0, xQ1)  
—
—
50  
0.1  
0.1  
0.2  
0.15  
0.3  
—
—
—
—
—
0.7  
0.7  
—
—
185  
0.25  
0.25  
0.5  
0.5  
0.9  
0.75  
0.3  
1
—
—
50  
0.1  
0.1  
0.2  
0.15  
0.3  
—
—
—
—
—
0.7  
0.7  
—
—
185  
0.25  
0.25  
0.5  
0.5  
0.9  
0.75  
0.25  
1
ps  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ms  
(4)  
ZeroOutputSkew(AllOutputs)  
(5)  
OutputSkew(Rise-Rise, Fall-Fall, Same Class Outputs)  
—
—
(5)  
OutputSkew(Rise-Fall,Nominal-Inverted,Divided-Divided)  
—
—
(5)  
OutputSkew(Rise-Rise,Fall-Fall,DifferentClassOutputs)  
—
—
(2)  
OutputSkew(Rise-Fall,Nominal-Divided,Divided-Inverted)  
—
—
(2,6)  
Device-to-Device Skew  
—
—
t(φ)  
REF Input to FB Static Phase Offset(7)  
−0.3  
−1  
—
−0.25  
−1  
—
tODCV  
tPWH  
Output Duty Cycle Variation from 50%  
(8)  
Output HIGH Time Deviation from 50%  
1.5  
2
1.5  
2
(9)  
tPWL  
OutputLOWTimeDeviationfrom50%  
—
—
tORISE  
tOFALL  
tLOCK  
tCCJH  
OutputRiseTime  
0.15  
0.15  
—
1.5  
1.5  
0.5  
100  
0.15  
0.15  
—
1.5  
1.5  
0.5  
100  
OutputFallTime  
PLLLockTime(10)  
Cycle-to-CycleOutputJitter(peak-to-peak)  
(divide by 1 output frequency, FS = H)  
Cycle-to-CycleOutputJitter(peak-to-peak)  
(divide by 1 output frequency, FS = M)  
Cycle-to-CycleOutputJitter(peak-to-peak)  
(divide by 1 output frequency, FS = L)  
—
—
tCCJM  
tCCJL  
—
—
—
—
200  
200  
—
—
—
—
150  
200  
ps  
NOTES:  
1. Refer to Input Timing Requirements table for more detail.  
2. Skew is the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with the specified  
load.  
3. tSKEWPR is the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.  
4. tSK(0) is the skew between outputs when they are selected for 0tU.  
5. There are 3 classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-2 or Divide-  
by-4 mode). Test condition: nF0:1=MM is set on unused outputs.  
6. tDEV is the output-to-output skew between any two devices operating under the same conditions (VDDQ, VDD, ambient temperature, air flow, etc.)  
7. tφ is measured with REF input rise and fall times (from 0.7V to 1.7V) of 0.5ns. Measured from 1.25V on REF to 1.25V on FB.  
8. Measured at 1.7V.  
9. Measured at 0.7V.  
10. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VDD/VDDQ is stable and within normal operating limits. This parameter  
is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.  
6
IDT5T9950/A  
INDUSTRIALTEMPERATURERANGE  
2.5VPROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCKIIJR.  
AC TEST LOADS AND WAVEFORMS  
VDDQ  
150Ω  
Output  
150Ω  
20pF  
tOFALL  
tORISE  
1.7V  
tPWH  
VTH = 1.25V  
0.7V  
tPWL  
2.5V Output Waveform  
≤1ns  
≤1ns  
2.5V  
1.7V  
VTH = 1.25V  
0.7V  
0V  
LVTTL Input Test Waveform  
7
IDT5T9950/A  
2.5VPROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCKIIJR.  
INDUSTRIALTEMPERATURERANGE  
AC TIMING DIAGRAM  
tRPWL  
tREF  
tRPWH  
REF  
FB  
Q
t(φ)  
tODCV  
tODCV  
tCCJ H,  
M, L  
tSKEWPR  
tSKEW0, 1  
tSKEWPR  
tSKEW0, 1  
OTHER Q  
tSKEW2  
tSKEW2  
INVERTED Q  
tSKEW3, 4  
tSKEW3, 4  
tSKEW3, 4  
tSKEW2, 4  
REF DIVIDED BY 2  
tSKEW1, 3, 4  
REF DIVIDED BY 4  
NOTES:  
PE:  
The AC Timing Diagram applies to PE=VDD. For PE=GND, the negative edge of FB aligns with the negative edge of REF, divided outputs change on the negative edge  
of REF, and the positive edges of the divide-by-2 and the divide-by-4 signals align.  
Skew:  
The time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with 20pF and terminated  
with 75Ω to VDDQ/2.  
tSKEWPR:  
tSKEW0:  
tDEV:  
The skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.  
The skew between outputs when they are selected for 0tU  
.
The output-to-output skew between any two devices operating under the same conditions (VDDQ, VDD, ambient temperature, air flow, etc.)  
The deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications.  
tODCV:  
tPWH is measured at 1.7V.  
tPWL is measured at 0.7V.  
tORISE and tOFALL are measured between 0.7V and 1.7V.  
tLOCK:  
The time that is required before synchronization is achieved. This specification is valid only after VDD/VDDQ is stable and within normal operating limits. This parameter  
is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.  
8
IDT5T9950/A  
INDUSTRIALTEMPERATURERANGE  
2.5VPROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCKIIJR.  
ORDERINGINFORMATION  
X
XXXXX  
XX  
Package Package  
Device Type  
I
-40°C to +85°C (Industrial)  
Thin Quad Flat Pack  
TFQFPN - Green  
PF  
PFG  
5T9950  
5T9950A  
2.5V Programmable Skew PLL Clock  
Driver TurboClock II Jr.  
CORPORATE HEADQUARTERS  
6024 Silver Creek Valley Road  
San Jose, CA 95138  
for SALES:  
800-345-7015 or 408-284-8200  
fax: 408-284-2775  
for Tech Support:  
clockhelp@idt.com  
www.idt.com  
9
厂商 型号 描述 页数 下载

IDT

 		5T9010BBGI8 [ PLL Based Clock Driver, 5T Series, 5 True Output(s), 0 Inverted Output(s), PBGA144, LEAD FREE, PLASTIC, BGA-144 ] 25 页

IDT

 		5T9050PGI [ Low Skew Clock Driver, 5T Series, 5 True Output(s), 0 Inverted Output(s), CMOS, PDSO28, TSSOP-28 ] 7 页

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IDT

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IDT

 		5T9070PAI [ Clock Driver, CMOS, PDSO48 ] 9 页

IDT

 		5T9070PAI8 [ Clock Driver, CMOS, PDSO48 ] 9 页

IDT

 		5T907PAI [ Clock Driver, 5T Series, 10 True Output(s), 0 Inverted Output(s), CMOS, PDSO48, TSSOP-48 ] 19 页

IDT

 		5T907PAI8 [ Clock Driver, PDSO48 ] 19 页

IDT

 		5T9110BBGI8 [ PLL Based Clock Driver, 5T Series, 5 True Output(s), 0 Inverted Output(s), PBGA144, GREEN, PLASTIC, BGA-144 ] 23 页

IDT

 		5T915PAI [ Clock Driver, CMOS, PDSO48 ] 19 页

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