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NVM3060

型号：

NVM3060

描述：

4096位EEPROM[ 4096-Bit EEPROM ]

品牌：

ETC[ ETC ]

页数：

13 页

PDF大小：

334 K

下载PDF手册

NVM 3060

4096-Bit EEPROM

Edition Feb. 14, 1990

6251-309-2/E

ITT Semiconductors

NVM 3060

Contents

Page

Section

Title

Introduction

Specifications

2.1.

Outline Dimensions

Pin Connections

2.2.

2.3.

Pin Descriptions

2.4.

Pin Circuits

2.5.

Electrical Characteristics

Absolute Maximum Ratings

Recommended Operating Conditions

Characteristics

2.5.1.

2.5.2.

2.5.3.

Functional Description

Memory Operation

Testing

3.1.

3.2.

3.3.

3.4.

Protected Matrix

Shipment

Test Functions

4.1.

4.2.

4.3.

Block Programming

Read Reference Shifting

Charge Pump Disable

Description of the IM Bus

NVM 3060

4096-Bit EEPROM

1. Introduction

well as several analog settings, further alignment infor-

mation given in the factory when producing the TV set.

The stored information remains stored even with the

supplyvoltagesswitchedoff. Readingandprogramming

operations are executed via the IM bus (see section 5.).

Input and output signals are TTL level. An address op-

tion input provides the possibility to operate two memo-

ries in parallel, to obtain a total storage capacity of 8192

bits.

Electrically erasable programmable read-only memory

(EEPROM) in N-channel floating-gate technology with

a capacity of 512 words, 8 bits each.

The NVM 3060 is intended for use as a reprogrammable

non-volatile memory in conjunction with the CCU

2030/2050/2070/3000 series Central Control Units or

the SAA 12xx and TVPO 2066 Remote Control and Tun-

ing ICs. It serves for storing the tuning information as

The device contains an on-chip charge pump for high

programming voltage generation and an on-chip clock

oscillator.

Option

NVM 3060

Charge

Pump

Clock

Ident

Data

Output

Buffer

and

EEPROM

Matrix

512 x 8

IM Bus

Interface

Input

Decoder and

Memory Address

Sequence

Control

Reset

+5 V

GND

SUP

Fig. 1–1: Block diagram of the NVM 3060 EEPROM

NVM 3060

2. Specifications

Pin 2 – Safe Input S

Fig. 2–2 shows the internal configuration of this input.

Normally, with pin 2 at ground potential (low), one por-

tion of the programming matrix is protected so that this

part of the memory cannot be reprogrammed inadver-

tently. Only when pin 2 receives high potential continu-

ously, the protected portion of the memory matrix can be

programmed. Pin 2 is internally tied to ground via a tran-

sistor equivalent to a 40 kΩ resistor.

2.1. Outline Dimensions

2.5

6.4

Pin 3 – Option Input Fig. 2–2 shows the internal configu-

ration of this input. With pin 3 at ground potential (low)

or floating, the NVM 3060 reacts upon the IM bus ad-

dresses 128,129 and 131. With pin 3 continuously at

max. 9.5

max.

5.08

min. 0.5

SUP

potential (high), the NVM 3060 reacts upon this IM

0.38

min.

2.8

bus addresses 132,133 and 135 (see Fig.2–6). In this

way, parallel operation of two NVM 3060 is permitted, to

obtain 8192 bits of non-volatile storage directly accessi-

ble via the IM bus. Pin 3 is internally tied to ground via

a transistor equivalent to a 40 kΩ resistor.

0_...15

0.5

1.1

3 x 2.54

7.62

Fig. 2–1: NVM 3060 in 8-pin Dil Plastic Package

20 A 8 according to DIN 41870

Pin 4 – Reset Input

This input has a configuration as shown in Fig. 2–3. Via

this input, the NVM 3060, together with the other circuits

belonging to the system, receives the Reset signal

Weight approx. 0.5 g

Dimensions in mm

which is derived from V

via an external RC circuit. A

SUP

low level is required during power-up and power-down

procedures. Low level at pin 4 (max. 1.3 V) cancels a

programming procedure and an IM bus operation in pro-

gress. The memory address register is not erased. Dur-

ing operation, pin 4 requires high level (min. 2.4 V).

2.2. Pin Connections

Ground, 0

Safe Input S

Pins 5 to 7 – IM Bus Connections

Option Input

These pins serve to connect the NVM 3060 EEPROM

to the IM bus (see section 5.), via which it communicates

with the CCU 2030/2050/2070/3000 Central Control

Units or the SAA 12xx and TVPO 2066 Remote Control

and Tuning ICs. Pins 5 (IM Bus Clock Input) and 6 (IM

Bus Ident Input) are inputs as shown in Fig. 2–3 and pin

7 (IM Bus Data) is an input/output as shown in Fig. 2–4.

The signal diagram for the IM bus is illustrated in Figs.

2–6 and Fig. 5–1. The required addresses which the

NVM 3060 EEPROM receives from the microcomputer,

are also shown in Fig. 2–6.

Reset Input

IM Bus Clock Input

IM Bus Ident Input

IM Bus Data Input/Output

Supply Voltage V

SUP

Pin 8 – Supply Voltage V

2.3. Pin Descriptions

SUP

The supply voltage required is +5V (±5%), and the cur-

rent consumption in active operation is approx. 30 mA.

Inserting or removing the NVM 3060 from a live socket

may alter programmed data!

Pin 1 – Ground, 0

This pin must be connected to the negative of the sup-

plies.

NVM 3060

2.4. Pin Circuits

SUP

The following figures show schematically the circuitry at

the various pins. The integrated protection structures

are not shown. The letter “E” means enhancement,

the letter “D” depletion.

Fig. 2–3:

Pins 4, 5, and 6, Inputs

GND

SUP

Fig. 2–2:

Pins 2 and 3, Input S

Fig. 2–4:

GND

Pin 7, Input/Output

2.5. Electrical Characteristics

All Voltages are referred to ground.

2.5.1. Absolute Maximum Ratings

Symbol

Parameter

Pin No.

Min.

Max.

Unit

Ambient Operating

Temperature

–

°C

Storage Temperature

Supply Voltage

Input Voltage

–

–40

+125*

°C

–0.5

SUP

2 to 7

–0.3 V

–

SUP

–

Output Current

* Stored data may be affected by T above +85 °C

2.5.2. Recommended Operating Conditions

Symbol

Parameter

Pin No.

Min.

Typ.

Max.

5.25

0.8

–

Unit

Supply Voltage

4.75

–

5.0

–

SUP

Input Low Voltage

Input High Voltage

Reset Input Low Voltage

Reset Input High Voltage

2, 3, 5 to 7

2.4

–

1.3

–

REIL

REIH

2.4

–

– V

Delay Time*

4, 8

–

SUP

REI

– V

–

SUP

*see Fig. 2–5

NVM 3060

Recommended Operating Conditions, continued

Symbol

Parameter

Pin No.

Min.

–

Typ.

Max.

0.8

–

Unit

IMIL

IMIH

IM Bus Input Low Voltage

IM Bus Input High Voltage

ΦI IM Bus Clock Frequency

5 to 7

–

2.4

0.05

170

–

kHz

–

ΦI Clock Input Delay Time

IM1

after IM Bus Ident Input

ΦI Clock Input

Low Pulse Time

3.0

–

µs

–

IM2

IM3

IM4

IM5

IM6

IM7

IM8

IM9

IM10

ΦI Clock Input

High Pulse Time

ΦI Clock Input Setup Time

before Ident Input High

ΦI Clock Input Hold Time

after Ident Input High

1.5

6.0

µs

–

ΦI Clock Input Setup Time

before Ident End-Pulse Input

IM Bus Input Delay Time

after ΦI Clock Input

IM Bus Data Input Setup

Time before ΦI Clock Input

–

IM Bus Data Input Hold Time

after ΦI Clock Input

–

IM Bus Ident

3.0

µs

End-Pulse Low Time

4.75 V

1.3 V

SUP

t₄

t₇

REI

Fig. 2–5: Power on/off timing

NVM 3060

2.5.3. Characteristics at V

= 5 V, T = 25 _C

SUP

Symbol

Parameter

Pin No.

Min.

–

Typ.

–

Max.

Unit

µA

Test Conditions

Supply Current

Input High Current

SUP

4 to 6

= 5 V

IM Bus Data Output Low Voltage

IMBusDataOutputHighCurrent

InputInternalPUll-DownCurrent

Erase or Write Time

–

0.4

= 3 mA

IMOL

IMOH

IMO

–

µA

V = 5 V

IMO

2, 3

–

260

V = 5 V

–

Ident

Data

IM Bus Address

Memory Address: 2 Bytes in

a) Entering memory address within a 16 Bit transfer

Data

IM Bus Address

Memory Data: 1st Byte out

don’t care: 2nd Byte out

b1) Reading data as first Byte within a

16 Bit transfer

Data

IM Bus Address

Memory Data: single Byte out

b2) Alternative to b1: Reading Data as a single Byte in an

8 Bit transfer

Data

IM Bus Address

Memory Data: 1st Byte in

don’t care: 2nd Byte in

c) Entering Data as first Byte within a

16 Bit transfer

IM Bus Address

Pin 3 Low

Pin 3 High

a) enter memory address:

b) reading:

128

129

131

132

133

135

c) programming:

Fig. 2–6: Signal diagram for the IM Bus

NVM 3060

3. Functional Description

3.1. Memory Operation

operation for entering address 526 should always di-

rectly precede reading the busy-bit.

Reading any other address location during the busy

state will produce erroneous data at the Data output. An

address change operation during the busy state will not

change the memory address register content. The in-

tended start of another programming operation during

the busy time will not be executed.

The internal memory address space ranges from ad-

dress 0 to address 511. Addresses 516 and 526 provide

special functions.

To read a stored data word, the desired memory address

has to be entered to the memory address register first.

This is done by serially entering the IM bus address 128

(optionally 132) (during Ident = L), followed by the mem-

ory address (during Ident D = H) in a single IM bus op-

eration.

b) After time-out, normal operation may be resumed,

e.g. by performing the second step of a programming

sequence, i.e. by programming the desired 8-bit data

word into the respective memory address location. This

is done by restoring the proper memory address first, if

necessary, and then by serially entering the IM bus ad-

dress 131 (optionally 135) followed by the desired 8-bit

data word as LSB in a 16-bit word. The device will again

time its own programming sequence as described under

a). After time-out the new data may be verified.

With the memory address register set, the memory data

may be read. This, in turn, is done by entering the IM bus

address 129 (optionally 133) to the device (during Ident

= L). Immediately after this, within the same IM bus op-

eration (during Ident = H) the open-drain Data output will

conduct to serially transmit the respective 8-bit memory

data within a 16-bit word.

3.2. Testing

The NVM 3060 EEPROM contains circuitry designed to

facilitate testing of the various functions. By program-

ming data into address location 516, the device is

switched to one or more of a number of test modes. A

detailed description is given in section 4.

Reprogramming a memory location is done in two steps,

a) and b), that are identical except for the data word to

be entered. Step a) resets all bits to”1”, and step b) pro-

grams the desired data into the selected memory loca-

tion.

3.3. Protected Matrix

a) First, the desired memory address is entered in the

way described above. Second, the actual programming

is initiated by serially entering the IM bus address 131

(optionally 135) followed by the data word to be stored,

which is 255 for step a). The device will now internally

time its programming sequence. During this ”busy”

time all inputs are blocked from affecting the program-

ming except for the Reset input. A Reset = L signal will

immediately cancel any programming operation as well

as any bus operation in progress.

The programming matrix contains a protectable portion.

Addresses 0 to 15, 64 to 79, 128 to 143, 192 to 207, 256

to 271, 320 to 335, 384 to 399 and 448 to 463 can only

be programmed if the ”Safe” input S (pin 2) is at high

potential. In that way, this portion of the memory is pro-

tected against inadvertent reprogramming even if such

false informations were received via the IM bus. The

second part of the programming matrix is not protected.

The busy state may be interrogated by reading bit 1 of

address location 526. A High level of this “busy-bit” in-

dicates that programming is still under way. The IM bus

3.4. Shipment

Parts are shipped with all bits set to “1”.

NVM 3060

Block

Read

Test Byte

enable

Read

Charge

Pump

Read

programming

enable

reference

shift -0.3 V

reference

shift -0.6V

reference

shift + 0.3 V

reference

shift + 0.6 V

disable

Fig. 4–1: Functions of the 8 bits in the test byte

4. Test Functions

Program Test byte (e.g. 160)

Enter Address 0, 2 or 3

Program Data

This description of the test byte is not part of the specifi-

cation. It contains no information necessary for normal

(intended) use of the NVM 3060 memory. It is only in-

tended as a description of the various functions of the

test byte that are designed for factory use, but it does not

specify such properties. The description is subject to

change.

A checkerboard pattern is programmed with two pro-

gramming operations after loading the test byte:

Enter Address 2

Program Data 85

Enter Address 3

Program Data 170

Address location 516 contains a test byte which governs

test mode operation of the NVM 3060. The test byte is

set by performing the IM bus operation for entering ad-

dress 516, followed by an IM bus programming opera-

tion with the desired test data word. The test byte is valid

during all following IM bus operations until changed or

set to 0 by a Reset = L signal. The test byte shall not be

changed during the busy time of a programming opera-

tion. Fig. 4–1 shows the bit arrangement of the test byte.

Set bit 5 for activation of the test byte!

4.2. Read Reference Shifting

During read operations the memory cell threshold volt-

age is compared with a reference voltage. The com-

parator output then produces the logic one level for a cell

threshold higher than the reference and the logic zero

level for a cell threshold lower than the reference.

The test byte provides means to shift the reference volt-

age in positive or negative direction in three steps:

±0.3 V, ±0.6 V, and ±0.9 V.

4.1. Block Programming

Three block program modes can be activated by the test

byte, in conjunction with the memory address loaded

into the memory address register:

During a read operation a positive-shifted reference

voltage establishes a margin test for logic ones,

whereas a negative-shifted reference does so for logic

zeroes. This margin test is performed digitally by IM bus

operationsonly, withouttheneedtoswitchanalogpower

supplies.

memory address

9 8 7 6 5 4 3 2 1 0

1) all bytes are selected : 0 x x x x x x x 0 x (e.g. 0)

7 6 5 4 3 2 1 0

2) all even-numbered

+0.9V:

+0.6V:

+0.3V:

-0.3V :

-0.6V :

-0.9V :

x 0 1 0 x 1 x1

x 0 1 0 x 0 x1

bytes are selected : 0 x x x x x x x 1 0 (e.g. 2)

x 0 1 0 x 1 x

3) all odd-numbered

x 1 1 0 x

x 0 1 1 x

x 1 1 1 x

0 x x x x x x x 1 1 (e.g. 3)

bytes are selected

Thus, programming all selected bytes with the same de-

sired data is done within one programming sequence.

4.3. Charge Pump Disable

The complete sequence is:

Enter Address 516

Bit 3 of the test byte disables the high voltage charge

pump.

NVM 3060

5. Description of the IM Bus

transmission, and sets the CL signal to Low level as well

to switch the first bit on the Data line. Thereafter eight

address bits are transmitted beginning with the LSB.

Data takeover in the slave ICs occurs at the positive

edge of the clock signal. At the end of the address byte

the ID signal goes High, initiating the address compari-

son in the slave circuits. In the addressed slave the IM

bus interface switches over to Data read or write, be-

cause these functions are correlated to the address.

The INTERMETALL Bus (IM Bus for short) has been de-

signed to control the DIGIT 2000 ICs by the CCU Central

Control Unit. Via this bus the CCU can write data to the

ICs or read data from them. This means the CCU acts

as a master whereas all controlled ICs are slaves.

The IM Bus consists of three lines for the signals Ident

(ID), Clock (CL) and Data (D). The clock frequency

range is 50 Hz to 170 kHz. Ident and clock are unidirec-

tional from the CCU to the slave ICs, Data is bidirec-

tional. Bidirectionality is achieved by using open-drain

outputs with On-resistances of 150 Ω maximum. The

2.5 kΩ pull-up resistor common to all outputs is incorpo-

rated in the CCU.

Also controlled by the address the CCU now transmits

eight or sixteen clock pulses, and accordingly one or two

bytes of data are written into the addressed IC or read

out from it, beginning with the LSB.

The completion of the bus transaction is signalled by a

short Low-state pulse of the ID signal. This initiates the

storing of the transferred data.

The timing of a complete IM Bus transaction is shown in

Fig. 5–1. In The non-operative state the signals of all

three bus lines are High. To start a transaction the CCU

sets the ID signal to Low level, indicating an address

It is permissible to interrupt a bus transaction for up to

10 ms.

Ident

Clock

10 11 12 13

Data

Address

LSB

MSBLSB

Data

MSB

Section A

Section B

Section C

IM1

Ident

Clock

Data

Address LSB

Address MSB

Data MSB

Fig. 5–1: IM bus waveforms

NVM 3060

Reprinting is generally permitted, indicating the source. However, our

consent must be obtained in all cases. Information furnished by ITT is

believed to be accurate and reliable. However, no responsibility is as-

sumed by ITT for its use; nor for any infringements of patents or other

rightsofthirdpartieswhichmayresultfromitsuse.Nolicenseisgranted

byimplicationorotherwiseunderanypatentorpatentrightsofITT. The

information and suggestions are given without obligation and cannot

giverisetoanyliability;theydonotindicatetheavailabilityofthecompo-

nentsmentioned.Deliveryofdevelopmentsamplesdoesnotimplyany

obligationofITTtosupplylargeramountsofsuchunitstoafixedterm.To

this effect, only written confirmation of orders will be binding.

ITT Semiconductors Group

World Headquarters

INTERMETALL

Hans-Bunte-Strasse 19

D-7800 Freiburg

Tel. (0761) 517-0, Telex 772 715

Telefax (0761) 517-174

Printed in Germany

by A. Simon & Sohn, Freiburg (2/90)

Order No. 6251-309-2E

End of Data Sheet

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